Lines Matching refs:slicing
1 // RUN: mlir-opt -allow-unregistered-dialect %s -affine-super-vectorizer-test -forward-slicing=true…
2 // RUN: mlir-opt -allow-unregistered-dialect %s -affine-super-vectorizer-test -backward-slicing=tru…
3 // RUN: mlir-opt -allow-unregistered-dialect %s -affine-super-vectorizer-test -slicing=true 2>&1 | …
31 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
32 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
33 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
34 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
35 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
36 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
37 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
38 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
39 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
41 %1 = "slicing-test-op" () : () -> i1
52 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
53 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
54 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
55 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
56 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
57 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
58 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
59 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
60 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
62 %2 = "slicing-test-op" () : () -> i2
72 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
73 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
74 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
75 // FWDBWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
76 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
77 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
78 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
79 // FWDBWD-NEXT: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
80 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
82 %3 = "slicing-test-op" () : () -> i3
92 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
93 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
94 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
95 // FWDBWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
96 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
97 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
98 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
99 // FWDBWD-NEXT: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
100 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
102 %4 = "slicing-test-op" () : () -> i4
110 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
111 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
114 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
115 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
116 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
117 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
118 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
119 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
120 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
121 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
122 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
124 %5 = "slicing-test-op" (%1, %2) : (i1, i2) -> i5
131 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
132 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
135 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
136 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
137 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
138 // FWDBWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
139 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
140 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
141 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
142 // FWDBWD-NEXT: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
143 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
145 %6 = "slicing-test-op" (%3, %4) : (i3, i4) -> i6
151 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
152 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
153 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
156 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
157 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
158 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
159 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
160 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
161 // FWDBWD: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
162 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
163 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
164 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
166 %7 = "slicing-test-op" (%1, %5) : (i1, i5) -> i7
172 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
173 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
174 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
175 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
176 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
177 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
180 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
181 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
182 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
183 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
184 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
185 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
186 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
187 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
188 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
190 %8 = "slicing-test-op" (%5, %6) : (i5, i6) -> i8
195 // BWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
196 // BWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
197 // BWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
198 // BWD-NEXT: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
199 // BWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
200 // BWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
201 // BWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
202 // BWD-NEXT: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
205 // FWDBWD-DAG: %[[v4:.*]] = "slicing-test-op"() : () -> i4
206 // FWDBWD-DAG: %[[v3:.*]] = "slicing-test-op"() : () -> i3
207 // FWDBWD-NEXT: %[[v6:.*]] = "slicing-test-op"(%[[v3]], %[[v4]]) : (i3, i4) -> i6
208 // FWDBWD-DAG: %[[v2:.*]] = "slicing-test-op"() : () -> i2
209 // FWDBWD-DAG: %[[v1:.*]] = "slicing-test-op"() : () -> i1
210 // FWDBWD-NEXT: %[[v5:.*]] = "slicing-test-op"(%[[v1]], %[[v2]]) : (i1, i2) -> i5
211 // FWDBWD-DAG: %[[v8:.*]] = "slicing-test-op"(%[[v5]], %[[v6]]) : (i5, i6) -> i8
212 // FWDBWD-DAG: %[[v7:.*]] = "slicing-test-op"(%[[v1]], %[[v5]]) : (i1, i5) -> i7
213 // FWDBWD-NEXT: %[[v9:.*]] = "slicing-test-op"(%[[v7]], %[[v8]]) : (i7, i8) -> i9
215 %9 = "slicing-test-op" (%7, %8) : (i7, i8) -> i9
237 %b = "slicing-test-op"(%i1): (index) -> index
247 %c = "slicing-test-op"(%i0): (index) -> index
258 %c = "slicing-test-op"(%f): (f32) -> index
263 %d = "slicing-test-op"(%c, %i2): (index, index) -> index
273 %0 = "slicing-test-op"(%arg0, %arg0): (index, index) -> index
282 …// FWD: matched: %{{.*}}:2 = "slicing-test-op"(%arg0, %arg0) : (index, index) -> (index, index) fo…
284 %0:2 = "slicing-test-op"(%arg0, %arg0): (index, index) -> (index, index)