Lines Matching full:generate

70  Generate machine code emitter.
74  Generate registers and register classes info.
78  Generate instruction descriptions.
82  Generate the assembly writer.
86  Generate disassembler.
90  Generate pseudo instruction lowering.
94  Generate a DAG (Directed Acycle Graph) instruction selector.
98  Generate assembly instruction matcher.
102  Generate DFA Packetizer for VLIW targets.
106  Generate a "fast" instruction selector.
110  Generate subtarget enumerations.
114  Generate intrinsic information.
118  Generate target intrinsic information.
122  Generate enhanced disassembly info.