Lines Matching refs:vector_extract
2080 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2085 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
3849 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3865 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3869 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3905 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3907 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3909 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3911 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3913 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3915 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3918 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),
3921 def : Pat<(sext_inreg (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),
3929 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3932 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
4045 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4050 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4056 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
4063 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
4079 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
4081 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
4083 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
4086 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
4088 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
4090 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
4142 // If a lane instruction caught the vector_extract around opNode, we can
4161 // If none did, fallback to the explicit patterns, consuming the vector_extract.
4162 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
4167 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4171 def : Pat<(i32 (vector_extract (insert_subvector undef,
4176 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4180 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4192 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4198 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4204 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4210 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4223 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4229 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4235 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4241 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4598 (vector_extract (v4f32 (fneg V128:$Rm)),
4603 (vector_extract (v4f32 (insert_subvector undef,
4612 (vector_extract (v2f64 (fneg V128:$Rm)),
4671 (vector_extract (v4i32 V128:$Vm),
5174 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5190 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5205 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5211 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5230 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5235 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
6027 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
6028 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
6030 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
6031 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
6033 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
6036 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
6037 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),