2005   const MCInstrDesc &InstDesc = MI.getDesc();  in isOperandLegal()  local
2006   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];  in isOperandLegal()
2027       } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {  in isOperandLegal()
2708   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitUnaryOp()  local
2723   BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitUnaryOp()
2730   BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitUnaryOp()
2762   const MCInstrDesc &InstDesc = get(Opcode);  in splitScalar64BitBinaryOp()  local
2784   MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)  in splitScalar64BitBinaryOp()
2794   MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)  in splitScalar64BitBinaryOp()
2827   const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);  in splitScalar64BitBCNT()  local
2842   BuildMI(MBB, MII, DL, InstDesc, MidReg)  in splitScalar64BitBCNT()
2846   BuildMI(MBB, MII, DL, InstDesc, ResultReg)  in splitScalar64BitBCNT()