Lines Matching refs:b1101
699 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
716 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
752 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
793 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
856 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1411 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1430 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1454 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1482 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1487 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1491 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1681 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1699 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1737 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1780 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1843 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1860 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
4118 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
4120 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
4122 def VADDhd : N3VD<0, 0, 0b01, 0b1101, 0, IIC_VBIND, "vadd", "f16",
4125 def VADDhq : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, "vadd", "f16",
4179 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4181 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4183 def VMULhd : N3VD<1, 0, 0b01, 0b1101, 1, IIC_VFMULD, "vmul", "f16",
4186 def VMULhq : N3VQ<1, 0, 0b01, 0b1101, 1, IIC_VFMULQ, "vmul", "f16",
4255 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4290 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4300 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4303 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4306 def VMLAhd : N3VDMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACD, "vmla", "f16",
4309 def VMLAhq : N3VQMulOp<0, 0, 0b01, 0b1101, 1, IIC_VMACQ, "vmla", "f16",
4530 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4533 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4536 def VMLShd : N3VDMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACD, "vmls", "f16",
4539 def VMLShq : N3VQMulOp<0, 0, 0b11, 0b1101, 1, IIC_VMACQ, "vmls", "f16",
4664 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4666 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4668 def VSUBhd : N3VD<0, 0, 0b11, 0b1101, 0, IIC_VBIND, "vsub", "f16",
4671 def VSUBhq : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, "vsub", "f16",
5125 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
5127 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
5129 def VABDhd : N3VDInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBIND,
5132 def VABDhq : N3VQInt<1, 0, 0b11, 0b1101, 0, N3RegFrm, IIC_VBINQ,
5275 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
5278 def VPADDh : N3VDInt<1, 0, 0b01, 0b1101, 0, N3RegFrm,
6183 def VCVTh2xsd : N2VCvtD<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16",
6185 def VCVTh2xud : N2VCvtD<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16",
6204 def VCVTh2xsq : N2VCvtQ<0, 1, 0b1101, 0, 1, "vcvt", "s16.f16",
6206 def VCVTh2xuq : N2VCvtQ<1, 1, 0b1101, 0, 1, "vcvt", "u16.f16",