Lines Matching refs:b0000

889      let Inst{7-4} = 0b0000;
1086     let Inst{26-23} = 0b0000;
1106     let Inst{26-23} = 0b0000;
1870   let Inst{7-4} = 0b0000;
2160 def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
2161 def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
2162 def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
2163 def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
2164 def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
2165 def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
2212 def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2218 def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2356 defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2544   let Inst{7-4} = 0b0000; // Multiply
2555   let Inst{7-4} = 0b0000; // Multiply
2572 def t2SMULL : T2MulLong<0b000, 0b0000,
2577 def t2UMULL : T2MulLong<0b010, 0b0000,
2584 def t2SMLAL : T2MlaLong<0b100, 0b0000,
2590 def t2UMLAL : T2MlaLong<0b110, 0b0000,
2615   let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2636   let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2657   let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2851             0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2863             0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2875             0, 0b010, 0b0000, (outs rGPR:$Rd),
2884 def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
3140 defm t2TST  : T2I_cmp_irs<0b0000, "tst",
4059   let Inst{3-0} = 0b0000;
4118   let Inst{3-0} = 0b0000;