Lines Matching refs:ExitingBlock
390 MachineBasicBlock *ExitingBlock = getExitingBlock(L); in findInductionRegister() local
391 if (!Header || !Preheader || !Latch || !ExitingBlock) in findInductionRegister()
439 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in findInductionRegister()
558 MachineBasicBlock *ExitingBlock = getExitingBlock(L); in getLoopTripCount() local
559 if (!ExitingBlock) in getLoopTripCount()
586 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in getLoopTripCount()
595 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in getLoopTripCount()
1183 MachineBasicBlock *ExitingBlock = getExitingBlock(L); in convertToHardwareLoop() local
1185 if (ExitingBlock != L->getLoopLatch()) { in convertToHardwareLoop()
1189 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) in convertToHardwareLoop()
1572 MachineBasicBlock *ExitingBlock = getExitingBlock(L); in fixupInductionVariable() local
1574 if (!(Header && Latch && ExitingBlock)) in fixupInductionVariable()
1624 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); in fixupInductionVariable()
1628 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { in fixupInductionVariable()
1821 MachineBasicBlock *ExitingBlock = getExitingBlock(L); in createPreheaderForLoop() local
1830 if (!Latch || !ExitingBlock || Header->hasAddressTaken()) in createPreheaderForLoop()
1842 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) in createPreheaderForLoop()