Lines Matching refs:bits
45 bits<10> offset;
47 bits<16> Inst;
53 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
54 bits<3> rs;
55 bits<7> offset;
57 bits<16> Inst;
64 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
65 bits<5> rs;
67 bits<16> Inst;
75 bits<5> rt;
76 bits<5> rs;
77 bits<16> offset;
79 bits<32> Inst;
88 bits<5> rt;
89 bits<5> rs;
90 bits<16> offset;
92 bits<32> Inst;
100 class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
101 bits<5> imm;
103 bits<16> Inst;
110 class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
111 bits<2> rt;
112 bits<4> addr;
114 bits<16> Inst;
122 class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
123 bits<5> rd;
124 bits<5> rt;
126 bits<32> Inst;
136 class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
137 bits<21> addr;
138 bits<5> hint;
140 bits<32> Inst;
149 class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
150 bits<5> rd;
151 bits<5> rt;
152 bits<5> rs;
154 bits<32> Inst;
164 class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
165 bits<5> rt;
166 bits<5> rs;
167 bits<16> imm16;
169 bits<32> Inst;
177 class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
178 bits<21> addr;
179 bits<5> hint;
180 bits<5> base = addr{20-16};
181 bits<9> offset = addr{8-0};
183 bits<32> Inst;
194 bits<21> addr;
195 bits<5> rt;
196 bits<5> base = addr{20-16};
197 bits<16> offset = addr{15-0};
199 bits<32> Inst;
208 bits<21> addr;
209 bits<5> rt;
210 bits<5> base = addr{20-16};
211 bits<16> offset = addr{15-0};
213 bits<32> Inst;
221 class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
222 bits<21> addr;
223 bits<5> rt;
225 bits<32> Inst;
235 class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
237 bits<5> rd;
238 bits<5> rt;
240 bits<32> Inst;
249 class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
250 bits<5> rt;
251 bits<19> imm;
253 bits<32> Inst;
261 class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
262 bits<5> rt;
263 bits<16> imm;
265 bits<32> Inst;
273 class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
274 bits<5> rd;
275 bits<5> rs;
276 bits<5> rt;
278 bits<32> Inst;
288 class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
289 bits<32> Inst;
299 class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
300 bits<5> rt;
301 bits<5> rd;
302 bits<32> Inst;
312 bits<5> rt;
313 bits<5> rs;
314 bits<3> sel;
315 bits<32> Inst;
327 bits<5> stype;
329 bits<32> Inst;
339 bits<21> addr;
340 bits<5> base = addr{20-16};
341 bits<16> immediate = addr{15-0};
343 bits<32> Inst;
351 class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
352 bits<5> rs;
353 bits<5> rt;
355 bits<32> Inst;
364 class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
365 bits<5> rs;
366 bits<5> rt;
368 bits<32> Inst;
378 class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
379 bits<5> rd;
380 bits<5> rs;
381 bits<5> rt;
382 bits<2> bp;
384 bits<32> Inst;
396 bits<5> rs;
397 bits<5> rt;
398 bits<16> imm;
400 bits<32> Inst;
408 class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
409 bits<5> rd;
410 bits<5> rs;
411 bits<5> rt;
412 bits<2> imm2;
414 bits<32> Inst;
425 class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
426 bits<5> rt;
427 bits<21> addr;
428 bits<5> base = addr{20-16};
429 bits<16> offset = addr{15-0};
431 bits<32> Inst;
439 class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
440 bits<5> rt;
441 bits<21> addr;
442 bits<5> base = addr{20-16};
443 bits<9> offset = addr{8-0};
445 bits<32> Inst;
455 class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
456 bits<5> rt;
457 bits<21> addr;
458 bits<5> base = addr{20-16};
459 bits<9> offset = addr{8-0};
461 bits<32> Inst;
472 bits<5> rt;
473 bits<21> addr;
474 bits<5> base = addr{20-16};
475 bits<16> offset = addr{15-0};
477 bits<32> Inst;
486 bits<5> rt;
487 bits<16> imm16;
489 bits<32> Inst;
497 class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
499 bits<5> rt;
500 bits<16> offset;
502 bits<32> Inst;
510 class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<string instr_asm, bits<6> funct>
512 bits<5> rt;
513 bits<16> offset;
515 bits<32> Inst;
523 class POOL32A_JALRC_FM_MMR6<string instr_asm, bits<10> funct>
525 bits<5> rt;
526 bits<5> rs;
528 bits<32> Inst;
537 class POOL32A_EXT_INS_FM_MMR6<string instr_asm, bits<6> funct>
539 bits<5> rt;
540 bits<5> rs;
541 bits<5> size;
542 bits<5> pos;
544 bits<32> Inst;
554 class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
556 bits<32> Inst;
565 bits<32> Inst;
575 bits<10> code_1;
576 bits<10> code_2;
577 bits<32> Inst;
584 class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
585 bits<32> Inst;
595 class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
597 bits<32> Inst;
598 bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
607 class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
608 bits<5> rd;
609 bits<5> rt;
610 bits<5> shamt;
612 bits<32> Inst;
622 class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
623 bits<5> rt;
624 bits<21> addr;
626 bits<32> Inst;
634 class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
635 bits<3> funct> : MMR6Arch<instr_asm> {
636 bits<5> rt;
637 bits<21> addr;
638 bits<5> base = addr{20-16};
639 bits<9> offset = addr{8-0};
641 bits<32> Inst;
651 class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
653 bits<5> ft;
654 bits<5> fs;
655 bits<5> fd;
657 bits<32> Inst;
668 class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
670 bits<5> ft;
671 bits<5> fs;
672 bits<5> fd;
674 bits<32> Inst;
684 class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
686 bits<5> ft;
687 bits<5> fs;
689 bits<32> Inst;
700 class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
702 bits<5> ft;
703 bits<5> fs;
704 bits<5> fd;
706 bits<32> Inst;
716 class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
718 bits<5> ft;
719 bits<5> fs;
720 bits<5> fd;
722 bits<32> Inst;
732 class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
734 bits<5> ft;
735 bits<5> fs;
737 bits<32> Inst;
747 class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
749 bits<5> ft;
750 bits<5> fs;
752 bits<32> Inst;
762 class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
764 bits<5> ft;
765 bits<5> fs;
767 bits<32> Inst;
778 class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
780 bits<5> ft;
781 bits<5> fs;
783 bits<32> Inst;
795 bits<3> rs;
796 bits<3> rt;
797 bits<3> rd;
799 bits<16> Inst;
809 bits<3> rt;
810 bits<3> rs;
812 bits<16> Inst;
821 bits<3> rt;
822 bits<3> rs;
824 bits<16> Inst;
832 class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
833 bits<3> rt;
834 bits<3> rs;
836 bits<16> Inst;
844 class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
845 bits<4> code_;
846 bits<16> Inst;
854 bits<3> rs;
855 bits<3> rt;
856 bits<3> rd;
858 bits<16> Inst;
867 class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
868 bits<5> rt;
869 bits<5> rs;
871 bits<32> Inst;
880 class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
882 bits<5> ft;
883 bits<5> fs;
885 bits<32> Inst;
896 class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
898 bits<5> fs;
899 bits<5> fd;
901 bits<32> Inst;
911 class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
913 bits<5> ft;
914 bits<5> fs;
915 bits<5> fd;
917 bits<32> Inst;
927 class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
929 bits<5> fs;
930 bits<5> fd;
932 bits<32> Inst;
942 class POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
944 bits<32> Inst;
952 class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
954 bits<5> rt;
955 bits<5> rs;
956 bits<3> sel;
958 bits<32> Inst;
969 class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
971 bits<5> rt;
972 bits<5> fs;
974 bits<32> Inst;
984 class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
986 bits<5> rt;
987 bits<5> impl;
989 bits<32> Inst;
998 class CMP_BRANCH_2R_OFF16_FM_MMR6<string opstr, bits<6> funct>
1000 bits<5> rt;
1001 bits<5> rs;
1002 bits<16> offset;
1004 bits<32> Inst;
1012 class POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
1014 bits<5> rs;
1016 bits<32> Inst;
1025 class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
1026 bits<5> rd;
1027 bits<21> addr;
1028 bits<5> base = addr{20-16};
1029 bits<12> offset = addr{11-0};
1031 bits<32> Inst;
1040 class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
1041 bits<5> rs;
1042 bits<21> offset;
1044 bits<32> Inst;
1051 class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
1053 bits<5> rt;
1054 bits<16> offset;
1056 bits<32> Inst;
1064 class LDWC1_SDWC1_FM_MMR6<string instr_asm, bits<6> funct>
1066 bits<5> ft;
1067 bits<21> addr;
1068 bits<5> base = addr{20-16};
1069 bits<16> offset = addr{15-0};
1071 bits<32> Inst;
1079 class POOL32B_LDWC2_SDWC2_FM_MMR6<string instr_asm, bits<4> funct>
1081 bits<5> rt;
1082 bits<21> addr;
1083 bits<5> base = addr{20-16};
1084 bits<11> offset = addr{10-0};
1086 bits<32> Inst;