Lines Matching refs:Enable
55 "Enable 64-bit instructions">;
59 "Enable 64-bit registers usage for ppc32 [beta]">;
63 "Enable Altivec instructions">;
65 "Enable SPE instructions">;
67 "Enable the MFOCRF instruction">;
69 "Enable the fsqrt instruction">;
71 "Enable the fcpsgn instruction">;
73 "Enable the fre instruction">;
75 "Enable the fres instruction">;
77 "Enable the frsqrte instruction">;
79 "Enable the frsqrtes instruction">;
83 "Enable the stfiwx instruction">;
85 "Enable the lfiwax instruction">;
87 "Enable the fri[mnpz] instructions">;
89 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
91 "Enable the isel instruction">;
93 "Enable the bpermd instruction">;
95 "Enable extended divide instructions">;
97 "Enable the ldbrx instruction">;
99 "Enable the cmpb instruction">;
101 "Enable icbt instruction">;
103 "Enable Book E instructions",
109 "Enable E500/E500mc instructions">;
111 "Enable PPC 4xx instructions">;
113 "Enable PPC 6xx instructions">;
115 "Enable QPX instructions">;
117 "Enable VSX instructions",
120 "Enable POWER8 Altivec instructions",
123 "Enable POWER8 Crypto instructions",
126 "Enable POWER8 vector instructions",
130 "Enable Power8 direct move instructions",
134 "Enable l[bh]arx and st[bh]cx.">;
140 "Enable Hardware Transactional Memory instructions">;
147 "Enable the __float128 data type for IEEE-754R Binary128.",
151 "Enable the popcnt[dw] instructions">;
164 "Enable instructions added in ISA 3.0.">;
166 "Enable POWER9 Altivec instructions",
169 "Enable POWER9 vector instructions",