Lines Matching +full:0 +full:x29
58 ; return i10 + (int)d10 + l1 + g() + vla[0];
66 ; return i10 + (int)d10 + l1 + vla[0];
74 ; return i10 + (int)d10 + l1 + g() + vla[0];
82 ; return i10 + (int)d10 + l1 + vla[0];
87 …uble %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
92 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
93 %add1 = add nsw i32 %add, %l1.0.l1.0.
108 ; CHECK: ldr d[[DARG:[0-9]+]], [sp, #56]
109 ; CHECK: ldr w[[IARG:[0-9]+]], [sp, #40]
111 ; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]
123 ; CHECK-MACHO: stp x29, x30, [sp, #32]
124 ; CHECK-MACHO: add x29, sp, #32
132 ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
133 ; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
135 ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [sp, #12]
137 ; CHECK-MACHO: ldp x29, x30, [sp, #32]
143 declare i32 @g() #0
151 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
152 %add1 = add nsw i32 %add, %l1.0.l1.0.
159 ; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40]
160 ; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24]
162 ; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12]
168 …uble %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
173 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
174 %add1 = add nsw i32 %add, %l1.0.l1.0.
185 ; CHECK: stp x29, x30, [sp, #16]
186 ; CHECK: add x29, sp, #16
189 ; CHECK: and sp, x9, #0xffffffffffffff80
196 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
197 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
199 ; CHECK: ldr w[[ILOC:[0-9]+]], [sp]
202 ; CHECK: sub sp, x29, #16 // =16
203 ; CHECK: ldp x29, x30, [sp, #16]
213 ; CHECK-MACHO: stp x29, x30, [sp, #16]
214 ; CHECK-MACHO: add x29, sp, #16
217 ; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
225 ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
226 ; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
228 ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [sp]
231 ; CHECK-MACHO: sub sp, x29, #16
232 ; CHECK-MACHO: ldp x29, x30, [sp, #16]
244 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
245 %add1 = add nsw i32 %add, %l1.0.l1.0.
251 ; CHECK: stp x29, x30, [sp, #-16]!
252 ; CHECK: mov x29, sp
255 ; CHECK: and sp, x9, #0xffffffffffffff80
257 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
258 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
260 ; CHECK: ldr w[[ILOC:[0-9]+]], [sp]
263 ; CHECK: mov sp, x29
264 ; CHECK: ldp x29, x30, [sp], #16
268 …uble %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
271 %0 = zext i32 %i1 to i64
272 %vla = alloca i32, i64 %0, align 4
275 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
276 %add1 = add nsw i32 %add, %l1.0.l1.0.
289 ; CHECK: stp x29, x30, [sp, #16]
290 ; CHECK: add x29, sp, #16
301 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
302 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
308 ; CHECK: and x9, x9, #0x7fffffff0
309 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
312 ; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-20]
314 ; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
317 ; CHECK: sub sp, x29, #16 // =16
318 ; CHECK: ldp x29, x30, [sp, #16]
328 %0 = zext i32 %i1 to i64
329 %vla = alloca i32, i64 %0, align 4
332 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4
333 %add1 = add nsw i32 %add, %l1.0.l1.0.
341 ; CHECK: stp x29, x30, [sp, #-16]!
342 ; CHECK: mov x29, sp
348 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
349 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
355 ; CHECK: and x9, x9, #0x7fffffff0
356 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
359 ; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4]
361 ; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
364 ; CHECK: mov sp, x29
365 ; CHECK: ldp x29, x30, [sp], #16
369 …uble %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 {
372 %0 = zext i32 %i1 to i64
373 %vla = alloca i32, i64 %0, align 4
376 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
377 %add1 = add nsw i32 %add, %l1.0.l1.0.
391 ; CHECK: stp x29, x30, [sp, #32]
392 ; CHECK: add x29, sp, #32
398 ; CHECK: and sp, x9, #0xffffffffffffff80
408 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
409 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
416 ; CHECK: and x9, x9, #0x7fffffff0
417 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
420 ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
421 ; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
424 ; CHECK: sub sp, x29, #32
425 ; CHECK: ldp x29, x30, [sp, #32]
437 ; CHECK-MACHO: stp x29, x30, [sp, #32]
438 ; CHECK-MACHO: add x29, sp, #32
444 ; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
455 ; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
456 ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
463 ; CHECK-MACHO: and x9, x9, #0x7fffffff0
464 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9
467 ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
468 ; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
471 ; CHECK-MACHO: sub sp, x29, #32
472 ; CHECK-MACHO: ldp x29, x30, [sp, #32]
483 %0 = zext i32 %i1 to i64
484 %vla = alloca i32, i64 %0, align 4
487 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128
488 %add1 = add nsw i32 %add, %l1.0.l1.0.
498 ; CHECK: stp x29, x30, [sp, #16]
499 ; CHECK: add x29, sp, #16
505 ; CHECK: and sp, x9, #0xffffffffffffff80
508 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
509 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
516 ; CHECK: and x9, x9, #0x7fffffff0
517 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
520 ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
521 ; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
524 ; CHECK: sub sp, x29, #16
525 ; CHECK: ldp x29, x30, [sp, #16]
533 ; CHECK-MACHO: stp x29, x30, [sp, #16]
534 ; CHECK-MACHO: add x29, sp, #16
540 ; CHECK-MACHO: and sp, x9, #0xffffffffffffff80
543 ; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
544 ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
551 ; CHECK-MACHO: and x9, x9, #0x7fffffff0
552 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9
555 ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
556 ; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
559 ; CHECK-MACHO: sub sp, x29, #16
560 ; CHECK-MACHO: ldp x29, x30, [sp, #16]
569 %0 = zext i32 %i1 to i64
570 %vla = alloca i32, i64 %0, align 4
573 %l1.0.l1.0. = load volatile i32, i32* %l1, align 32768
574 %add1 = add nsw i32 %add, %l1.0.l1.0.
584 ; CHECK: stp x29, x30, [sp, #16]
585 ; CHECK: add x29, sp, #16
591 ; CHECK: and sp, x9, #0xffffffffffff8000
594 ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24]
595 ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40]
602 ; CHECK: and x9, x9, #0x7fffffff0
603 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
606 ; CHECK: ldr w[[ILOC:[0-9]+]], [x19]
607 ; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
610 ; CHECK: sub sp, x29, #16
611 ; CHECK: ldp x29, x30, [sp, #16]
619 ; CHECK-MACHO: stp x29, x30, [sp, #16]
620 ; CHECK-MACHO: add x29, sp, #16
626 ; CHECK-MACHO: and sp, x9, #0xffffffffffff8000
629 ; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20]
630 ; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32]
637 ; CHECK-MACHO: and x9, x9, #0x7fffffff0
638 ; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9
641 ; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19]
642 ; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]]
645 ; CHECK-MACHO: sub sp, x29, #16
646 ; CHECK-MACHO: ldp x29, x30, [sp, #16]
666 ; CHECK-NOT: 0xffffffffffffffe0
670 ; CHECK: and sp, [[REG]], #0xffffffffffffffe0
692 ; CHECK: and sp, x9, #0xffffffffffffffe0
696 ; CHECK: and sp, [[REG]], #0xffffffffffffffe0
700 attributes #0 = { "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" …
703 !1 = !{!2, !2, i64 0}
704 !2 = !{!"int", !3, i64 0}
705 !3 = !{!"omnipotent char", !4, i64 0}