Lines Matching refs:var8
10 @var8 = global i8 0
17 %old = atomicrmw add i8* @var8, i8 %offset seq_cst
19 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
20 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
97 %old = atomicrmw sub i8* @var8, i8 %offset monotonic
99 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
100 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
177 %old = atomicrmw and i8* @var8, i8 %offset release
179 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
180 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
257 %old = atomicrmw or i8* @var8, i8 %offset seq_cst
259 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
260 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
337 %old = atomicrmw xor i8* @var8, i8 %offset acquire
339 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
340 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
417 %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
419 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
420 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
494 %old = atomicrmw min i8* @var8, i8 %offset acquire
496 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
497 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
591 %old = atomicrmw max i8* @var8, i8 %offset seq_cst
593 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
594 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
689 %old = atomicrmw umin i8* @var8, i8 %offset monotonic
691 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
692 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
785 %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
787 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
788 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
881 %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
885 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
886 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
981 %val = load atomic i8, i8* @var8 monotonic, align 1
983 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
984 ; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
1005 %val = load atomic i8, i8* @var8 acquire, align 1
1007 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
1009 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
1018 %val = load atomic i8, i8* @var8 seq_cst, align 1
1020 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
1022 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
1069 store atomic i8 %val, i8* @var8 monotonic, align 1
1070 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
1071 ; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
1089 store atomic i8 %val, i8* @var8 release, align 1
1091 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
1093 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
1102 store atomic i8 %val, i8* @var8 seq_cst, align 1
1104 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
1106 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8