77   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,  in EmitRegUnitPressure()  argument
192   unsigned NumRCs = RegBank.getRegClasses().size();  in EmitRegUnitPressure()
193   unsigned NumSets = RegBank.getNumRegPressureSets();  in EmitRegUnitPressure()
199   for (const auto &RC : RegBank.getRegClasses()) {  in EmitRegUnitPressure()
206       OS << "    {" << (*Regs.begin())->getWeight(RegBank)  in EmitRegUnitPressure()
207          << ", " << RegBank.getRegUnitSetWeight(RegUnits);  in EmitRegUnitPressure()
218   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
220     if (RegBank.getRegUnit(UnitIdx).Weight > 1)  in EmitRegUnitPressure()
226      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
230     for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
232       const RegUnit &RU = RegBank.getRegUnit(UnitIdx);  in EmitRegUnitPressure()
256     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
271     const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);  in EmitRegUnitPressure()
283   unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();  in EmitRegUnitPressure()
287     ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);  in EmitRegUnitPressure()
291       PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);  in EmitRegUnitPressure()
323      << "  assert(RegUnit < " << RegBank.getNumNativeRegUnits()  in EmitRegUnitPressure()
327   for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();  in EmitRegUnitPressure()
329     OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])  in EmitRegUnitPressure()
648                                               CodeGenRegBank &RegBank,  in emitComposeSubRegIndices()  argument
650   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndices()
718                                                     CodeGenRegBank &RegBank,  in emitComposeSubRegIndexLaneMask()  argument
721   const auto &SubRegIndices = RegBank.getSubRegIndices();  in emitComposeSubRegIndexLaneMask()
816                                CodeGenRegBank &RegBank) {  in runMCDesc()  argument
822   const auto &Regs = RegBank.getRegisters();  in runMCDesc()
824   auto &SubRegIndices = RegBank.getSubRegIndices();  in runMCDesc()
856     Reg.addSubRegsPreOrder(SR, RegBank);  in runMCDesc()
970   for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {  in runMCDesc()
971     ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();  in runMCDesc()
981   const auto &RegisterClasses = RegBank.getRegClasses();  in runMCDesc()
1075      << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "  in runMCDesc()
1092                                      CodeGenRegBank &RegBank) {  in runTargetHeader()  argument
1110   if (!RegBank.getSubRegIndices().empty()) {  in runTargetHeader()
1138   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetHeader()
1161                                    CodeGenRegBank &RegBank){  in runTargetDesc()  argument
1174   const auto &RegisterClasses = RegBank.getRegClasses();  in runTargetDesc()
1175   const auto &SubRegIndices = RegBank.getSubRegIndices();  in runTargetDesc()
1361   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()
1377     emitComposeSubRegIndices(OS, RegBank, ClassName);  in runTargetDesc()
1378     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);  in runTargetDesc()
1413   EmitRegUnitPressure(OS, RegBank, ClassName);  in runTargetDesc()
1434   OS.write_hex(RegBank.CoveringLanes);  in runTargetDesc()
1440      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"  in runTargetDesc()
1459     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()
1470     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1477       RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());  in runTargetDesc()
1478       Covered |= RegBank.computeCoveredRegisters(  in runTargetDesc()
1527   CodeGenRegBank &RegBank = Target.getRegBank();  in run()  local
1528   RegBank.computeDerivedInfo();  in run()
1530   runEnums(OS, Target, RegBank);  in run()
1531   runMCDesc(OS, Target, RegBank);  in run()
1532   runTargetHeader(OS, Target, RegBank);  in run()
1533   runTargetDesc(OS, Target, RegBank);  in run()