490     unsigned lanes0_temp = 0;  in pan_pack_add_isub_v2u16()  local
491     if (lanes0_sz == 16 && ins->swizzle[0][0] == 0 && ins->swizzle[0][1] == 1) lanes0_temp = 0;  in pan_pack_add_isub_v2u16()
492     else if (lanes0_sz == 16 && ins->swizzle[0][0] == 1 && ins->swizzle[0][1] == 0) lanes0_temp = 1;  in pan_pack_add_isub_v2u16()
494     unsigned lanes0 = lanes0_temp;  in pan_pack_add_isub_v2u16()
2065     unsigned lanes0_temp = 0;  in pan_pack_add_isub_v4u8()  local
2066 … && ins->swizzle[0][1] == 1 && ins->swizzle[0][2] == 2 && ins->swizzle[0][3] == 3) lanes0_temp = 0;  in pan_pack_add_isub_v4u8()
2068     unsigned lanes0 = lanes0_temp;  in pan_pack_add_isub_v4u8()
2778     unsigned lanes0_temp = 0;  in pan_pack_add_iadd_v4s8()  local
2779 … && ins->swizzle[0][1] == 1 && ins->swizzle[0][2] == 2 && ins->swizzle[0][3] == 3) lanes0_temp = 0;  in pan_pack_add_iadd_v4s8()
2781     unsigned lanes0 = lanes0_temp;  in pan_pack_add_iadd_v4s8()
3093     unsigned lanes0_temp = 0;  in pan_pack_add_iadd_v2u16()  local
3094     if (lanes0_sz == 16 && ins->swizzle[0][0] == 0 && ins->swizzle[0][1] == 1) lanes0_temp = 0;  in pan_pack_add_iadd_v2u16()
3095     else if (lanes0_sz == 16 && ins->swizzle[0][0] == 1 && ins->swizzle[0][1] == 0) lanes0_temp = 1;  in pan_pack_add_iadd_v2u16()
3097     unsigned lanes0 = lanes0_temp;  in pan_pack_add_iadd_v2u16()
3238     unsigned lanes0_temp = 0;  in pan_pack_add_isub_v2s16()  local
3239     if (lanes0_sz == 16 && ins->swizzle[0][0] == 0 && ins->swizzle[0][1] == 1) lanes0_temp = 0;  in pan_pack_add_isub_v2s16()
3240     else if (lanes0_sz == 16 && ins->swizzle[0][0] == 1 && ins->swizzle[0][1] == 0) lanes0_temp = 1;  in pan_pack_add_isub_v2s16()
3242     unsigned lanes0 = lanes0_temp;  in pan_pack_add_isub_v2s16()
5875     unsigned lanes0_temp = 0;  in pan_pack_add_iadd_v2s16()  local
5876     if (lanes0_sz == 16 && ins->swizzle[0][0] == 0 && ins->swizzle[0][1] == 1) lanes0_temp = 0;  in pan_pack_add_iadd_v2s16()
5877     else if (lanes0_sz == 16 && ins->swizzle[0][0] == 1 && ins->swizzle[0][1] == 0) lanes0_temp = 1;  in pan_pack_add_iadd_v2s16()
5879     unsigned lanes0 = lanes0_temp;  in pan_pack_add_iadd_v2s16()
7255     unsigned lanes0_temp = 0;  in pan_pack_add_isub_v4s8()  local
7256 … && ins->swizzle[0][1] == 1 && ins->swizzle[0][2] == 2 && ins->swizzle[0][3] == 3) lanes0_temp = 0;  in pan_pack_add_isub_v4s8()
7258     unsigned lanes0 = lanes0_temp;  in pan_pack_add_isub_v4s8()
7659     unsigned lanes0_temp = 0;  in pan_pack_add_iadd_v4u8()  local
7660 … && ins->swizzle[0][1] == 1 && ins->swizzle[0][2] == 2 && ins->swizzle[0][3] == 3) lanes0_temp = 0;  in pan_pack_add_iadd_v4u8()
7662     unsigned lanes0 = lanes0_temp;  in pan_pack_add_iadd_v4u8()