35                                       struct radeon_cmdbuf *cs,  in radeon_check_space()  argument
38         if (cs->max_dw - cs->cdw < needed)  in radeon_check_space()
39                 ws->cs_grow(cs, needed);  in radeon_check_space()
40         return cs->cdw + needed;  in radeon_check_space()
43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_config_reg_seq()  argument
46         assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_config_reg_seq()
48         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));  in radeon_set_config_reg_seq()
49         radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);  in radeon_set_config_reg_seq()
52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_config_reg()  argument
54         radeon_set_config_reg_seq(cs, reg, 1);  in radeon_set_config_reg()
55         radeon_emit(cs, value);  in radeon_set_config_reg()
58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_context_reg_seq()  argument
61         assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_context_reg_seq()
63         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));  in radeon_set_context_reg_seq()
64         radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_seq()
67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_context_reg()  argument
69         radeon_set_context_reg_seq(cs, reg, 1);  in radeon_set_context_reg()
70         radeon_emit(cs, value);  in radeon_set_context_reg()
74 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,  in radeon_set_context_reg_idx()  argument
79 	assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_context_reg_idx()
80 	radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));  in radeon_set_context_reg_idx()
81 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_context_reg_idx()
82 	radeon_emit(cs, value);  in radeon_set_context_reg_idx()
85 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs,  in radeon_set_context_reg_rmw()  argument
90 	assert(cs->cdw + 4 <= cs->max_dw);  in radeon_set_context_reg_rmw()
91 	radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));  in radeon_set_context_reg_rmw()
92 	radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);  in radeon_set_context_reg_rmw()
93 	radeon_emit(cs, mask);  in radeon_set_context_reg_rmw()
94 	radeon_emit(cs, value);  in radeon_set_context_reg_rmw()
97 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_sh_reg_seq()  argument
100 	assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_sh_reg_seq()
102 	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));  in radeon_set_sh_reg_seq()
103 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);  in radeon_set_sh_reg_seq()
106 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_sh_reg()  argument
108 	radeon_set_sh_reg_seq(cs, reg, 1);  in radeon_set_sh_reg()
109 	radeon_emit(cs, value);  in radeon_set_sh_reg()
113 					 struct radeon_cmdbuf *cs,  in radeon_set_sh_reg_idx()  argument
118 	assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_sh_reg_idx()
125 	radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_sh_reg_idx()
126 	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_sh_reg_idx()
127 	radeon_emit(cs, value);  in radeon_set_sh_reg_idx()
130 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)  in radeon_set_uconfig_reg_seq()  argument
133 	assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_uconfig_reg_seq()
135 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));  in radeon_set_uconfig_reg_seq()
136 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq()
139 static inline void radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs,  in radeon_set_uconfig_reg_seq_perfctr()  argument
143 	assert(cs->cdw + 2 + num <= cs->max_dw);  in radeon_set_uconfig_reg_seq_perfctr()
145 	radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 1));  in radeon_set_uconfig_reg_seq_perfctr()
146 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);  in radeon_set_uconfig_reg_seq_perfctr()
149 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)  in radeon_set_uconfig_reg()  argument
151 	radeon_set_uconfig_reg_seq(cs, reg, 1);  in radeon_set_uconfig_reg()
152 	radeon_emit(cs, value);  in radeon_set_uconfig_reg()
156 					      struct radeon_cmdbuf *cs,  in radeon_set_uconfig_reg_idx()  argument
161 	assert(cs->cdw + 3 <= cs->max_dw);  in radeon_set_uconfig_reg_idx()
169 	radeon_emit(cs, PKT3(opcode, 1, 0));  in radeon_set_uconfig_reg_idx()
170 	radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));  in radeon_set_uconfig_reg_idx()
171 	radeon_emit(cs, value);  in radeon_set_uconfig_reg_idx()
174 static inline void radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs,  in radeon_set_privileged_config_reg()  argument
179 	assert(cs->cdw + 6 <= cs->max_dw);  in radeon_set_privileged_config_reg()
181 	radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));  in radeon_set_privileged_config_reg()
182 	radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |  in radeon_set_privileged_config_reg()
184 	radeon_emit(cs, value);  in radeon_set_privileged_config_reg()
185 	radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()
186 	radeon_emit(cs, reg >> 2);  in radeon_set_privileged_config_reg()
187 	radeon_emit(cs, 0); /* unused */  in radeon_set_privileged_config_reg()