333 	struct radeon_info *rad_info = &device->physical_device->rad_info;  in radv_fill_sqtt_asic_info()  local
334 	bool has_wave32 = rad_info->chip_class >= GFX10;  in radv_fill_sqtt_asic_info()
347 	if (rad_info->chip_class < GFX9)  in radv_fill_sqtt_asic_info()
351 	if (rad_info->family == CHIP_FIJI || rad_info->chip_class >= GFX9)  in radv_fill_sqtt_asic_info()
354 	chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000;  in radv_fill_sqtt_asic_info()
355 	chunk->trace_memory_clock = rad_info->max_memory_clock * 1000000;  in radv_fill_sqtt_asic_info()
357 	chunk->device_id = rad_info->pci_id;  in radv_fill_sqtt_asic_info()
358 	chunk->device_revision_id = rad_info->pci_rev_id;  in radv_fill_sqtt_asic_info()
359 	chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd *  in radv_fill_sqtt_asic_info()
361 	chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd;  in radv_fill_sqtt_asic_info()
362 	chunk->shader_engines = rad_info->max_se;  in radv_fill_sqtt_asic_info()
363 	chunk->compute_unit_per_shader_engine = rad_info->min_good_cu_per_sa *  in radv_fill_sqtt_asic_info()
364 	                                        rad_info->max_sh_per_se;  in radv_fill_sqtt_asic_info()
365 	chunk->simd_per_compute_unit = rad_info->num_simd_per_compute_unit;  in radv_fill_sqtt_asic_info()
366 	chunk->wavefronts_per_simd = rad_info->max_wave64_per_simd;  in radv_fill_sqtt_asic_info()
368 	chunk->minimum_vgpr_alloc = rad_info->min_wave64_vgpr_alloc;  in radv_fill_sqtt_asic_info()
369 	chunk->vgpr_alloc_granularity = rad_info->wave64_vgpr_alloc_granularity *  in radv_fill_sqtt_asic_info()
371 	chunk->minimum_sgpr_alloc = rad_info->min_sgpr_alloc;  in radv_fill_sqtt_asic_info()
372 	chunk->sgpr_alloc_granularity = rad_info->sgpr_alloc_granularity;  in radv_fill_sqtt_asic_info()
375 	chunk->gpu_type = rad_info->has_dedicated_vram ? SQTT_GPU_TYPE_DISCRETE : SQTT_GPU_TYPE_INTEGRATED;  in radv_fill_sqtt_asic_info()
376 	chunk->gfxip_level = radv_chip_class_to_sqtt_gfxip_level(rad_info->chip_class);  in radv_fill_sqtt_asic_info()
380 	chunk->ce_ram_size = rad_info->ce_ram_size;  in radv_fill_sqtt_asic_info()
384 	chunk->vram_bus_width = rad_info->vram_bit_width;  in radv_fill_sqtt_asic_info()
385 	chunk->vram_size = rad_info->vram_size;  in radv_fill_sqtt_asic_info()
386 	chunk->l2_cache_size = rad_info->l2_cache_size;  in radv_fill_sqtt_asic_info()
387 	chunk->l1_cache_size = rad_info->l1_cache_size;  in radv_fill_sqtt_asic_info()
388 	chunk->lds_size = rad_info->lds_size_per_workgroup;  in radv_fill_sqtt_asic_info()
397 	chunk->gpu_timestamp_frequency = rad_info->clock_crystal_freq * 1000;  in radv_fill_sqtt_asic_info()
398 	chunk->max_shader_core_clock = rad_info->max_shader_clock * 1000000;  in radv_fill_sqtt_asic_info()
399 	chunk->max_memory_clock = rad_info->max_memory_clock * 1000000;  in radv_fill_sqtt_asic_info()
401 	chunk->memory_chip_type = radv_vram_type_to_sqtt_memory_type(rad_info->vram_type);  in radv_fill_sqtt_asic_info()
402 	chunk->lds_granularity = rad_info->lds_granularity;  in radv_fill_sqtt_asic_info()
406 			chunk->cu_mask[se][sa] = rad_info->cu_mask[se][sa];  in radv_fill_sqtt_asic_info()
551 …chunk->sqtt_version = radv_chip_class_to_sqtt_version(device->physical_device->rad_info.chip_class…  in radv_sqtt_fill_sqtt_desc()