Lines Matching refs:cs
38 struct radeon_cmdbuf *cs, in si_write_harvested_raster_configs() argument
54 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
59 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
62 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); in si_write_harvested_raster_configs()
67 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
72 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
77 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
82 struct radeon_cmdbuf *cs) in si_emit_compute() argument
84 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
85 radeon_emit(cs, 0); in si_emit_compute()
86 radeon_emit(cs, 0); in si_emit_compute()
87 radeon_emit(cs, 0); in si_emit_compute()
89 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_emit_compute()
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
97 radeon_set_sh_reg_seq(cs, in si_emit_compute()
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | in si_emit_compute()
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | in si_emit_compute()
107 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2); in si_emit_compute()
108 radeon_emit(cs, bc_va >> 8); in si_emit_compute()
109 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); in si_emit_compute()
114 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY, in si_emit_compute()
119 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0); in si_emit_compute()
120 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0); in si_emit_compute()
121 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0); in si_emit_compute()
122 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0); in si_emit_compute()
123 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0); in si_emit_compute()
124 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); in si_emit_compute()
136 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, in si_emit_compute()
141 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_compute()
155 struct radeon_cmdbuf *cs) in si_set_raster_config() argument
169 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, in si_set_raster_config()
172 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, in si_set_raster_config()
175 si_write_harvested_raster_configs(physical_device, cs, in si_set_raster_config()
183 struct radeon_cmdbuf *cs) in si_emit_graphics() argument
190 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_graphics()
191 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1)); in si_emit_graphics()
192 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1)); in si_emit_graphics()
195 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0)); in si_emit_graphics()
196 radeon_emit(cs, 0); in si_emit_graphics()
200 si_set_raster_config(physical_device, cs); in si_emit_graphics()
202 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); in si_emit_graphics()
204 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); in si_emit_graphics()
208 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); in si_emit_graphics()
209 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); in si_emit_graphics()
213 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); in si_emit_graphics()
214 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_emit_graphics()
215 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); in si_emit_graphics()
219 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); in si_emit_graphics()
221 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0); in si_emit_graphics()
223 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | in si_emit_graphics()
227 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); in si_emit_graphics()
233 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); in si_emit_graphics()
234 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, in si_emit_graphics()
236 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, in si_emit_graphics()
238 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR, in si_emit_graphics()
240 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); in si_emit_graphics()
241 radeon_set_context_reg(cs, R_028034_PA_SC_SCREEN_SCISSOR_BR, in si_emit_graphics()
247 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0); in si_emit_graphics()
248 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0)); in si_emit_graphics()
253 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); in si_emit_graphics()
254 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); in si_emit_graphics()
256 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); in si_emit_graphics()
257 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0); in si_emit_graphics()
258 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); in si_emit_graphics()
259 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); in si_emit_graphics()
260 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0); in si_emit_graphics()
263 radeon_set_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, in si_emit_graphics()
268 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0); in si_emit_graphics()
269 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0); in si_emit_graphics()
270 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0); in si_emit_graphics()
271 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0); in si_emit_graphics()
272 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0); in si_emit_graphics()
273 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0); in si_emit_graphics()
275 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
276 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
277 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0); in si_emit_graphics()
284 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0); in si_emit_graphics()
285 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0); in si_emit_graphics()
286 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0); in si_emit_graphics()
305 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, in si_emit_graphics()
307 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS, in si_emit_graphics()
309 radeon_set_sh_reg_idx(physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS, in si_emit_graphics()
314 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_emit_graphics()
317 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, in si_emit_graphics()
319 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_emit_graphics()
321 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, in si_emit_graphics()
327 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL, in si_emit_graphics()
392 radeon_set_sh_reg_idx(physical_device, cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, in si_emit_graphics()
395 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, in si_emit_graphics()
398 radeon_set_sh_reg_idx(physical_device, cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, in si_emit_graphics()
402 radeon_set_sh_reg_idx(physical_device, cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS, in si_emit_graphics()
407 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, in si_emit_graphics()
421 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL, in si_emit_graphics()
423 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_emit_graphics()
437 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL, in si_emit_graphics()
446 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL, in si_emit_graphics()
455 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0); in si_emit_graphics()
457 radeon_set_sh_reg(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0); in si_emit_graphics()
458 radeon_set_sh_reg(cs, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0); in si_emit_graphics()
459 radeon_set_sh_reg(cs, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0); in si_emit_graphics()
460 radeon_set_sh_reg(cs, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0); in si_emit_graphics()
461 radeon_set_sh_reg(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0); in si_emit_graphics()
462 radeon_set_sh_reg(cs, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0); in si_emit_graphics()
463 radeon_set_sh_reg(cs, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0); in si_emit_graphics()
464 radeon_set_sh_reg(cs, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0); in si_emit_graphics()
465 radeon_set_sh_reg(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0); in si_emit_graphics()
466 radeon_set_sh_reg(cs, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0); in si_emit_graphics()
467 radeon_set_sh_reg(cs, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0); in si_emit_graphics()
468 radeon_set_sh_reg(cs, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0); in si_emit_graphics()
469 radeon_set_sh_reg(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0); in si_emit_graphics()
470 radeon_set_sh_reg(cs, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0); in si_emit_graphics()
471 radeon_set_sh_reg(cs, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0); in si_emit_graphics()
472 radeon_set_sh_reg(cs, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0); in si_emit_graphics()
474 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS, in si_emit_graphics()
477 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0); in si_emit_graphics()
480 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff); in si_emit_graphics()
482 radeon_set_context_reg(cs, R_028848_PA_CL_VRS_CNTL, in si_emit_graphics()
488 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_emit_graphics()
489 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); in si_emit_graphics()
493 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, in si_emit_graphics()
499 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, in si_emit_graphics()
517 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, in si_emit_graphics()
520 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14); in si_emit_graphics()
521 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16); in si_emit_graphics()
527 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); in si_emit_graphics()
529 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI, in si_emit_graphics()
535 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1, in si_emit_graphics()
538 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, in si_emit_graphics()
540 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); in si_emit_graphics()
544 radeon_set_context_reg_seq(cs, R_028A00_PA_SU_POINT_SIZE, 1); in si_emit_graphics()
545 radeon_emit(cs, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); in si_emit_graphics()
546 radeon_set_context_reg_seq(cs, R_028A04_PA_SU_POINT_MINMAX, 1); in si_emit_graphics()
547 radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | in si_emit_graphics()
551 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, in si_emit_graphics()
566 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, in si_emit_graphics()
570 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0, in si_emit_graphics()
579 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL, in si_emit_graphics()
584 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL, in si_emit_graphics()
590 si_emit_compute(device, cs); in si_emit_graphics()
596 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); in cik_create_gfx_config() local
597 if (!cs) in cik_create_gfx_config()
600 si_emit_graphics(device, cs); in cik_create_gfx_config()
602 while (cs->cdw & 7) { in cik_create_gfx_config()
604 radeon_emit(cs, PKT2_NOP_PAD); in cik_create_gfx_config()
606 radeon_emit(cs, PKT3_NOP_PAD); in cik_create_gfx_config()
610 cs->cdw * 4, 4096, in cik_create_gfx_config()
626 memcpy(map, cs->buf, cs->cdw * 4); in cik_create_gfx_config()
629 device->gfx_init_size_dw = cs->cdw; in cik_create_gfx_config()
631 device->ws->cs_destroy(cs); in cik_create_gfx_config()
655 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, in si_write_viewport() argument
661 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE + in si_write_viewport()
669 radeon_emit(cs, fui(scale[0])); in si_write_viewport()
670 radeon_emit(cs, fui(translate[0])); in si_write_viewport()
671 radeon_emit(cs, fui(scale[1])); in si_write_viewport()
672 radeon_emit(cs, fui(translate[1])); in si_write_viewport()
673 radeon_emit(cs, fui(scale[2])); in si_write_viewport()
674 radeon_emit(cs, fui(translate[2])); in si_write_viewport()
677 radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + in si_write_viewport()
682 radeon_emit(cs, fui(zmin)); in si_write_viewport()
683 radeon_emit(cs, fui(zmax)); in si_write_viewport()
714 si_write_scissors(struct radeon_cmdbuf *cs, int first, in si_write_scissors() argument
724 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2); in si_write_scissors()
741 radeon_emit(cs, S_028250_TL_X(scissor.offset.x) | in si_write_scissors()
744 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) | in si_write_scissors()
752 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4); in si_write_scissors()
753 radeon_emit(cs, fui(guardband_y)); in si_write_scissors()
754 radeon_emit(cs, fui(1.0)); in si_write_scissors()
755 radeon_emit(cs, fui(guardband_x)); in si_write_scissors()
756 radeon_emit(cs, fui(1.0)); in si_write_scissors()
928 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, in si_cs_emit_write_event_eop() argument
956 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cs_emit_write_event_eop()
957 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); in si_cs_emit_write_event_eop()
958 radeon_emit(cs, gfx9_eop_bug_va); in si_cs_emit_write_event_eop()
959 radeon_emit(cs, gfx9_eop_bug_va >> 32); in si_cs_emit_write_event_eop()
962 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false)); in si_cs_emit_write_event_eop()
963 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
964 radeon_emit(cs, sel); in si_cs_emit_write_event_eop()
965 radeon_emit(cs, va); /* address lo */ in si_cs_emit_write_event_eop()
966 radeon_emit(cs, va >> 32); /* address hi */ in si_cs_emit_write_event_eop()
967 radeon_emit(cs, new_fence); /* immediate data lo */ in si_cs_emit_write_event_eop()
968 radeon_emit(cs, 0); /* immediate data hi */ in si_cs_emit_write_event_eop()
970 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
979 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
980 radeon_emit(cs, va); in si_cs_emit_write_event_eop()
981 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in si_cs_emit_write_event_eop()
982 radeon_emit(cs, 0); /* immediate data */ in si_cs_emit_write_event_eop()
983 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
986 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in si_cs_emit_write_event_eop()
987 radeon_emit(cs, op); in si_cs_emit_write_event_eop()
988 radeon_emit(cs, va); in si_cs_emit_write_event_eop()
989 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in si_cs_emit_write_event_eop()
990 radeon_emit(cs, new_fence); /* immediate data */ in si_cs_emit_write_event_eop()
991 radeon_emit(cs, 0); /* unused */ in si_cs_emit_write_event_eop()
996 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, in radv_cp_wait_mem() argument
1003 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false)); in radv_cp_wait_mem()
1004 radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1)); in radv_cp_wait_mem()
1005 radeon_emit(cs, va); in radv_cp_wait_mem()
1006 radeon_emit(cs, va >> 32); in radv_cp_wait_mem()
1007 radeon_emit(cs, ref); /* reference value */ in radv_cp_wait_mem()
1008 radeon_emit(cs, mask); /* mask */ in radv_cp_wait_mem()
1009 radeon_emit(cs, 4); /* poll interval */ in radv_cp_wait_mem()
1013 si_emit_acquire_mem(struct radeon_cmdbuf *cs, in si_emit_acquire_mem() argument
1020 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | in si_emit_acquire_mem()
1022 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in si_emit_acquire_mem()
1023 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in si_emit_acquire_mem()
1024 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */ in si_emit_acquire_mem()
1025 radeon_emit(cs, 0); /* CP_COHER_BASE */ in si_emit_acquire_mem()
1026 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in si_emit_acquire_mem()
1027 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in si_emit_acquire_mem()
1030 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false)); in si_emit_acquire_mem()
1031 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in si_emit_acquire_mem()
1032 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in si_emit_acquire_mem()
1033 radeon_emit(cs, 0); /* CP_COHER_BASE */ in si_emit_acquire_mem()
1034 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in si_emit_acquire_mem()
1039 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, in gfx10_cs_emit_cache_flush() argument
1097 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1098 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | in gfx10_cs_emit_cache_flush()
1107 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1108 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | in gfx10_cs_emit_cache_flush()
1130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1131 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
1135 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1136 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
1143 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1144 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); in gfx10_cs_emit_cache_flush()
1180 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, in gfx10_cs_emit_cache_flush()
1193 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, in gfx10_cs_emit_cache_flush()
1199 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1200 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
1209 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in gfx10_cs_emit_cache_flush()
1210 radeon_emit(cs, 0); /* CP_COHER_CNTL */ in gfx10_cs_emit_cache_flush()
1211 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in gfx10_cs_emit_cache_flush()
1212 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx10_cs_emit_cache_flush()
1213 radeon_emit(cs, 0); /* CP_COHER_BASE */ in gfx10_cs_emit_cache_flush()
1214 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in gfx10_cs_emit_cache_flush()
1215 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in gfx10_cs_emit_cache_flush()
1216 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */ in gfx10_cs_emit_cache_flush()
1223 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in gfx10_cs_emit_cache_flush()
1224 radeon_emit(cs, 0); in gfx10_cs_emit_cache_flush()
1230 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1231 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | in gfx10_cs_emit_cache_flush()
1234 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
1235 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | in gfx10_cs_emit_cache_flush()
1241 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, in si_cs_emit_cache_flush() argument
1256 gfx10_cs_emit_cache_flush(cs, chip_class, flush_cnt, flush_va, in si_cs_emit_cache_flush()
1285 si_cs_emit_write_event_eop(cs, in si_cs_emit_cache_flush()
1307 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1308 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1314 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1315 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1321 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1322 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1326 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1327 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1333 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1334 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in si_cs_emit_cache_flush()
1380 si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags, in si_cs_emit_cache_flush()
1385 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va, in si_cs_emit_cache_flush()
1391 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1392 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1397 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1398 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); in si_cs_emit_cache_flush()
1410 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in si_cs_emit_cache_flush()
1411 radeon_emit(cs, 0); in si_cs_emit_cache_flush()
1418 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, in si_cs_emit_cache_flush()
1434 si_emit_acquire_mem(cs, is_mec, in si_cs_emit_cache_flush()
1444 si_emit_acquire_mem(cs, is_mec, in si_cs_emit_cache_flush()
1458 si_emit_acquire_mem(cs, is_mec, chip_class == GFX9, cp_coher_cntl); in si_cs_emit_cache_flush()
1461 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1462 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | in si_cs_emit_cache_flush()
1465 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_cs_emit_cache_flush()
1466 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | in si_cs_emit_cache_flush()
1492 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128); in si_emit_cache_flush()
1494 si_cs_emit_cache_flush(cmd_buffer->cs, in si_emit_cache_flush()
1540 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0)); in si_emit_set_predication_state()
1541 radeon_emit(cmd_buffer->cs, op); in si_emit_set_predication_state()
1542 radeon_emit(cmd_buffer->cs, va); in si_emit_set_predication_state()
1543 radeon_emit(cmd_buffer->cs, va >> 32); in si_emit_set_predication_state()
1545 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0)); in si_emit_set_predication_state()
1546 radeon_emit(cmd_buffer->cs, va); in si_emit_set_predication_state()
1547 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF)); in si_emit_set_predication_state()
1584 struct radeon_cmdbuf *cs = cmd_buffer->cs; in si_emit_cp_dma() local
1589 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 9); in si_emit_cp_dma()
1622 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1623 radeon_emit(cs, header); in si_emit_cp_dma()
1624 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
1625 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */ in si_emit_cp_dma()
1626 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
1627 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */ in si_emit_cp_dma()
1628 radeon_emit(cs, command); in si_emit_cp_dma()
1632 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1633 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
1634 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */ in si_emit_cp_dma()
1635 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
1636 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */ in si_emit_cp_dma()
1637 radeon_emit(cs, command); in si_emit_cp_dma()
1647 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating)); in si_emit_cp_dma()
1648 radeon_emit(cs, 0); in si_emit_cp_dma()
1890 void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) in radv_emit_default_sample_locations() argument
1895 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1896 radeon_emit(cs, (uint32_t)centroid_priority_1x); in radv_emit_default_sample_locations()
1897 radeon_emit(cs, centroid_priority_1x >> 32); in radv_emit_default_sample_locations()
1898 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x); in radv_emit_default_sample_locations()
1899 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x); in radv_emit_default_sample_locations()
1900 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x); in radv_emit_default_sample_locations()
1901 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x); in radv_emit_default_sample_locations()
1904 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1905 radeon_emit(cs, (uint32_t)centroid_priority_2x); in radv_emit_default_sample_locations()
1906 radeon_emit(cs, centroid_priority_2x >> 32); in radv_emit_default_sample_locations()
1907 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x); in radv_emit_default_sample_locations()
1908 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x); in radv_emit_default_sample_locations()
1909 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x); in radv_emit_default_sample_locations()
1910 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x); in radv_emit_default_sample_locations()
1913 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1914 radeon_emit(cs, (uint32_t)centroid_priority_4x); in radv_emit_default_sample_locations()
1915 radeon_emit(cs, centroid_priority_4x >> 32); in radv_emit_default_sample_locations()
1916 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x); in radv_emit_default_sample_locations()
1917 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x); in radv_emit_default_sample_locations()
1918 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x); in radv_emit_default_sample_locations()
1919 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x); in radv_emit_default_sample_locations()
1922 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); in radv_emit_default_sample_locations()
1923 radeon_emit(cs, (uint32_t)centroid_priority_8x); in radv_emit_default_sample_locations()
1924 radeon_emit(cs, centroid_priority_8x >> 32); in radv_emit_default_sample_locations()
1925 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); in radv_emit_default_sample_locations()
1926 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1927 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1928 radeon_emit_array(cs, sample_locs_8x, 4); in radv_emit_default_sample_locations()
1929 radeon_emit_array(cs, sample_locs_8x, 2); in radv_emit_default_sample_locations()