Lines Matching refs:instr
56 static bool is_eligible_mov(struct ir3_instruction *instr, in is_eligible_mov() argument
59 if (is_same_type_mov(instr)) { in is_eligible_mov()
60 struct ir3_register *dst = instr->regs[0]; in is_eligible_mov()
61 struct ir3_register *src = instr->regs[1]; in is_eligible_mov()
152 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n, in lower_immed() argument
161 if (!ir3_valid_flags(instr, n, new_flags)) in lower_immed()
169 bool f_opcode = (is_cat2_float(instr->opc) || in lower_immed()
170 is_cat3_float(instr->opc)) ? true : false; in lower_immed()
235 instr->regs[n + 1] = reg; in lower_immed()
241 unuse(struct ir3_instruction *instr) in unuse() argument
243 debug_assert(instr->use_count > 0); in unuse()
245 if (--instr->use_count == 0) { in unuse()
246 struct ir3_block *block = instr->block; in unuse()
248 instr->barrier_class = 0; in unuse()
249 instr->barrier_conflict = 0; in unuse()
255 debug_assert(block->keeps[i] != instr); in unuse()
266 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags) in try_swap_mad_two_srcs() argument
268 if (!is_mad(instr->opc)) in try_swap_mad_two_srcs()
274 swap(instr->regs[0 + 1], instr->regs[1 + 1]); in try_swap_mad_two_srcs()
286 ir3_valid_flags(instr, 0, new_flags) && in try_swap_mad_two_srcs()
288 ir3_valid_flags(instr, 1, instr->regs[1 + 1]->flags); in try_swap_mad_two_srcs()
292 swap(instr->regs[0 + 1], instr->regs[1 + 1]); in try_swap_mad_two_srcs()
306 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, in reg_cp() argument
311 if (is_eligible_mov(src, instr, true)) { in reg_cp()
318 if (ir3_valid_flags(instr, n, new_flags)) { in reg_cp()
324 reg->instr = ssa(src_reg); in reg_cp()
326 instr->barrier_class |= src->barrier_class; in reg_cp()
327 instr->barrier_conflict |= src->barrier_conflict; in reg_cp()
330 reg->instr->use_count++; in reg_cp()
336 !is_meta(instr)) { in reg_cp()
343 if (!ir3_valid_flags(instr, n, new_flags)) { in reg_cp()
345 if (lower_immed(ctx, instr, n, src_reg, new_flags)) in reg_cp()
355 if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) { in reg_cp()
375 conflicts(instr->address, reg->instr->address)) in reg_cp()
382 if ((opc_cat(instr->opc) == 3) && (n == 2) && in reg_cp()
392 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type)) in reg_cp()
394 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc)) in reg_cp()
398 src_reg = ir3_reg_clone(instr->block->shader, src_reg); in reg_cp()
400 instr->regs[n+1] = src_reg; in reg_cp()
403 ir3_instr_set_address(instr, reg->instr->address); in reg_cp()
409 !conflicts(instr->address, reg->instr->address)) { in reg_cp()
410 src_reg = ir3_reg_clone(instr->block->shader, src_reg); in reg_cp()
412 instr->regs[n+1] = src_reg; in reg_cp()
413 ir3_instr_set_address(instr, reg->instr->address); in reg_cp()
429 debug_assert((opc_cat(instr->opc) == 1) || in reg_cp()
430 (opc_cat(instr->opc) == 6) || in reg_cp()
431 ir3_cat2_int(instr->opc) || in reg_cp()
432 (is_mad(instr->opc) && (n == 0))); in reg_cp()
444 if (ir3_valid_flags(instr, n, new_flags) && in reg_cp()
445 ((instr->opc == OPC_MOV) || in reg_cp()
448 src_reg = ir3_reg_clone(instr->block->shader, src_reg); in reg_cp()
451 instr->regs[n+1] = src_reg; in reg_cp()
454 } else if (lower_immed(ctx, instr, n, src_reg, new_flags)) { in reg_cp()
470 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr) in eliminate_output_mov() argument
472 if (is_eligible_mov(instr, NULL, false)) { in eliminate_output_mov()
473 struct ir3_register *reg = instr->regs[1]; in eliminate_output_mov()
481 return instr; in eliminate_output_mov()
489 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr) in instr_cp() argument
491 if (instr->regs_count == 0) in instr_cp()
494 if (ir3_instr_check_mark(instr)) in instr_cp()
501 foreach_src_n (reg, n, instr) { in instr_cp()
516 if (is_meta(instr) && (src->opc != OPC_MOV)) in instr_cp()
519 progress |= reg_cp(ctx, instr, reg, n); in instr_cp()
524 if (instr->regs[0]->flags & IR3_REG_ARRAY) { in instr_cp()
525 struct ir3_instruction *src = ssa(instr->regs[0]); in instr_cp()
530 if (instr->address) { in instr_cp()
531 instr_cp(ctx, instr->address); in instr_cp()
532 ir3_instr_set_address(instr, eliminate_output_mov(ctx, instr->address)); in instr_cp()
544 if ((instr->opc == OPC_CMPS_S) && in instr_cp()
545 (instr->regs[0]->num == regid(REG_P0, 0)) && in instr_cp()
546 ssa(instr->regs[1]) && in instr_cp()
547 (instr->regs[2]->flags & IR3_REG_IMMED) && in instr_cp()
548 (instr->regs[2]->iim_val == 0) && in instr_cp()
549 (instr->cat2.condition == IR3_COND_NE)) { in instr_cp()
550 struct ir3_instruction *cond = ssa(instr->regs[1]); in instr_cp()
555 instr->opc = cond->opc; in instr_cp()
556 instr->flags = cond->flags; in instr_cp()
557 instr->cat2 = cond->cat2; in instr_cp()
558 ir3_instr_set_address(instr, cond->address); in instr_cp()
559 instr->regs[1] = cond->regs[1]; in instr_cp()
560 instr->regs[2] = cond->regs[2]; in instr_cp()
561 instr->barrier_class |= cond->barrier_class; in instr_cp()
562 instr->barrier_conflict |= cond->barrier_conflict; in instr_cp()
577 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) && in instr_cp()
578 !(instr->flags & IR3_INSTR_B) && in instr_cp()
583 struct ir3_instruction *samp_tex = ssa(instr->regs[1]); in instr_cp()
594 instr->flags &= ~IR3_INSTR_S2EN; in instr_cp()
595 instr->cat5.samp = samp->regs[1]->iim_val; in instr_cp()
596 instr->cat5.tex = tex->regs[1]->iim_val; in instr_cp()
599 instr->regs_count--; in instr_cp()
600 for (unsigned i = 1; i < instr->regs_count; i++) { in instr_cp()
601 instr->regs[i] = instr->regs[i + 1]; in instr_cp()
624 foreach_instr (instr, &block->instr_list) { in ir3_cp()
629 debug_assert(instr->deps_count == 0); in ir3_cp()
631 foreach_ssa_src (src, instr) { in ir3_cp()