Lines Matching refs:instr
44 #define di(instr, fmt, ...) do { if (SCHED_DEBUG) { \ argument
46 ir3_print_instr(instr); \
70 struct ir3_instruction *instr; member
84 schedule(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) in schedule() argument
86 debug_assert(ctx->block == instr->block); in schedule()
90 list_delinit(&instr->node); in schedule()
92 di(instr, "schedule"); in schedule()
94 list_addtail(&instr->node, &instr->block->instr_list); in schedule()
96 struct ir3_postsched_node *n = instr->data; in schedule()
99 if (is_meta(instr) && (instr->opc != OPC_META_TEX_PREFETCH)) in schedule()
102 if (is_sfu(instr)) { in schedule()
104 } else if (check_src_cond(instr, is_sfu)) { in schedule()
110 if (is_tex_or_prefetch(instr)) { in schedule()
112 } else if (check_src_cond(instr, is_tex_or_prefetch)) { in schedule()
126 di(n->instr, "maxdel=%3d ", n->max_delay); in dump_state()
132 di(child->instr, " -> (%d parents) ", child->dag.parent_count); in dump_state()
143 would_sync(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) in would_sync() argument
146 if (check_src_cond(instr, is_sfu)) in would_sync()
151 if (check_src_cond(instr, is_tex_or_prefetch)) in would_sync()
167 if (!is_meta(n->instr)) in choose_instr()
175 di(chosen->instr, "prio: chose (meta)"); in choose_instr()
176 return chosen->instr; in choose_instr()
184 if (!is_input(n->instr)) in choose_instr()
192 di(chosen->instr, "prio: chose (input)"); in choose_instr()
193 return chosen->instr; in choose_instr()
198 unsigned d = ir3_delay_calc(ctx->block, n->instr, false, false); in choose_instr()
203 if (!is_kill(n->instr)) in choose_instr()
211 di(chosen->instr, "csp: chose (kill, hard ready)"); in choose_instr()
212 return chosen->instr; in choose_instr()
217 unsigned d = ir3_delay_calc(ctx->block, n->instr, false, false); in choose_instr()
222 if (!(is_sfu(n->instr) || is_tex(n->instr))) in choose_instr()
230 di(chosen->instr, "csp: chose (sfu/tex, hard ready)"); in choose_instr()
231 return chosen->instr; in choose_instr()
244 if (would_sync(ctx, n->instr)) in choose_instr()
247 unsigned d = ir3_delay_calc(ctx->block, n->instr, true, false); in choose_instr()
257 di(chosen->instr, "csp: chose (soft ready, delay=%u)", delay); in choose_instr()
258 return chosen->instr; in choose_instr()
268 unsigned d = ir3_delay_calc(ctx->block, n->instr, true, false); in choose_instr()
278 di(chosen->instr, "csp: chose (soft ready)"); in choose_instr()
279 return chosen->instr; in choose_instr()
287 unsigned d = ir3_delay_calc(ctx->block, n->instr, false, false); in choose_instr()
297 di(chosen->instr, "csp: chose (hard ready)"); in choose_instr()
298 return chosen->instr; in choose_instr()
312 di(chosen->instr, "csp: chose (leader)"); in choose_instr()
313 return chosen->instr; in choose_instr()
410 foreach_src_n (reg, i, node->instr) { in calculate_deps()
426 unsigned d = ir3_delayslots(dep->instr, node->instr, i, true); in calculate_deps()
433 if (node->instr->address) { in calculate_deps()
434 add_reg_dep(state, node, node->instr->address->regs[0], in calculate_deps()
435 node->instr->address->regs[0]->num, in calculate_deps()
439 if (dest_regs(node->instr) == 0) in calculate_deps()
445 struct ir3_register *reg = node->instr->regs[0]; in calculate_deps()
468 foreach_instr (instr, &ctx->unscheduled_list) { in calculate_forward_deps()
469 calculate_deps(&state, instr->data); in calculate_forward_deps()
482 foreach_instr_rev (instr, &ctx->unscheduled_list) { in calculate_reverse_deps()
483 calculate_deps(&state, instr->data); in calculate_reverse_deps()
488 sched_node_init(struct ir3_postsched_ctx *ctx, struct ir3_instruction *instr) in sched_node_init() argument
494 n->instr = instr; in sched_node_init()
495 instr->data = n; in sched_node_init()
519 foreach_instr (instr, &ctx->unscheduled_list) in sched_dag_init()
520 sched_node_init(ctx, instr); in sched_dag_init()
539 foreach_instr (instr, &ctx->unscheduled_list) { in sched_dag_init()
540 struct ir3_postsched_node *n = instr->data; in sched_dag_init()
542 foreach_ssa_src_n (src, i, instr) { in sched_dag_init()
543 if (src->block != instr->block) in sched_dag_init()
553 if (src->block != instr->block) in sched_dag_init()
559 if (is_kill(instr)) { in sched_dag_init()
560 util_dynarray_append(&kills, struct ir3_instruction *, instr); in sched_dag_init()
561 } else if (is_tex(instr) || is_mem(instr)) { in sched_dag_init()
599 foreach_instr_safe (instr, &ctx->unscheduled_list) { in sched_block()
600 switch (instr->opc) { in sched_block()
604 list_delinit(&instr->node); in sched_block()
622 foreach_instr_safe (instr, &ctx->unscheduled_list) in sched_block()
623 if (instr->opc == OPC_META_INPUT) in sched_block()
624 schedule(ctx, instr); in sched_block()
626 foreach_instr_safe (instr, &ctx->unscheduled_list) in sched_block()
627 if (instr->opc == OPC_META_TEX_PREFETCH) in sched_block()
628 schedule(ctx, instr); in sched_block()
631 struct ir3_instruction *instr = choose_instr(ctx); in sched_block() local
633 unsigned delay = ir3_delay_calc(ctx->block, instr, false, false); in sched_block()
645 schedule(ctx, instr); in sched_block()
653 is_self_mov(struct ir3_instruction *instr) in is_self_mov() argument
655 if (!is_same_type_mov(instr)) in is_self_mov()
658 if (instr->regs[0]->num != instr->regs[1]->num) in is_self_mov()
661 if (instr->regs[0]->flags & IR3_REG_RELATIV) in is_self_mov()
664 if (instr->regs[1]->flags & (IR3_REG_CONST | IR3_REG_IMMED | in is_self_mov()
683 foreach_instr_safe (instr, &block->instr_list) { in cleanup_self_movs()
685 foreach_src (reg, instr) { in cleanup_self_movs()
686 if (!reg->instr) in cleanup_self_movs()
689 if (is_self_mov(reg->instr)) { in cleanup_self_movs()
690 list_delinit(®->instr->node); in cleanup_self_movs()
691 reg->instr = reg->instr->regs[1]->instr; in cleanup_self_movs()
695 for (unsigned i = 0; i < instr->deps_count; i++) { in cleanup_self_movs()
696 if (instr->deps[i] && is_self_mov(instr->deps[i])) { in cleanup_self_movs()
697 list_delinit(&instr->deps[i]->node); in cleanup_self_movs()
698 instr->deps[i] = instr->deps[i]->regs[1]->instr; in cleanup_self_movs()