Lines Matching refs:cs

45 			     struct radeon_cmdbuf *cs,  in radeon_cs_memory_below_limit()  argument
48 vram += cs->used_vram; in radeon_cs_memory_below_limit()
49 gtt += cs->used_gart; in radeon_cs_memory_below_limit()
77 ring->cs, rbo->buf, in radeon_add_to_buffer_list()
108 !radeon_cs_memory_below_limit(rctx->screen, ring->cs, in radeon_add_to_buffer_list_check_mem()
121 struct radeon_cmdbuf *cs = ring->cs; in r600_emit_reloc() local
126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
127 radeon_emit(cs, reloc); in r600_emit_reloc()
131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument
134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument
141 radeon_set_config_reg_seq(cs, reg, 1); in radeon_set_config_reg()
142 radeon_emit(cs, value); in radeon_set_config_reg()
145 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument
148 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg() argument
155 radeon_set_context_reg_seq(cs, reg, 1); in radeon_set_context_reg()
156 radeon_emit(cs, value); in radeon_set_context_reg()
159 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, in radeon_set_context_reg_idx() argument
164 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
166 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
167 radeon_emit(cs, value); in radeon_set_context_reg_idx()
170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() argument
173 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
174 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
175 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2); in radeon_set_sh_reg_seq()
178 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() argument
180 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
181 radeon_emit(cs, value); in radeon_set_sh_reg()
184 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq() argument
187 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
188 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0)); in radeon_set_uconfig_reg_seq()
189 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); in radeon_set_uconfig_reg_seq()
192 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg() argument
194 radeon_set_uconfig_reg_seq(cs, reg, 1); in radeon_set_uconfig_reg()
195 radeon_emit(cs, value); in radeon_set_uconfig_reg()
198 static inline void radeon_set_uconfig_reg_idx(struct radeon_cmdbuf *cs, in radeon_set_uconfig_reg_idx() argument
203 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
204 radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0)); in radeon_set_uconfig_reg_idx()
205 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_uconfig_reg_idx()
206 radeon_emit(cs, value); in radeon_set_uconfig_reg_idx()