661    if (dispatch_width == 8)  in SHADER_TIME_ADD()
681          dispatch_width, stage_abbrev, msg);  in vfail()
714    if (dispatch_width > n) {  in limit_dispatch_width()
1189    int reg_width = dispatch_width / 8;  in vgrf()
1446       for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {  in emit_sampleid_setup()
1447          const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);  in emit_sampleid_setup()
3399    if (dispatch_width >= 16)  in remove_duplicate_mrf_writes()
3868          fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);  in lower_mul_dword_inst()
4297       assert(bld.dispatch_width() <= 16);  in sample_mask_reg()
4300       assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16);  in sample_mask_reg()
4488       for (unsigned i = 0; i < bld.dispatch_width() / 8; i++) {  in lower_fb_write_logical_send()
4541       assert(bld.dispatch_width() == 8);  in lower_fb_write_logical_send()
4602       if (devinfo->gen < 6 && bld.dispatch_width() == 16)  in lower_fb_write_logical_send()
4688         (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8))) {  in lower_sampler_logical_send_gen4()
4698       assert(bld.dispatch_width() == 8);  in lower_sampler_logical_send_gen4()
4733       assert(shadow_c.file != BAD_FILE ? bld.dispatch_width() == 8 :  in lower_sampler_logical_send_gen4()
4734              bld.dispatch_width() == 16);  in lower_sampler_logical_send_gen4()
4744       if (op == SHADER_OPCODE_TEX && bld.dispatch_width() == 8) {  in lower_sampler_logical_send_gen4()
4950    unsigned reg_width = bld.dispatch_width() / 8;  in lower_sampler_logical_send_gen7()
5073       assert(bld.dispatch_width() == 8);  in lower_sampler_logical_send_gen7()
5371           bld.dispatch_width() == inst->exec_size);  in emit_predicate_on_sample_mask()
6820    return !(is_periodic(inst->src[i], lbld.dispatch_width()) ||  in needs_src_copy()
6822              lbld.dispatch_width() <= inst->exec_size)) ||  in needs_src_copy()
6845       const fs_builder cbld = lbld.group(MIN2(lbld.dispatch_width(),  in emit_unzip()
6854    } else if (is_periodic(inst->src[i], lbld.dispatch_width())) {  in emit_unzip()
6888    if (lbld.dispatch_width() > inst->exec_size)  in needs_dst_copy()
6925    assert(lbld_before.dispatch_width() == lbld_after.dispatch_width());  in emit_zip()
6943             lbld_before.group(MIN2(lbld_before.dispatch_width(),  in emit_zip()
6952          lbld_after.group(MIN2(lbld_after.dispatch_width(),  in emit_zip()
7423    if (inst->exec_size != dispatch_width)  in dump_instruction()
7434    const unsigned payload_width = MIN2(16, dispatch_width);  in setup_fs_payload_gen6()
7435    assert(dispatch_width % payload_width == 0);  in setup_fs_payload_gen6()
7441    for (unsigned j = 0; j < dispatch_width / payload_width; j++) {  in setup_fs_payload_gen6()
7446    for (unsigned j = 0; j < dispatch_width / payload_width; j++) {  in setup_fs_payload_gen6()
7610                   stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \  in optimize()
7624                stage_abbrev, dispatch_width, nir->info.name);  in optimize()
7800          inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),  in fixup_3src_null_dest()
7850    const brw_predicate pred = dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H :  in fixup_nomask_control_flow()
7851                               dispatch_width > 8 ? BRW_PREDICATE_ALIGN1_ANY16H :  in fixup_nomask_control_flow()
7917                                        .exec_all().group(dispatch_width, 0);  in fixup_nomask_control_flow()
7925                                       flag_mask(flag, dispatch_width / 8);  in fixup_nomask_control_flow()
8361       assert(dispatch_width == 16);  in run_fs()
8380          const unsigned lower_width = MIN2(dispatch_width, 16);  in run_fs()
8381          for (unsigned i = 0; i < dispatch_width / lower_width; i++) {  in run_fs()
9116 brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width)  in brw_nir_lower_simd()  argument
9119                                  (void *)(uintptr_t)dispatch_width);  in brw_nir_lower_simd()
9127                   unsigned dispatch_width)  in compile_cs_to_nir()  argument
9130    brw_nir_apply_key(shader, compiler, &key->base, dispatch_width, true);  in compile_cs_to_nir()
9132    NIR_PASS_V(shader, brw_nir_lower_simd, dispatch_width);  in compile_cs_to_nir()
9369       prog_data->prog_mask = 1 << (v->dispatch_width / 16);  in brw_compile_cs()
9370       g.generate_code(v->cfg, v->dispatch_width, v->shader_stats,  in brw_compile_cs()