Lines Matching full:16
34 stp x29,x30,[sp,#-16]!
53 eor v0.16b,v0.16b,v0.16b
54 ld1 {v3.16b},[x0],#16
64 tbl v6.16b,{v3.16b},v2.16b
65 ext v5.16b,v0.16b,v3.16b,#12
66 st1 {v3.4s},[x2],#16
67 aese v6.16b,v0.16b
70 eor v3.16b,v3.16b,v5.16b
71 ext v5.16b,v0.16b,v5.16b,#12
72 eor v3.16b,v3.16b,v5.16b
73 ext v5.16b,v0.16b,v5.16b,#12
74 eor v6.16b,v6.16b,v1.16b
75 eor v3.16b,v3.16b,v5.16b
76 shl v1.16b,v1.16b,#1
77 eor v3.16b,v3.16b,v6.16b
82 tbl v6.16b,{v3.16b},v2.16b
83 ext v5.16b,v0.16b,v3.16b,#12
84 st1 {v3.4s},[x2],#16
85 aese v6.16b,v0.16b
87 eor v3.16b,v3.16b,v5.16b
88 ext v5.16b,v0.16b,v5.16b,#12
89 eor v3.16b,v3.16b,v5.16b
90 ext v5.16b,v0.16b,v5.16b,#12
91 eor v6.16b,v6.16b,v1.16b
92 eor v3.16b,v3.16b,v5.16b
93 shl v1.16b,v1.16b,#1
94 eor v3.16b,v3.16b,v6.16b
96 tbl v6.16b,{v3.16b},v2.16b
97 ext v5.16b,v0.16b,v3.16b,#12
98 st1 {v3.4s},[x2],#16
99 aese v6.16b,v0.16b
101 eor v3.16b,v3.16b,v5.16b
102 ext v5.16b,v0.16b,v5.16b,#12
103 eor v3.16b,v3.16b,v5.16b
104 ext v5.16b,v0.16b,v5.16b,#12
105 eor v6.16b,v6.16b,v1.16b
106 eor v3.16b,v3.16b,v5.16b
107 eor v3.16b,v3.16b,v6.16b
118 ld1 {v4.16b},[x0]
121 st1 {v3.4s},[x2],#16
124 tbl v6.16b,{v4.16b},v2.16b
125 ext v5.16b,v0.16b,v3.16b,#12
126 st1 {v4.4s},[x2],#16
127 aese v6.16b,v0.16b
130 eor v3.16b,v3.16b,v5.16b
131 ext v5.16b,v0.16b,v5.16b,#12
132 eor v3.16b,v3.16b,v5.16b
133 ext v5.16b,v0.16b,v5.16b,#12
134 eor v6.16b,v6.16b,v1.16b
135 eor v3.16b,v3.16b,v5.16b
136 shl v1.16b,v1.16b,#1
137 eor v3.16b,v3.16b,v6.16b
138 st1 {v3.4s},[x2],#16
142 ext v5.16b,v0.16b,v4.16b,#12
143 aese v6.16b,v0.16b
145 eor v4.16b,v4.16b,v5.16b
146 ext v5.16b,v0.16b,v5.16b,#12
147 eor v4.16b,v4.16b,v5.16b
148 ext v5.16b,v0.16b,v5.16b,#12
149 eor v4.16b,v4.16b,v5.16b
151 eor v4.16b,v4.16b,v6.16b
160 ldr x29,[sp],#16
170 ld1 {v0.4s},[x2],#16
171 ld1 {v2.16b},[x0]
173 ld1 {v1.4s},[x2],#16
176 aese v2.16b,v0.16b
177 aesmc v2.16b,v2.16b
178 ld1 {v0.4s},[x2],#16
180 aese v2.16b,v1.16b
181 aesmc v2.16b,v2.16b
182 ld1 {v1.4s},[x2],#16
185 aese v2.16b,v0.16b
186 aesmc v2.16b,v2.16b
188 aese v2.16b,v1.16b
189 eor v2.16b,v2.16b,v0.16b
191 st1 {v2.16b},[x1]
201 ld1 {v0.4s},[x2],#16
202 ld1 {v2.16b},[x0]
204 ld1 {v1.4s},[x2],#16
207 aesd v2.16b,v0.16b
208 aesimc v2.16b,v2.16b
209 ld1 {v0.4s},[x2],#16
211 aesd v2.16b,v1.16b
212 aesimc v2.16b,v2.16b
213 ld1 {v1.4s},[x2],#16
216 aesd v2.16b,v0.16b
217 aesimc v2.16b,v2.16b
219 aesd v2.16b,v1.16b
220 eor v2.16b,v2.16b,v0.16b
222 st1 {v2.16b},[x1]
232 stp x29,x30,[sp,#-16]!
241 mov x12,#16
260 // could write to v1.16b and v18.16b directly, but that trips this bugs.
261 // We write to v6.16b and copy to the final register as a workaround.
269 orr v6.16b,v0.16b,v0.16b
273 orr v1.16b,v6.16b,v6.16b
278 orr v18.16b,v6.16b,v6.16b
283 aese v0.16b,v16.16b
284 aesmc v0.16b,v0.16b
285 aese v1.16b,v16.16b
286 aesmc v1.16b,v1.16b
287 aese v18.16b,v16.16b
288 aesmc v18.16b,v18.16b
289 ld1 {v16.4s},[x7],#16
291 aese v0.16b,v17.16b
292 aesmc v0.16b,v0.16b
293 aese v1.16b,v17.16b
294 aesmc v1.16b,v1.16b
295 aese v18.16b,v17.16b
296 aesmc v18.16b,v18.16b
297 ld1 {v17.4s},[x7],#16
300 aese v0.16b,v16.16b
301 aesmc v4.16b,v0.16b
302 aese v1.16b,v16.16b
303 aesmc v5.16b,v1.16b
304 ld1 {v2.16b},[x0],#16
306 aese v18.16b,v16.16b
307 aesmc v18.16b,v18.16b
308 ld1 {v3.16b},[x0],#16
310 aese v4.16b,v17.16b
311 aesmc v4.16b,v4.16b
312 aese v5.16b,v17.16b
313 aesmc v5.16b,v5.16b
314 ld1 {v19.16b},[x0],#16
316 aese v18.16b,v17.16b
317 aesmc v17.16b,v18.16b
318 aese v4.16b,v20.16b
319 aesmc v4.16b,v4.16b
320 aese v5.16b,v20.16b
321 aesmc v5.16b,v5.16b
322 eor v2.16b,v2.16b,v7.16b
324 aese v17.16b,v20.16b
325 aesmc v17.16b,v17.16b
326 eor v3.16b,v3.16b,v7.16b
328 aese v4.16b,v21.16b
329 aesmc v4.16b,v4.16b
330 aese v5.16b,v21.16b
331 aesmc v5.16b,v5.16b
332 // Note the logic to update v0.16b, v1.16b, and v1.16b is written to work
335 eor v19.16b,v19.16b,v7.16b
337 aese v17.16b,v21.16b
338 aesmc v17.16b,v17.16b
339 orr v0.16b,v6.16b,v6.16b
341 aese v4.16b,v22.16b
342 aesmc v4.16b,v4.16b
345 aese v5.16b,v22.16b
346 aesmc v5.16b,v5.16b
347 orr v1.16b,v6.16b,v6.16b
349 aese v17.16b,v22.16b
350 aesmc v17.16b,v17.16b
351 orr v18.16b,v6.16b,v6.16b
353 aese v4.16b,v23.16b
354 aese v5.16b,v23.16b
355 aese v17.16b,v23.16b
357 eor v2.16b,v2.16b,v4.16b
358 ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
359 st1 {v2.16b},[x1],#16
360 eor v3.16b,v3.16b,v5.16b
362 st1 {v3.16b},[x1],#16
363 eor v19.16b,v19.16b,v17.16b
364 ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
365 st1 {v19.16b},[x1],#16
371 mov x12,#16
375 aese v0.16b,v16.16b
376 aesmc v0.16b,v0.16b
377 aese v1.16b,v16.16b
378 aesmc v1.16b,v1.16b
379 ld1 {v16.4s},[x7],#16
381 aese v0.16b,v17.16b
382 aesmc v0.16b,v0.16b
383 aese v1.16b,v17.16b
384 aesmc v1.16b,v1.16b
385 ld1 {v17.4s},[x7],#16
388 aese v0.16b,v16.16b
389 aesmc v0.16b,v0.16b
390 aese v1.16b,v16.16b
391 aesmc v1.16b,v1.16b
392 aese v0.16b,v17.16b
393 aesmc v0.16b,v0.16b
394 aese v1.16b,v17.16b
395 aesmc v1.16b,v1.16b
396 ld1 {v2.16b},[x0],x12
397 aese v0.16b,v20.16b
398 aesmc v0.16b,v0.16b
399 aese v1.16b,v20.16b
400 aesmc v1.16b,v1.16b
401 ld1 {v3.16b},[x0]
402 aese v0.16b,v21.16b
403 aesmc v0.16b,v0.16b
404 aese v1.16b,v21.16b
405 aesmc v1.16b,v1.16b
406 eor v2.16b,v2.16b,v7.16b
407 aese v0.16b,v22.16b
408 aesmc v0.16b,v0.16b
409 aese v1.16b,v22.16b
410 aesmc v1.16b,v1.16b
411 eor v3.16b,v3.16b,v7.16b
412 aese v0.16b,v23.16b
413 aese v1.16b,v23.16b
416 eor v2.16b,v2.16b,v0.16b
417 eor v3.16b,v3.16b,v1.16b
418 st1 {v2.16b},[x1],#16
420 st1 {v3.16b},[x1]
423 ldr x29,[sp],#16