Lines Matching refs:OpRs
207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs, in emitRsRt() argument
209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt()
219 const Operand *OpRs, const uint32_t Imm, in emitRtRsImm16() argument
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16()
232 const Operand *OpRs, in emitRtRsImm16Rel() argument
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel()
256 const Operand *OpRs, const uint32_t Imm, in emitFtRsImm16() argument
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16()
282 const Operand *OpRs, const Operand *OpRt, in emitRdRsRt() argument
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt()
377 void AssemblerMIPS32::addi(const Operand *OpRt, const Operand *OpRs, in addi() argument
380 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addi"); in addi()
395 void AssemblerMIPS32::addiu(const Operand *OpRt, const Operand *OpRs, in addiu() argument
398 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addiu"); in addiu()
401 void AssemblerMIPS32::addiu(const Operand *OpRt, const Operand *OpRs, in addiu() argument
404 emitRtRsImm16Rel(Opcode, OpRt, OpRs, OpImm, Reloc, "addiu"); in addiu()
407 void AssemblerMIPS32::addu(const Operand *OpRd, const Operand *OpRs, in addu() argument
410 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "addu"); in addu()
413 void AssemblerMIPS32::and_(const Operand *OpRd, const Operand *OpRs, in and_() argument
416 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "and"); in and_()
419 void AssemblerMIPS32::andi(const Operand *OpRt, const Operand *OpRs, in andi() argument
422 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "andi"); in andi()
525 void AssemblerMIPS32::clz(const Operand *OpRd, const Operand *OpRs) { in clz() argument
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz()
565 void AssemblerMIPS32::div(const Operand *OpRs, const Operand *OpRt) { in div() argument
567 emitRsRt(Opcode, OpRs, OpRt, "div"); in div()
582 void AssemblerMIPS32::divu(const Operand *OpRs, const Operand *OpRt) { in divu() argument
584 emitRsRt(Opcode, OpRs, OpRt, "divu"); in divu()
654 void AssemblerMIPS32::jalr(const Operand *OpRs, const Operand *OpRd) { in jalr() argument
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr()
796 void AssemblerMIPS32::move(const Operand *OpRd, const Operand *OpRs) { in move() argument
799 const Type SrcType = OpRs->getType(); in move()
804 mtc1(OpRs, OpRd); in move()
806 mfc1(OpRd, OpRs); in move()
811 mov_s(OpRd, OpRs); in move()
814 mov_d(OpRd, OpRs); in move()
822 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move()
837 void AssemblerMIPS32::movf(const Operand *OpRd, const Operand *OpRs, in movf() argument
841 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf()
854 void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs, in movn() argument
857 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn"); in movn()
872 void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs, in movt() argument
876 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt()
895 void AssemblerMIPS32::movz(const Operand *OpRd, const Operand *OpRs, in movz() argument
898 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movz"); in movz()
912 void AssemblerMIPS32::mthi(const Operand *OpRs) { in mthi() argument
914 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mthi"); in mthi()
919 void AssemblerMIPS32::mtlo(const Operand *OpRs) { in mtlo() argument
921 IValueT Rs = encodeGPRegister(OpRs, "Rs", "mtlo"); in mtlo()
926 void AssemblerMIPS32::mul(const Operand *OpRd, const Operand *OpRs, in mul() argument
929 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "mul"); in mul()
944 void AssemblerMIPS32::mult(const Operand *OpRs, const Operand *OpRt) { in mult() argument
946 emitRsRt(Opcode, OpRs, OpRt, "mult"); in mult()
949 void AssemblerMIPS32::multu(const Operand *OpRs, const Operand *OpRt) { in multu() argument
951 emitRsRt(Opcode, OpRs, OpRt, "multu"); in multu()
954 void AssemblerMIPS32::nor(const Operand *OpRd, const Operand *OpRs, in nor() argument
957 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor"); in nor()
960 void AssemblerMIPS32::or_(const Operand *OpRd, const Operand *OpRs, in or_() argument
963 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or"); in or_()
966 void AssemblerMIPS32::ori(const Operand *OpRt, const Operand *OpRs, in ori() argument
969 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori"); in ori()
991 const Operand *OpRs) { in sllv() argument
993 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv"); in sllv()
996 void AssemblerMIPS32::slt(const Operand *OpRd, const Operand *OpRs, in slt() argument
999 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "slt"); in slt()
1002 void AssemblerMIPS32::slti(const Operand *OpRt, const Operand *OpRs, in slti() argument
1005 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "slti"); in slti()
1008 void AssemblerMIPS32::sltu(const Operand *OpRd, const Operand *OpRs, in sltu() argument
1011 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sltu"); in sltu()
1014 void AssemblerMIPS32::sltiu(const Operand *OpRt, const Operand *OpRs, in sltiu() argument
1017 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "sltiu"); in sltiu()
1043 const Operand *OpRs) { in srav() argument
1045 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srav"); in srav()
1049 const Operand *OpRs) { in srlv() argument
1051 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv"); in srlv()
1066 void AssemblerMIPS32::subu(const Operand *OpRd, const Operand *OpRs, in subu() argument
1069 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "subu"); in subu()
1154 void AssemblerMIPS32::teq(const Operand *OpRs, const Operand *OpRt, in teq() argument
1157 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "teq"); in teq()
1185 void AssemblerMIPS32::xor_(const Operand *OpRd, const Operand *OpRs, in xor_() argument
1188 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "xor"); in xor_()
1191 void AssemblerMIPS32::xori(const Operand *OpRt, const Operand *OpRs, in xori() argument
1194 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "xori"); in xori()
1197 void AssemblerMIPS32::emitBr(const CondMIPS32::Cond Cond, const Operand *OpRs, in emitBr() argument
1231 if (OpRs != nullptr) { in emitBr()
1232 IValueT Rs = encodeGPRegister(OpRs, "Rs", "branch"); in emitBr()
1246 void AssemblerMIPS32::bcc(const CondMIPS32::Cond Cond, const Operand *OpRs, in bcc() argument
1250 emitBr(Cond, OpRs, OpRt, Dest); in bcc()
1257 emitBr(Cond, OpRs, OpRt, PrevPosition); in bcc()
1261 void AssemblerMIPS32::bzc(const CondMIPS32::Cond Cond, const Operand *OpRs, in bzc() argument
1266 emitBr(Cond, OpRs, OpRtNone, Dest); in bzc()
1273 emitBr(Cond, OpRs, OpRtNone, PrevPosition); in bzc()