Lines Matching refs:instr
65 void Disassembler::VisitAddSubImmediate(const Instruction *instr) { in VisitAddSubImmediate() argument
66 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubImmediate()
68 (rd_is_zr || RnIsZROrSP(instr)) && (instr->GetImmAddSub() == 0) ? true in VisitAddSubImmediate()
75 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
110 Format(instr, mnemonic, form); in VisitAddSubImmediate()
114 void Disassembler::VisitAddSubShifted(const Instruction *instr) { in VisitAddSubShifted() argument
115 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubShifted()
116 bool rn_is_zr = RnIsZROrSP(instr); in VisitAddSubShifted()
122 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
160 Format(instr, mnemonic, form); in VisitAddSubShifted()
164 void Disassembler::VisitAddSubExtended(const Instruction *instr) { in VisitAddSubExtended() argument
165 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubExtended()
167 Extend mode = static_cast<Extend>(instr->GetExtendMode()); in VisitAddSubExtended()
173 switch (instr->Mask(AddSubExtendedMask)) { in VisitAddSubExtended()
203 Format(instr, mnemonic, form); in VisitAddSubExtended()
207 void Disassembler::VisitAddSubWithCarry(const Instruction *instr) { in VisitAddSubWithCarry() argument
208 bool rn_is_zr = RnIsZROrSP(instr); in VisitAddSubWithCarry()
213 switch (instr->Mask(AddSubWithCarryMask)) { in VisitAddSubWithCarry()
243 Format(instr, mnemonic, form); in VisitAddSubWithCarry()
247 void Disassembler::VisitRotateRightIntoFlags(const Instruction *instr) { in VisitRotateRightIntoFlags() argument
251 switch (instr->Mask(RotateRightIntoFlagsMask)) { in VisitRotateRightIntoFlags()
260 Format(instr, mnemonic, form); in VisitRotateRightIntoFlags()
264 void Disassembler::VisitEvaluateIntoFlags(const Instruction *instr) { in VisitEvaluateIntoFlags() argument
268 switch (instr->Mask(EvaluateIntoFlagsMask)) { in VisitEvaluateIntoFlags()
281 Format(instr, mnemonic, form); in VisitEvaluateIntoFlags()
285 void Disassembler::VisitLogicalImmediate(const Instruction *instr) { in VisitLogicalImmediate() argument
286 bool rd_is_zr = RdIsZROrSP(instr); in VisitLogicalImmediate()
287 bool rn_is_zr = RnIsZROrSP(instr); in VisitLogicalImmediate()
291 if (instr->GetImmLogical() == 0) { in VisitLogicalImmediate()
293 Format(instr, "unallocated", "(LogicalImmediate)"); in VisitLogicalImmediate()
297 switch (instr->Mask(LogicalImmediateMask)) { in VisitLogicalImmediate()
306 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; in VisitLogicalImmediate()
307 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->GetImmLogical())) { in VisitLogicalImmediate()
329 Format(instr, mnemonic, form); in VisitLogicalImmediate()
361 void Disassembler::VisitLogicalShifted(const Instruction *instr) { in VisitLogicalShifted() argument
362 bool rd_is_zr = RdIsZROrSP(instr); in VisitLogicalShifted()
363 bool rn_is_zr = RnIsZROrSP(instr); in VisitLogicalShifted()
367 switch (instr->Mask(LogicalShiftedMask)) { in VisitLogicalShifted()
400 if (rn_is_zr && (instr->GetImmDPShift() == 0) && in VisitLogicalShifted()
401 (instr->GetShiftDP() == LSL)) { in VisitLogicalShifted()
420 Format(instr, mnemonic, form); in VisitLogicalShifted()
424 void Disassembler::VisitConditionalCompareRegister(const Instruction *instr) { in VisitConditionalCompareRegister() argument
428 switch (instr->Mask(ConditionalCompareRegisterMask)) { in VisitConditionalCompareRegister()
440 Format(instr, mnemonic, form); in VisitConditionalCompareRegister()
444 void Disassembler::VisitConditionalCompareImmediate(const Instruction *instr) { in VisitConditionalCompareImmediate() argument
448 switch (instr->Mask(ConditionalCompareImmediateMask)) { in VisitConditionalCompareImmediate()
460 Format(instr, mnemonic, form); in VisitConditionalCompareImmediate()
464 void Disassembler::VisitConditionalSelect(const Instruction *instr) { in VisitConditionalSelect() argument
465 bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr)); in VisitConditionalSelect()
466 bool rn_is_rm = (instr->GetRn() == instr->GetRm()); in VisitConditionalSelect()
472 Condition cond = static_cast<Condition>(instr->GetCondition()); in VisitConditionalSelect()
475 switch (instr->Mask(ConditionalSelectMask)) { in VisitConditionalSelect()
516 Format(instr, mnemonic, form); in VisitConditionalSelect()
520 void Disassembler::VisitBitfield(const Instruction *instr) { in VisitBitfield() argument
521 unsigned s = instr->GetImmS(); in VisitBitfield()
522 unsigned r = instr->GetImmR(); in VisitBitfield()
524 ((instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1; in VisitBitfield()
534 switch (instr->Mask(BitfieldMask)) { in VisitBitfield()
545 } else if ((s == 31) && (instr->GetSixtyFourBits() == 1)) { in VisitBitfield()
590 if (instr->GetRn() == kZeroRegCode) { in VisitBitfield()
600 Format(instr, mnemonic, form); in VisitBitfield()
604 void Disassembler::VisitExtract(const Instruction *instr) { in VisitExtract() argument
608 switch (instr->Mask(ExtractMask)) { in VisitExtract()
611 if (instr->GetRn() == instr->GetRm()) { in VisitExtract()
622 Format(instr, mnemonic, form); in VisitExtract()
626 void Disassembler::VisitPCRelAddressing(const Instruction *instr) { in VisitPCRelAddressing() argument
627 switch (instr->Mask(PCRelAddressingMask)) { in VisitPCRelAddressing()
629 Format(instr, "adr", "'Xd, 'AddrPCRelByte"); in VisitPCRelAddressing()
632 Format(instr, "adrp", "'Xd, 'AddrPCRelPage"); in VisitPCRelAddressing()
635 Format(instr, "unimplemented", "(PCRelAddressing)"); in VisitPCRelAddressing()
640 void Disassembler::VisitConditionalBranch(const Instruction *instr) { in VisitConditionalBranch() argument
641 switch (instr->Mask(ConditionalBranchMask)) { in VisitConditionalBranch()
643 Format(instr, "b.'CBrn", "'TImmCond"); in VisitConditionalBranch()
652 const Instruction *instr) { in VisitUnconditionalBranchToRegister() argument
656 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { in VisitUnconditionalBranchToRegister()
667 if (instr->GetRn() == kLinkRegCode) { in VisitUnconditionalBranchToRegister()
717 Format(instr, mnemonic, form); in VisitUnconditionalBranchToRegister()
721 void Disassembler::VisitUnconditionalBranch(const Instruction *instr) { in VisitUnconditionalBranch() argument
725 switch (instr->Mask(UnconditionalBranchMask)) { in VisitUnconditionalBranch()
735 Format(instr, mnemonic, form); in VisitUnconditionalBranch()
739 void Disassembler::VisitDataProcessing1Source(const Instruction *instr) { in VisitDataProcessing1Source() argument
743 switch (instr->Mask(DataProcessing1SourceMask)) { in VisitDataProcessing1Source()
796 Format(instr, mnemonic, form); in VisitDataProcessing1Source()
800 void Disassembler::VisitDataProcessing2Source(const Instruction *instr) { in VisitDataProcessing2Source() argument
805 switch (instr->Mask(DataProcessing2SourceMask)) { in VisitDataProcessing2Source()
851 Format(instr, mnemonic, form); in VisitDataProcessing2Source()
855 void Disassembler::VisitDataProcessing3Source(const Instruction *instr) { in VisitDataProcessing3Source() argument
856 bool ra_is_zr = RaIsZROrSP(instr); in VisitDataProcessing3Source()
864 switch (instr->Mask(DataProcessing3SourceMask)) { in VisitDataProcessing3Source()
930 Format(instr, mnemonic, form); in VisitDataProcessing3Source()
934 void Disassembler::VisitCompareBranch(const Instruction *instr) { in VisitCompareBranch() argument
938 switch (instr->Mask(CompareBranchMask)) { in VisitCompareBranch()
950 Format(instr, mnemonic, form); in VisitCompareBranch()
954 void Disassembler::VisitTestBranch(const Instruction *instr) { in VisitTestBranch() argument
962 switch (instr->Mask(TestBranchMask)) { in VisitTestBranch()
972 Format(instr, mnemonic, form); in VisitTestBranch()
976 void Disassembler::VisitMoveWideImmediate(const Instruction *instr) { in VisitMoveWideImmediate() argument
983 switch (instr->Mask(MoveWideImmediateMask)) { in VisitMoveWideImmediate()
986 if ((instr->GetImmMoveWide()) || (instr->GetShiftMoveWide() == 0)) { in VisitMoveWideImmediate()
987 if ((instr->GetSixtyFourBits() == 0) && in VisitMoveWideImmediate()
988 (instr->GetImmMoveWide() == 0xffff)) { in VisitMoveWideImmediate()
1000 if ((instr->GetImmMoveWide()) || (instr->GetShiftMoveWide() == 0)) in VisitMoveWideImmediate()
1013 Format(instr, mnemonic, form); in VisitMoveWideImmediate()
1042 void Disassembler::VisitLoadStorePreIndex(const Instruction *instr) { in VisitLoadStorePreIndex() argument
1046 switch (instr->Mask(LoadStorePreIndexMask)) { in VisitLoadStorePreIndex()
1055 Format(instr, mnemonic, form); in VisitLoadStorePreIndex()
1059 void Disassembler::VisitLoadStorePostIndex(const Instruction *instr) { in VisitLoadStorePostIndex() argument
1063 switch (instr->Mask(LoadStorePostIndexMask)) { in VisitLoadStorePostIndex()
1072 Format(instr, mnemonic, form); in VisitLoadStorePostIndex()
1076 void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction *instr) { in VisitLoadStoreUnsignedOffset() argument
1080 switch (instr->Mask(LoadStoreUnsignedOffsetMask)) { in VisitLoadStoreUnsignedOffset()
1092 Format(instr, mnemonic, form); in VisitLoadStoreUnsignedOffset()
1096 void Disassembler::VisitLoadStoreRCpcUnscaledOffset(const Instruction *instr) { in VisitLoadStoreRCpcUnscaledOffset() argument
1101 switch (instr->Mask(LoadStoreRCpcUnscaledOffsetMask)) { in VisitLoadStoreRCpcUnscaledOffset()
1151 Format(instr, mnemonic, form); in VisitLoadStoreRCpcUnscaledOffset()
1155 void Disassembler::VisitLoadStoreRegisterOffset(const Instruction *instr) { in VisitLoadStoreRegisterOffset() argument
1159 switch (instr->Mask(LoadStoreRegisterOffsetMask)) { in VisitLoadStoreRegisterOffset()
1171 Format(instr, mnemonic, form); in VisitLoadStoreRegisterOffset()
1175 void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction *instr) { in VisitLoadStoreUnscaledOffset() argument
1186 switch (instr->Mask(LoadStoreUnscaledOffsetMask)) { in VisitLoadStoreUnscaledOffset()
1276 Format(instr, mnemonic, form); in VisitLoadStoreUnscaledOffset()
1280 void Disassembler::VisitLoadLiteral(const Instruction *instr) { in VisitLoadLiteral() argument
1284 switch (instr->Mask(LoadLiteralMask)) { in VisitLoadLiteral()
1313 Format(instr, mnemonic, form); in VisitLoadLiteral()
1330 void Disassembler::VisitLoadStorePairPostIndex(const Instruction *instr) { in VisitLoadStorePairPostIndex() argument
1334 switch (instr->Mask(LoadStorePairPostIndexMask)) { in VisitLoadStorePairPostIndex()
1343 Format(instr, mnemonic, form); in VisitLoadStorePairPostIndex()
1347 void Disassembler::VisitLoadStorePairPreIndex(const Instruction *instr) { in VisitLoadStorePairPreIndex() argument
1351 switch (instr->Mask(LoadStorePairPreIndexMask)) { in VisitLoadStorePairPreIndex()
1360 Format(instr, mnemonic, form); in VisitLoadStorePairPreIndex()
1364 void Disassembler::VisitLoadStorePairOffset(const Instruction *instr) { in VisitLoadStorePairOffset() argument
1368 switch (instr->Mask(LoadStorePairOffsetMask)) { in VisitLoadStorePairOffset()
1377 Format(instr, mnemonic, form); in VisitLoadStorePairOffset()
1381 void Disassembler::VisitLoadStorePairNonTemporal(const Instruction *instr) { in VisitLoadStorePairNonTemporal() argument
1385 switch (instr->Mask(LoadStorePairNonTemporalMask)) { in VisitLoadStorePairNonTemporal()
1429 Format(instr, mnemonic, form); in VisitLoadStorePairNonTemporal()
1501 void Disassembler::VisitLoadStoreExclusive(const Instruction *instr) { in VisitLoadStoreExclusive() argument
1505 switch (instr->Mask(LoadStoreExclusiveMask)) { in VisitLoadStoreExclusive()
1517 switch (instr->Mask(LoadStoreExclusiveMask)) { in VisitLoadStoreExclusive()
1526 if ((instr->GetRs() % 2 == 1) || (instr->GetRt() % 2 == 1)) { in VisitLoadStoreExclusive()
1533 Format(instr, mnemonic, form); in VisitLoadStoreExclusive()
1536 void Disassembler::VisitLoadStorePAC(const Instruction *instr) { in VisitLoadStorePAC() argument
1540 switch (instr->Mask(LoadStorePACMask)) { in VisitLoadStorePAC()
1559 Format(instr, mnemonic, form); in VisitLoadStorePAC()
1572 void Disassembler::VisitAtomicMemory(const Instruction *instr) { in VisitAtomicMemory() argument
1577 switch (instr->Mask(AtomicMemoryMask)) { in VisitAtomicMemory()
1659 switch (instr->Mask(AtomicMemoryMask)) { in VisitAtomicMemory()
1678 unsigned rt = instr->GetRt(); \ in VisitAtomicMemory()
1688 unsigned rt = instr->GetRt(); \ in VisitAtomicMemory()
1705 Format(instr, mnemonic, form); in VisitAtomicMemory()
1709 void Disassembler::VisitFPCompare(const Instruction *instr) { in VisitFPCompare() argument
1714 switch (instr->Mask(FPCompareMask)) { in VisitFPCompare()
1738 Format(instr, mnemonic, form); in VisitFPCompare()
1742 void Disassembler::VisitFPConditionalCompare(const Instruction *instr) { in VisitFPConditionalCompare() argument
1746 switch (instr->Mask(FPConditionalCompareMask)) { in VisitFPConditionalCompare()
1760 Format(instr, mnemonic, form); in VisitFPConditionalCompare()
1764 void Disassembler::VisitFPConditionalSelect(const Instruction *instr) { in VisitFPConditionalSelect() argument
1768 switch (instr->Mask(FPConditionalSelectMask)) { in VisitFPConditionalSelect()
1777 Format(instr, mnemonic, form); in VisitFPConditionalSelect()
1781 void Disassembler::VisitFPDataProcessing1Source(const Instruction *instr) { in VisitFPDataProcessing1Source() argument
1785 switch (instr->Mask(FPDataProcessing1SourceMask)) { in VisitFPDataProcessing1Source()
1841 Format(instr, mnemonic, form); in VisitFPDataProcessing1Source()
1845 void Disassembler::VisitFPDataProcessing2Source(const Instruction *instr) { in VisitFPDataProcessing2Source() argument
1849 switch (instr->Mask(FPDataProcessing2SourceMask)) { in VisitFPDataProcessing2Source()
1869 Format(instr, mnemonic, form); in VisitFPDataProcessing2Source()
1873 void Disassembler::VisitFPDataProcessing3Source(const Instruction *instr) { in VisitFPDataProcessing3Source() argument
1877 switch (instr->Mask(FPDataProcessing3SourceMask)) { in VisitFPDataProcessing3Source()
1892 Format(instr, mnemonic, form); in VisitFPDataProcessing3Source()
1896 void Disassembler::VisitFPImmediate(const Instruction *instr) { in VisitFPImmediate() argument
1899 switch (instr->Mask(FPImmediateMask)) { in VisitFPImmediate()
1915 Format(instr, mnemonic, form); in VisitFPImmediate()
1919 void Disassembler::VisitFPIntegerConvert(const Instruction *instr) { in VisitFPIntegerConvert() argument
1925 switch (instr->Mask(FPIntegerConvertMask)) { in VisitFPIntegerConvert()
2061 Format(instr, mnemonic, form); in VisitFPIntegerConvert()
2065 void Disassembler::VisitFPFixedPointConvert(const Instruction *instr) { in VisitFPFixedPointConvert() argument
2070 switch (instr->Mask(FPFixedPointConvertMask)) { in VisitFPFixedPointConvert()
2108 Format(instr, mnemonic, form); in VisitFPFixedPointConvert()
2127 void Disassembler::VisitSystem(const Instruction *instr) { in VisitSystem() argument
2133 if (instr->GetInstructionBits() == XPACLRI) { in VisitSystem()
2136 } else if (instr->Mask(SystemPStateFMask) == SystemPStateFixed) { in VisitSystem()
2137 switch (instr->Mask(SystemPStateMask)) { in VisitSystem()
2151 } else if (instr->Mask(SystemPAuthFMask) == SystemPAuthFixed) { in VisitSystem()
2152 switch (instr->Mask(SystemPAuthMask)) { in VisitSystem()
2162 } else if (instr->Mask(SystemExclusiveMonitorFMask) == in VisitSystem()
2164 switch (instr->Mask(SystemExclusiveMonitorMask)) { in VisitSystem()
2167 form = (instr->GetCRm() == 0xf) ? NULL : "'IX"; in VisitSystem()
2171 } else if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) { in VisitSystem()
2172 switch (instr->Mask(SystemSysRegMask)) { in VisitSystem()
2184 } else if (instr->Mask(SystemHintFMask) == SystemHintFixed) { in VisitSystem()
2186 switch (instr->GetImmHint()) { in VisitSystem()
2229 } else if (instr->Mask(MemBarrierFMask) == MemBarrierFixed) { in VisitSystem()
2230 switch (instr->Mask(MemBarrierMask)) { in VisitSystem()
2247 } else if (instr->Mask(SystemSysFMask) == SystemSysFixed) { in VisitSystem()
2248 switch (instr->GetSysOp()) { in VisitSystem()
2279 if (instr->GetRt() == 31) { in VisitSystem()
2287 Format(instr, mnemonic, form); in VisitSystem()
2291 void Disassembler::VisitException(const Instruction *instr) { in VisitException() argument
2295 switch (instr->Mask(ExceptionMask)) { in VisitException()
2326 Format(instr, mnemonic, form); in VisitException()
2330 void Disassembler::VisitCrypto2RegSHA(const Instruction *instr) { in VisitCrypto2RegSHA() argument
2331 VisitUnimplemented(instr); in VisitCrypto2RegSHA()
2335 void Disassembler::VisitCrypto3RegSHA(const Instruction *instr) { in VisitCrypto3RegSHA() argument
2336 VisitUnimplemented(instr); in VisitCrypto3RegSHA()
2340 void Disassembler::VisitCryptoAES(const Instruction *instr) { in VisitCryptoAES() argument
2341 VisitUnimplemented(instr); in VisitCryptoAES()
2345 void Disassembler::VisitNEON2RegMisc(const Instruction *instr) { in VisitNEON2RegMisc() argument
2350 NEONFormatDecoder nfd(instr); in VisitNEON2RegMisc()
2360 if (instr->Mask(NEON2RegMiscOpcode) <= NEON_NEG_opcode) { in VisitNEON2RegMisc()
2363 switch (instr->Mask(NEON2RegMiscMask)) { in VisitNEON2RegMisc()
2437 switch (instr->GetFPType()) { in VisitNEON2RegMisc()
2454 switch (instr->Mask(NEON2RegMiscFPMask)) { in VisitNEON2RegMisc()
2462 mnemonic = instr->Mask(NEON_Q) ? "fcvtn2" : "fcvtn"; in VisitNEON2RegMisc()
2467 mnemonic = instr->Mask(NEON_Q) ? "fcvtxn2" : "fcvtxn"; in VisitNEON2RegMisc()
2472 mnemonic = instr->Mask(NEON_Q) ? "fcvtl2" : "fcvtl"; in VisitNEON2RegMisc()
2581 if ((NEON_XTN_opcode <= instr->Mask(NEON2RegMiscOpcode)) && in VisitNEON2RegMisc()
2582 (instr->Mask(NEON2RegMiscOpcode) <= NEON_UQXTN_opcode)) { in VisitNEON2RegMisc()
2586 switch (instr->Mask(NEON2RegMiscMask)) { in VisitNEON2RegMisc()
2603 switch (instr->GetNEONSize()) { in VisitNEON2RegMisc()
2614 Format(instr, "unallocated", "(NEON2RegMisc)"); in VisitNEON2RegMisc()
2618 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form)); in VisitNEON2RegMisc()
2625 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEON2RegMisc()
2628 void Disassembler::VisitNEON2RegMiscFP16(const Instruction *instr) { in VisitNEON2RegMiscFP16() argument
2634 NEONFormatDecoder nfd(instr, &map_half); in VisitNEON2RegMiscFP16()
2636 switch (instr->Mask(NEON2RegMiscFP16Mask)) { in VisitNEON2RegMiscFP16()
2692 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEON2RegMiscFP16()
2696 void Disassembler::VisitNEON3Same(const Instruction *instr) { in VisitNEON3Same() argument
2699 NEONFormatDecoder nfd(instr); in VisitNEON3Same()
2701 if (instr->Mask(NEON3SameLogicalFMask) == NEON3SameLogicalFixed) { in VisitNEON3Same()
2702 switch (instr->Mask(NEON3SameLogicalMask)) { in VisitNEON3Same()
2708 if (instr->GetRm() == instr->GetRn()) { in VisitNEON3Same()
2869 unsigned index = (instr->ExtractBits(15, 11) << 2) | in VisitNEON3Same()
2870 (instr->ExtractBit(23) << 1) | instr->ExtractBit(29); in VisitNEON3Same()
2881 const char *fhm_form = (instr->Mask(NEON_Q) == 0) in VisitNEON3Same()
2884 switch (instr->Mask(NEON3SameFHMMask)) { in VisitNEON3Same()
2908 if (instr->Mask(NEON3SameFPFMask) == NEON3SameFPFixed) { in VisitNEON3Same()
2912 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEON3Same()
2915 void Disassembler::VisitNEON3SameFP16(const Instruction *instr) { in VisitNEON3SameFP16() argument
2919 NEONFormatDecoder nfd(instr); in VisitNEON3SameFP16()
2922 switch (instr->Mask(NEON3SameFP16Mask)) { in VisitNEON3SameFP16()
2956 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEON3SameFP16()
2959 void Disassembler::VisitNEON3SameExtra(const Instruction *instr) { in VisitNEON3SameExtra() argument
2965 NEONFormatDecoder nfd(instr); in VisitNEON3SameExtra()
2967 if (instr->Mask(NEON3SameExtraFCMLAMask) == NEON_FCMLA) { in VisitNEON3SameExtra()
2970 } else if (instr->Mask(NEON3SameExtraFCADDMask) == NEON_FCADD) { in VisitNEON3SameExtra()
2975 switch (instr->Mask(NEON3SameExtraMask)) { in VisitNEON3SameExtra()
2995 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEON3SameExtra()
2999 void Disassembler::VisitNEON3Different(const Instruction *instr) { in VisitNEON3Different() argument
3003 NEONFormatDecoder nfd(instr); in VisitNEON3Different()
3007 switch (instr->Mask(NEON3DifferentMask) & ~NEON_Q) { in VisitNEON3Different()
3101 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form)); in VisitNEON3Different()
3105 void Disassembler::VisitNEONAcrossLanes(const Instruction *instr) { in VisitNEONAcrossLanes() argument
3112 NEONFormatDecoder nfd(instr, in VisitNEONAcrossLanes()
3116 if (instr->Mask(NEONAcrossLanesFP16FMask) == NEONAcrossLanesFP16Fixed) { in VisitNEONAcrossLanes()
3120 switch (instr->Mask(NEONAcrossLanesFP16Mask)) { in VisitNEONAcrossLanes()
3134 } else if (instr->Mask(NEONAcrossLanesFPFMask) == NEONAcrossLanesFPFixed) { in VisitNEONAcrossLanes()
3137 switch (instr->Mask(NEONAcrossLanesFPMask)) { in VisitNEONAcrossLanes()
3154 } else if (instr->Mask(NEONAcrossLanesFMask) == NEONAcrossLanesFixed) { in VisitNEONAcrossLanes()
3155 switch (instr->Mask(NEONAcrossLanesMask)) { in VisitNEONAcrossLanes()
3186 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONAcrossLanes()
3188 Format(instr, in VisitNEONAcrossLanes()
3197 void Disassembler::VisitNEONByIndexedElement(const Instruction *instr) { in VisitNEONByIndexedElement() argument
3214 NEONFormatDecoder nfd(instr, in VisitNEONByIndexedElement()
3219 switch (instr->Mask(NEONByIndexedElementMask)) { in VisitNEONByIndexedElement()
3288 switch (instr->Mask(NEONByIndexedElementFPLongMask)) { in VisitNEONByIndexedElement()
3306 switch (instr->Mask(NEONByIndexedElementFPMask)) { in VisitNEONByIndexedElement()
3340 switch (instr->Mask(NEONByIndexedElementFPComplexMask)) { in VisitNEONByIndexedElement()
3354 form = (instr->Mask(NEON_Q) == 0) in VisitNEONByIndexedElement()
3357 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONByIndexedElement()
3361 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONByIndexedElement()
3363 Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form)); in VisitNEONByIndexedElement()
3366 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONByIndexedElement()
3370 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONByIndexedElement()
3373 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONByIndexedElement()
3378 void Disassembler::VisitNEONCopy(const Instruction *instr) { in VisitNEONCopy() argument
3382 NEONFormatDecoder nfd(instr, in VisitNEONCopy()
3386 if (instr->Mask(NEONCopyInsElementMask) == NEON_INS_ELEMENT) { in VisitNEONCopy()
3390 } else if (instr->Mask(NEONCopyInsGeneralMask) == NEON_INS_GENERAL) { in VisitNEONCopy()
3398 } else if (instr->Mask(NEONCopyUmovMask) == NEON_UMOV) { in VisitNEONCopy()
3399 if (instr->Mask(NEON_Q) || ((instr->GetImmNEON5() & 7) == 4)) { in VisitNEONCopy()
3410 } else if (instr->Mask(NEONCopySmovMask) == NEON_SMOV) { in VisitNEONCopy()
3414 } else if (instr->Mask(NEONCopyDupElementMask) == NEON_DUP_ELEMENT) { in VisitNEONCopy()
3417 } else if (instr->Mask(NEONCopyDupGeneralMask) == NEON_DUP_GENERAL) { in VisitNEONCopy()
3425 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONCopy()
3429 void Disassembler::VisitNEONExtract(const Instruction *instr) { in VisitNEONExtract() argument
3432 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap()); in VisitNEONExtract()
3433 if (instr->Mask(NEONExtractMask) == NEON_EXT) { in VisitNEONExtract()
3437 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONExtract()
3441 void Disassembler::VisitNEONLoadStoreMultiStruct(const Instruction *instr) { in VisitNEONLoadStoreMultiStruct() argument
3448 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap()); in VisitNEONLoadStoreMultiStruct()
3450 switch (instr->Mask(NEONLoadStoreMultiStructMask)) { in VisitNEONLoadStoreMultiStruct()
3513 switch (instr->Mask(NEONLoadStoreMultiStructMask)) { in VisitNEONLoadStoreMultiStruct()
3521 allocated = (instr->GetNEONQ() != 0) || (instr->GetNEONLSSize() != 3); in VisitNEONLoadStoreMultiStruct()
3534 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONLoadStoreMultiStruct()
3539 const Instruction *instr) { in VisitNEONLoadStoreMultiStructPostIndex() argument
3547 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap()); in VisitNEONLoadStoreMultiStructPostIndex()
3549 switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) { in VisitNEONLoadStoreMultiStructPostIndex()
3612 switch (instr->Mask(NEONLoadStoreMultiStructPostIndexMask)) { in VisitNEONLoadStoreMultiStructPostIndex()
3620 allocated = (instr->GetNEONQ() != 0) || (instr->GetNEONLSSize() != 3); in VisitNEONLoadStoreMultiStructPostIndex()
3633 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONLoadStoreMultiStructPostIndex()
3637 void Disassembler::VisitNEONLoadStoreSingleStruct(const Instruction *instr) { in VisitNEONLoadStoreSingleStruct() argument
3645 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap()); in VisitNEONLoadStoreSingleStruct()
3647 switch (instr->Mask(NEONLoadStoreSingleStructMask)) { in VisitNEONLoadStoreSingleStruct()
3659 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d; in VisitNEONLoadStoreSingleStruct()
3672 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d; in VisitNEONLoadStoreSingleStruct()
3680 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStruct()
3685 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStruct()
3692 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStruct()
3693 if ((instr->GetNEONLSSize() & 1) == 0) { in VisitNEONLoadStoreSingleStruct()
3705 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStruct()
3710 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStruct()
3715 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStruct()
3716 if ((instr->GetNEONLSSize() & 1) == 0) { in VisitNEONLoadStoreSingleStruct()
3728 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStruct()
3733 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStruct()
3740 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStruct()
3741 if ((instr->GetNEONLSSize() & 1) == 0) { in VisitNEONLoadStoreSingleStruct()
3757 switch (instr->Mask(NEONLoadStoreSingleStructMask)) { in VisitNEONLoadStoreSingleStruct()
3767 allocated = ((instr->GetNEONLSSize() & 1) == 0); in VisitNEONLoadStoreSingleStruct()
3778 allocated = (instr->GetNEONLSSize() <= 1) && in VisitNEONLoadStoreSingleStruct()
3779 ((instr->GetNEONLSSize() == 0) || (instr->GetNEONS() == 0)); in VisitNEONLoadStoreSingleStruct()
3786 allocated = (instr->GetNEONS() == 0); in VisitNEONLoadStoreSingleStruct()
3799 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONLoadStoreSingleStruct()
3804 const Instruction *instr) { in VisitNEONLoadStoreSingleStructPostIndex() argument
3812 NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap()); in VisitNEONLoadStoreSingleStructPostIndex()
3814 switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) { in VisitNEONLoadStoreSingleStructPostIndex()
3826 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d; in VisitNEONLoadStoreSingleStructPostIndex()
3839 form = ((instr->GetNEONLSSize() & 1) == 0) ? form_1s : form_1d; in VisitNEONLoadStoreSingleStructPostIndex()
3847 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStructPostIndex()
3852 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStructPostIndex()
3857 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld2" : "st2"; in VisitNEONLoadStoreSingleStructPostIndex()
3858 if ((instr->GetNEONLSSize() & 1) == 0) in VisitNEONLoadStoreSingleStructPostIndex()
3869 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStructPostIndex()
3874 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStructPostIndex()
3879 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld3" : "st3"; in VisitNEONLoadStoreSingleStructPostIndex()
3880 if ((instr->GetNEONLSSize() & 1) == 0) in VisitNEONLoadStoreSingleStructPostIndex()
3891 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStructPostIndex()
3896 mnemonic = (instr->GetLdStXLoad()) == 1 ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStructPostIndex()
3901 mnemonic = (instr->GetLdStXLoad() == 1) ? "ld4" : "st4"; in VisitNEONLoadStoreSingleStructPostIndex()
3902 if ((instr->GetNEONLSSize() & 1) == 0) in VisitNEONLoadStoreSingleStructPostIndex()
3917 switch (instr->Mask(NEONLoadStoreSingleStructPostIndexMask)) { in VisitNEONLoadStoreSingleStructPostIndex()
3927 allocated = ((instr->GetNEONLSSize() & 1) == 0); in VisitNEONLoadStoreSingleStructPostIndex()
3938 allocated = (instr->GetNEONLSSize() <= 1) && in VisitNEONLoadStoreSingleStructPostIndex()
3939 ((instr->GetNEONLSSize() == 0) || (instr->GetNEONS() == 0)); in VisitNEONLoadStoreSingleStructPostIndex()
3946 allocated = (instr->GetNEONS() == 0); in VisitNEONLoadStoreSingleStructPostIndex()
3959 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONLoadStoreSingleStructPostIndex()
3963 void Disassembler::VisitNEONModifiedImmediate(const Instruction *instr) { in VisitNEONModifiedImmediate() argument
3967 int half_enc = instr->ExtractBit(11); in VisitNEONModifiedImmediate()
3968 int cmode = instr->GetNEONCmode(); in VisitNEONModifiedImmediate()
3973 int q = instr->GetNEONQ(); in VisitNEONModifiedImmediate()
3974 int op = instr->GetNEONModImmOp(); in VisitNEONModifiedImmediate()
3979 NEONFormatDecoder nfd(instr, &map_b); in VisitNEONModifiedImmediate()
4025 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONModifiedImmediate()
4029 void Disassembler::VisitNEONScalar2RegMisc(const Instruction *instr) { in VisitNEONScalar2RegMisc() argument
4035 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap()); in VisitNEONScalar2RegMisc()
4037 if (instr->Mask(NEON2RegMiscOpcode) <= NEON_NEG_scalar_opcode) { in VisitNEONScalar2RegMisc()
4040 switch (instr->Mask(NEONScalar2RegMiscMask)) { in VisitNEONScalar2RegMisc()
4086 switch (instr->Mask(NEONScalar2RegMiscFPMask)) { in VisitNEONScalar2RegMisc()
4159 switch (instr->Mask(NEONScalar2RegMiscMask)) { in VisitNEONScalar2RegMisc()
4174 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form)); in VisitNEONScalar2RegMisc()
4177 void Disassembler::VisitNEONScalar2RegMiscFP16(const Instruction *instr) { in VisitNEONScalar2RegMiscFP16() argument
4182 switch (instr->Mask(NEONScalar2RegMiscFP16Mask)) { in VisitNEONScalar2RegMiscFP16()
4220 Format(instr, mnemonic, form); in VisitNEONScalar2RegMiscFP16()
4224 void Disassembler::VisitNEONScalar3Diff(const Instruction *instr) { in VisitNEONScalar3Diff() argument
4227 NEONFormatDecoder nfd(instr, in VisitNEONScalar3Diff()
4231 switch (instr->Mask(NEONScalar3DiffMask)) { in VisitNEONScalar3Diff()
4244 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form)); in VisitNEONScalar3Diff()
4248 void Disassembler::VisitNEONScalar3Same(const Instruction *instr) { in VisitNEONScalar3Same() argument
4251 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap()); in VisitNEONScalar3Same()
4253 if (instr->Mask(NEONScalar3SameFPFMask) == NEONScalar3SameFPFixed) { in VisitNEONScalar3Same()
4255 switch (instr->Mask(NEONScalar3SameFPMask)) { in VisitNEONScalar3Same()
4287 switch (instr->Mask(NEONScalar3SameMask)) { in VisitNEONScalar3Same()
4358 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form)); in VisitNEONScalar3Same()
4361 void Disassembler::VisitNEONScalar3SameFP16(const Instruction *instr) { in VisitNEONScalar3SameFP16() argument
4365 switch (instr->Mask(NEONScalar3SameFP16Mask)) { in VisitNEONScalar3SameFP16()
4396 Format(instr, mnemonic, form); in VisitNEONScalar3SameFP16()
4399 void Disassembler::VisitNEONScalar3SameExtra(const Instruction *instr) { in VisitNEONScalar3SameExtra() argument
4402 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap()); in VisitNEONScalar3SameExtra()
4404 switch (instr->Mask(NEONScalar3SameExtraMask)) { in VisitNEONScalar3SameExtra()
4414 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form)); in VisitNEONScalar3SameExtra()
4418 void Disassembler::VisitNEONScalarByIndexedElement(const Instruction *instr) { in VisitNEONScalarByIndexedElement() argument
4422 NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap()); in VisitNEONScalarByIndexedElement()
4425 switch (instr->Mask(NEONScalarByIndexedElementMask)) { in VisitNEONScalarByIndexedElement()
4452 switch (instr->Mask(NEONScalarByIndexedElementFPMask)) { in VisitNEONScalarByIndexedElement()
4490 Format(instr, in VisitNEONScalarByIndexedElement()
4496 void Disassembler::VisitNEONScalarCopy(const Instruction *instr) { in VisitNEONScalarCopy() argument
4500 NEONFormatDecoder nfd(instr, NEONFormatDecoder::TriangularScalarFormatMap()); in VisitNEONScalarCopy()
4502 if (instr->Mask(NEONScalarCopyMask) == NEON_DUP_ELEMENT_scalar) { in VisitNEONScalarCopy()
4507 Format(instr, mnemonic, nfd.Substitute(form, nfd.kPlaceholder, nfd.kFormat)); in VisitNEONScalarCopy()
4511 void Disassembler::VisitNEONScalarPairwise(const Instruction *instr) { in VisitNEONScalarPairwise() argument
4515 NEONFormatDecoder nfd(instr, in VisitNEONScalarPairwise()
4519 switch (instr->Mask(NEONScalarPairwiseMask)) { in VisitNEONScalarPairwise()
4559 Format(instr, in VisitNEONScalarPairwise()
4567 void Disassembler::VisitNEONScalarShiftImmediate(const Instruction *instr) { in VisitNEONScalarShiftImmediate() argument
4591 NEONFormatDecoder nfd(instr, &map_shift); in VisitNEONScalarShiftImmediate()
4593 if (instr->GetImmNEONImmh()) { // immh has to be non-zero. in VisitNEONScalarShiftImmediate()
4594 switch (instr->Mask(NEONScalarShiftImmediateMask)) { in VisitNEONScalarShiftImmediate()
4684 Format(instr, mnemonic, nfd.SubstitutePlaceholders(form)); in VisitNEONScalarShiftImmediate()
4688 void Disassembler::VisitNEONShiftImmediate(const Instruction *instr) { in VisitNEONShiftImmediate() argument
4709 NEONFormatDecoder nfd(instr, &map_shift_tb); in VisitNEONShiftImmediate()
4711 if (instr->GetImmNEONImmh()) { // immh has to be non-zero. in VisitNEONShiftImmediate()
4712 switch (instr->Mask(NEONShiftImmediateMask)) { in VisitNEONShiftImmediate()
4773 mnemonic = instr->Mask(NEON_Q) ? "shrn2" : "shrn"; in VisitNEONShiftImmediate()
4777 mnemonic = instr->Mask(NEON_Q) ? "rshrn2" : "rshrn"; in VisitNEONShiftImmediate()
4781 mnemonic = instr->Mask(NEON_Q) ? "uqshrn2" : "uqshrn"; in VisitNEONShiftImmediate()
4785 mnemonic = instr->Mask(NEON_Q) ? "uqrshrn2" : "uqrshrn"; in VisitNEONShiftImmediate()
4789 mnemonic = instr->Mask(NEON_Q) ? "sqshrn2" : "sqshrn"; in VisitNEONShiftImmediate()
4793 mnemonic = instr->Mask(NEON_Q) ? "sqrshrn2" : "sqrshrn"; in VisitNEONShiftImmediate()
4797 mnemonic = instr->Mask(NEON_Q) ? "sqshrun2" : "sqshrun"; in VisitNEONShiftImmediate()
4801 mnemonic = instr->Mask(NEON_Q) ? "sqrshrun2" : "sqrshrun"; in VisitNEONShiftImmediate()
4806 if (instr->GetImmNEONImmb() == 0 && in VisitNEONShiftImmediate()
4807 CountSetBits(instr->GetImmNEONImmh(), 32) == 1) { // sxtl variant. in VisitNEONShiftImmediate()
4809 mnemonic = instr->Mask(NEON_Q) ? "sxtl2" : "sxtl"; in VisitNEONShiftImmediate()
4812 mnemonic = instr->Mask(NEON_Q) ? "sshll2" : "sshll"; in VisitNEONShiftImmediate()
4817 if (instr->GetImmNEONImmb() == 0 && in VisitNEONShiftImmediate()
4818 CountSetBits(instr->GetImmNEONImmh(), 32) == 1) { // uxtl variant. in VisitNEONShiftImmediate()
4820 mnemonic = instr->Mask(NEON_Q) ? "uxtl2" : "uxtl"; in VisitNEONShiftImmediate()
4823 mnemonic = instr->Mask(NEON_Q) ? "ushll2" : "ushll"; in VisitNEONShiftImmediate()
4832 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONShiftImmediate()
4836 void Disassembler::VisitNEONTable(const Instruction *instr) { in VisitNEONTable() argument
4845 NEONFormatDecoder nfd(instr, &map_b); in VisitNEONTable()
4847 switch (instr->Mask(NEONTableMask)) { in VisitNEONTable()
4885 int reg_num = instr->GetRn(); in VisitNEONTable()
4893 Format(instr, mnemonic, nfd.Substitute(re_form)); in VisitNEONTable()
4897 void Disassembler::VisitNEONPerm(const Instruction *instr) { in VisitNEONPerm() argument
4900 NEONFormatDecoder nfd(instr); in VisitNEONPerm()
4902 switch (instr->Mask(NEONPermMask)) { in VisitNEONPerm()
4924 Format(instr, mnemonic, nfd.Substitute(form)); in VisitNEONPerm()
4929 const Instruction *instr) { in VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets() argument
4933 switch (instr->Mask( in VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets()
4951 Format(instr, mnemonic, form); in VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets()
4955 const Instruction *instr) { in VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets() argument
4960 instr->Mask(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask)) { in VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets()
4971 Format(instr, mnemonic, form); in VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets()
4975 const Instruction *instr) { in VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets() argument
4979 switch (instr->Mask(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask)) { in VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets()
5014 Format(instr, mnemonic, form); in VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets()
5018 const Instruction *instr) { in VisitSVE32BitGatherLoad_VectorPlusImm() argument
5026 switch (instr->Mask(SVE32BitGatherLoad_VectorPlusImmMask)) { in VisitSVE32BitGatherLoad_VectorPlusImm()
5072 if (instr->ExtractBits(20, 16) != 0) form = form_imm; in VisitSVE32BitGatherLoad_VectorPlusImm()
5074 Format(instr, mnemonic, form); in VisitSVE32BitGatherLoad_VectorPlusImm()
5078 const Instruction *instr) { in VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets() argument
5084 instr->Mask(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask)) { in VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets()
5105 Format(instr, mnemonic, form, suffix); in VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets()
5109 const Instruction *instr) { in VisitSVE32BitGatherPrefetch_VectorPlusImm() argument
5111 const char *form = (instr->ExtractBits(20, 16) != 0) in VisitSVE32BitGatherPrefetch_VectorPlusImm()
5115 switch (instr->Mask(SVE32BitGatherPrefetch_VectorPlusImmMask)) { in VisitSVE32BitGatherPrefetch_VectorPlusImm()
5131 Format(instr, mnemonic, form); in VisitSVE32BitGatherPrefetch_VectorPlusImm()
5135 const Instruction *instr) { in VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets() argument
5139 switch (instr->Mask(SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask)) { in VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets()
5150 Format(instr, mnemonic, form); in VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets()
5154 const Instruction *instr) { in VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets() argument
5159 instr->Mask(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask)) { in VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets()
5173 Format(instr, mnemonic, form); in VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets()
5177 const Instruction *instr) { in VisitSVE32BitScatterStore_VectorPlusImm() argument
5182 bool is_zero = instr->ExtractBits(20, 16) == 0; in VisitSVE32BitScatterStore_VectorPlusImm()
5184 switch (instr->Mask(SVE32BitScatterStore_VectorPlusImmMask)) { in VisitSVE32BitScatterStore_VectorPlusImm()
5201 Format(instr, mnemonic, form, suffix); in VisitSVE32BitScatterStore_VectorPlusImm()
5205 const Instruction *instr) { in VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets() argument
5209 switch (instr->Mask( in VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets()
5245 Format(instr, mnemonic, form); in VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets()
5249 const Instruction *instr) { in VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets() argument
5253 switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)) { in VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets()
5288 Format(instr, mnemonic, form); in VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets()
5292 const Instruction *instr) { in VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets() argument
5296 switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask)) { in VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets()
5342 Format(instr, mnemonic, form); in VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets()
5347 const Instruction *instr) { in VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets() argument
5351 switch (instr->Mask( in VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets()
5399 Format(instr, mnemonic, form); in VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets()
5403 const Instruction *instr) { in VisitSVE64BitGatherLoad_VectorPlusImm() argument
5410 if (instr->ExtractBits(20, 16) != 0) { in VisitSVE64BitGatherLoad_VectorPlusImm()
5411 unsigned msz = instr->ExtractBits(24, 23); in VisitSVE64BitGatherLoad_VectorPlusImm()
5412 bool sign_extend = instr->ExtractBit(14) == 0; in VisitSVE64BitGatherLoad_VectorPlusImm()
5422 switch (instr->Mask(SVE64BitGatherLoad_VectorPlusImmMask)) { in VisitSVE64BitGatherLoad_VectorPlusImm()
5468 Format(instr, mnemonic, form); in VisitSVE64BitGatherLoad_VectorPlusImm()
5472 const Instruction *instr) { in VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets() argument
5477 instr->Mask(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask)) { in VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets()
5497 Format(instr, mnemonic, form); in VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets()
5502 const Instruction *instr) { in VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets() argument
5507 switch (instr->Mask( in VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets()
5529 Format(instr, mnemonic, form, suffix); in VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets()
5533 const Instruction *instr) { in VisitSVE64BitGatherPrefetch_VectorPlusImm() argument
5535 const char *form = (instr->ExtractBits(20, 16) != 0) in VisitSVE64BitGatherPrefetch_VectorPlusImm()
5539 switch (instr->Mask(SVE64BitGatherPrefetch_VectorPlusImmMask)) { in VisitSVE64BitGatherPrefetch_VectorPlusImm()
5555 Format(instr, mnemonic, form); in VisitSVE64BitGatherPrefetch_VectorPlusImm()
5559 const Instruction *instr) { in VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets() argument
5563 switch (instr->Mask(SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask)) { in VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets()
5577 Format(instr, mnemonic, form); in VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets()
5581 const Instruction *instr) { in VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets() argument
5586 instr->Mask(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask)) { in VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets()
5603 Format(instr, mnemonic, form); in VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets()
5608 const Instruction *instr) { in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets() argument
5612 switch (instr->Mask( in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets()
5627 Format(instr, mnemonic, form); in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets()
5632 const Instruction *instr) { in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets() argument
5636 switch (instr->Mask( in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets()
5654 Format(instr, mnemonic, form); in VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets()
5658 const Instruction *instr) { in VisitSVE64BitScatterStore_VectorPlusImm() argument
5663 bool is_zero = instr->ExtractBits(20, 16) == 0; in VisitSVE64BitScatterStore_VectorPlusImm()
5665 switch (instr->Mask(SVE64BitScatterStore_VectorPlusImmMask)) { in VisitSVE64BitScatterStore_VectorPlusImm()
5686 Format(instr, mnemonic, form, suffix); in VisitSVE64BitScatterStore_VectorPlusImm()
5690 const Instruction *instr) { in VisitSVEBitwiseLogicalWithImm_Unpredicated() argument
5694 if (instr->GetSVEImmLogical() == 0) { in VisitSVEBitwiseLogicalWithImm_Unpredicated()
5696 Format(instr, "unallocated", "(SVEBitwiseImm)"); in VisitSVEBitwiseLogicalWithImm_Unpredicated()
5700 switch (instr->Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask)) { in VisitSVEBitwiseLogicalWithImm_Unpredicated()
5713 Format(instr, mnemonic, form); in VisitSVEBitwiseLogicalWithImm_Unpredicated()
5716 void Disassembler::VisitSVEBitwiseLogical_Predicated(const Instruction *instr) { in VisitSVEBitwiseLogical_Predicated() argument
5720 switch (instr->Mask(SVEBitwiseLogical_PredicatedMask)) { in VisitSVEBitwiseLogical_Predicated()
5736 Format(instr, mnemonic, form); in VisitSVEBitwiseLogical_Predicated()
5740 const Instruction *instr) { in VisitSVEBitwiseShiftByImm_Predicated() argument
5743 unsigned tsize = (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(9, 8); in VisitSVEBitwiseShiftByImm_Predicated()
5748 switch (instr->Mask(SVEBitwiseShiftByImm_PredicatedMask)) { in VisitSVEBitwiseShiftByImm_Predicated()
5766 Format(instr, mnemonic, form); in VisitSVEBitwiseShiftByImm_Predicated()
5770 const Instruction *instr) { in VisitSVEBitwiseShiftByVector_Predicated() argument
5774 switch (instr->Mask(SVEBitwiseShiftByVector_PredicatedMask)) { in VisitSVEBitwiseShiftByVector_Predicated()
5797 Format(instr, mnemonic, form); in VisitSVEBitwiseShiftByVector_Predicated()
5801 const Instruction *instr) { in VisitSVEBitwiseShiftByWideElements_Predicated() argument
5805 if (instr->GetSVESize() == kDRegSizeInBytesLog2) { in VisitSVEBitwiseShiftByWideElements_Predicated()
5808 switch (instr->Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) { in VisitSVEBitwiseShiftByWideElements_Predicated()
5823 Format(instr, mnemonic, form); in VisitSVEBitwiseShiftByWideElements_Predicated()
5907 void Disassembler::VisitSVEBroadcastBitmaskImm(const Instruction *instr) { in VisitSVEBroadcastBitmaskImm() argument
5911 switch (instr->Mask(SVEBroadcastBitmaskImmMask)) { in VisitSVEBroadcastBitmaskImm()
5913 uint64_t imm = instr->GetSVEImmLogical(); in VisitSVEBroadcastBitmaskImm()
5915 int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2(); in VisitSVEBroadcastBitmaskImm()
5924 Format(instr, mnemonic, form); in VisitSVEBroadcastBitmaskImm()
5928 const Instruction *instr) { in VisitSVEBroadcastFPImm_Unpredicated() argument
5932 switch (instr->Mask(SVEBroadcastFPImm_UnpredicatedMask)) { in VisitSVEBroadcastFPImm_Unpredicated()
5941 Format(instr, mnemonic, form); in VisitSVEBroadcastFPImm_Unpredicated()
5944 void Disassembler::VisitSVEBroadcastGeneralRegister(const Instruction *instr) { in VisitSVEBroadcastGeneralRegister() argument
5948 switch (instr->Mask(SVEBroadcastGeneralRegisterMask)) { in VisitSVEBroadcastGeneralRegister()
5952 if (instr->GetSVESize() == kDRegSizeInBytesLog2) { in VisitSVEBroadcastGeneralRegister()
5961 Format(instr, mnemonic, form); in VisitSVEBroadcastGeneralRegister()
5964 void Disassembler::VisitSVEBroadcastIndexElement(const Instruction *instr) { in VisitSVEBroadcastIndexElement() argument
5968 switch (instr->Mask(SVEBroadcastIndexElementMask)) { in VisitSVEBroadcastIndexElement()
5971 int tsz = instr->ExtractBits(20, 16); in VisitSVEBroadcastIndexElement()
5975 int imm2 = instr->ExtractBits(23, 22); in VisitSVEBroadcastIndexElement()
5989 Format(instr, mnemonic, form); in VisitSVEBroadcastIndexElement()
5993 const Instruction *instr) { in VisitSVEBroadcastIntImm_Unpredicated() argument
5997 switch (instr->Mask(SVEBroadcastIntImm_UnpredicatedMask)) { in VisitSVEBroadcastIntImm_Unpredicated()
6000 if ((instr->GetSVEVectorFormat() == kFormatVnB) && in VisitSVEBroadcastIntImm_Unpredicated()
6001 (instr->ExtractBit(13) == 1)) in VisitSVEBroadcastIntImm_Unpredicated()
6006 form = (instr->ExtractBit(13) == 0) ? "'Zd.'t, #'s1205" in VisitSVEBroadcastIntImm_Unpredicated()
6012 Format(instr, mnemonic, form); in VisitSVEBroadcastIntImm_Unpredicated()
6015 void Disassembler::VisitSVECompressActiveElements(const Instruction *instr) { in VisitSVECompressActiveElements() argument
6019 switch (instr->Mask(SVECompressActiveElementsMask)) { in VisitSVECompressActiveElements()
6023 VIXL_ASSERT(instr->ExtractBit(23) == 1); in VisitSVECompressActiveElements()
6030 Format(instr, mnemonic, form); in VisitSVECompressActiveElements()
6034 const Instruction *instr) { in VisitSVEConditionallyBroadcastElementToVector() argument
6038 switch (instr->Mask(SVEConditionallyBroadcastElementToVectorMask)) { in VisitSVEConditionallyBroadcastElementToVector()
6048 Format(instr, mnemonic, form); in VisitSVEConditionallyBroadcastElementToVector()
6052 const Instruction *instr) { in VisitSVEConditionallyExtractElementToGeneralRegister() argument
6056 if (instr->GetSVESize() == kDRegSizeInBytesLog2) { in VisitSVEConditionallyExtractElementToGeneralRegister()
6060 switch (instr->Mask(SVEConditionallyExtractElementToGeneralRegisterMask)) { in VisitSVEConditionallyExtractElementToGeneralRegister()
6070 Format(instr, mnemonic, form); in VisitSVEConditionallyExtractElementToGeneralRegister()
6074 const Instruction *instr) { in VisitSVEConditionallyExtractElementToSIMDFPScalar() argument
6078 switch (instr->Mask(SVEConditionallyExtractElementToSIMDFPScalarMask)) { in VisitSVEConditionallyExtractElementToSIMDFPScalar()
6088 Format(instr, mnemonic, form); in VisitSVEConditionallyExtractElementToSIMDFPScalar()
6092 const Instruction *instr) { in VisitSVEConditionallyTerminateScalars() argument
6094 const char *form = (instr->ExtractBit(22) == 0) ? "'Wn, 'Wm" : "'Xn, 'Xm"; in VisitSVEConditionallyTerminateScalars()
6096 switch (instr->Mask(SVEConditionallyTerminateScalarsMask)) { in VisitSVEConditionallyTerminateScalars()
6106 Format(instr, mnemonic, form); in VisitSVEConditionallyTerminateScalars()
6110 const Instruction *instr) { in VisitSVEConstructivePrefix_Unpredicated() argument
6114 switch (instr->Mask(SVEConstructivePrefix_UnpredicatedMask)) { in VisitSVEConstructivePrefix_Unpredicated()
6122 Format(instr, mnemonic, form); in VisitSVEConstructivePrefix_Unpredicated()
6126 const Instruction *instr) { in VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar() argument
6129 bool rm_is_zr = instr->GetRm() == kZeroRegCode; in VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar()
6134 switch (instr->Mask(SVEContiguousFirstFaultLoad_ScalarPlusScalarMask)) { in VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar()
6177 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar()
6181 const Instruction *instr) { in VisitSVEContiguousNonFaultLoad_ScalarPlusImm() argument
6185 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]"; in VisitSVEContiguousNonFaultLoad_ScalarPlusImm()
6187 switch (instr->Mask(SVEContiguousNonFaultLoad_ScalarPlusImmMask)) { in VisitSVEContiguousNonFaultLoad_ScalarPlusImm()
6223 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousNonFaultLoad_ScalarPlusImm()
6227 const Instruction *instr) { in VisitSVEContiguousNonTemporalLoad_ScalarPlusImm() argument
6232 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]"; in VisitSVEContiguousNonTemporalLoad_ScalarPlusImm()
6233 switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusImmMask)) { in VisitSVEContiguousNonTemporalLoad_ScalarPlusImm()
6254 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousNonTemporalLoad_ScalarPlusImm()
6258 const Instruction *instr) { in VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar() argument
6262 switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusScalarMask)) { in VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar()
6282 Format(instr, mnemonic, form); in VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar()
6286 const Instruction *instr) { in VisitSVEContiguousNonTemporalStore_ScalarPlusImm() argument
6291 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]"; in VisitSVEContiguousNonTemporalStore_ScalarPlusImm()
6292 switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusImmMask)) { in VisitSVEContiguousNonTemporalStore_ScalarPlusImm()
6313 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousNonTemporalStore_ScalarPlusImm()
6317 const Instruction *instr) { in VisitSVEContiguousNonTemporalStore_ScalarPlusScalar() argument
6321 switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusScalarMask)) { in VisitSVEContiguousNonTemporalStore_ScalarPlusScalar()
6341 Format(instr, mnemonic, form); in VisitSVEContiguousNonTemporalStore_ScalarPlusScalar()
6345 const Instruction *instr) { in VisitSVEContiguousPrefetch_ScalarPlusImm() argument
6347 const char *form = (instr->ExtractBits(21, 16) != 0) in VisitSVEContiguousPrefetch_ScalarPlusImm()
6351 switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusImmMask)) { in VisitSVEContiguousPrefetch_ScalarPlusImm()
6367 Format(instr, mnemonic, form); in VisitSVEContiguousPrefetch_ScalarPlusImm()
6371 const Instruction *instr) { in VisitSVEContiguousPrefetch_ScalarPlusScalar() argument
6375 if (instr->GetRm() != kZeroRegCode) { in VisitSVEContiguousPrefetch_ScalarPlusScalar()
6376 switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) { in VisitSVEContiguousPrefetch_ScalarPlusScalar()
6397 Format(instr, mnemonic, form); in VisitSVEContiguousPrefetch_ScalarPlusScalar()
6401 const Instruction *instr) { in VisitSVEContiguousStore_ScalarPlusImm() argument
6406 if (instr->ExtractBits(19, 16) == 0) { in VisitSVEContiguousStore_ScalarPlusImm()
6410 switch (instr->Mask(SVEContiguousStore_ScalarPlusImmMask)) { in VisitSVEContiguousStore_ScalarPlusImm()
6426 Format(instr, mnemonic, form); in VisitSVEContiguousStore_ScalarPlusImm()
6430 const Instruction *instr) { in VisitSVEContiguousStore_ScalarPlusScalar() argument
6436 switch (instr->Mask(SVEContiguousStore_ScalarPlusScalarMask)) { in VisitSVEContiguousStore_ScalarPlusScalar()
6452 Format(instr, mnemonic, form); in VisitSVEContiguousStore_ScalarPlusScalar()
6455 void Disassembler::VisitSVECopyFPImm_Predicated(const Instruction *instr) { in VisitSVECopyFPImm_Predicated() argument
6459 switch (instr->Mask(SVECopyFPImm_PredicatedMask)) { in VisitSVECopyFPImm_Predicated()
6468 Format(instr, mnemonic, form); in VisitSVECopyFPImm_Predicated()
6472 const Instruction *instr) { in VisitSVECopyGeneralRegisterToVector_Predicated() argument
6476 switch (instr->Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) { in VisitSVECopyGeneralRegisterToVector_Predicated()
6481 if (instr->GetSVESize() == kXRegSizeInBytesLog2) { in VisitSVECopyGeneralRegisterToVector_Predicated()
6488 Format(instr, mnemonic, form); in VisitSVECopyGeneralRegisterToVector_Predicated()
6491 void Disassembler::VisitSVECopyIntImm_Predicated(const Instruction *instr) { in VisitSVECopyIntImm_Predicated() argument
6496 switch (instr->Mask(SVECopyIntImm_PredicatedMask)) { in VisitSVECopyIntImm_Predicated()
6501 if (instr->ExtractBit(13) != 0) suffix = ", lsl #8"; in VisitSVECopyIntImm_Predicated()
6507 Format(instr, mnemonic, form, suffix); in VisitSVECopyIntImm_Predicated()
6511 const Instruction *instr) { in VisitSVECopySIMDFPScalarRegisterToVector_Predicated() argument
6515 switch (instr->Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) { in VisitSVECopySIMDFPScalarRegisterToVector_Predicated()
6524 Format(instr, mnemonic, form); in VisitSVECopySIMDFPScalarRegisterToVector_Predicated()
6528 const Instruction *instr) { in VisitSVEExtractElementToGeneralRegister() argument
6532 if (instr->GetSVESize() == kDRegSizeInBytesLog2) { in VisitSVEExtractElementToGeneralRegister()
6536 switch (instr->Mask(SVEExtractElementToGeneralRegisterMask)) { in VisitSVEExtractElementToGeneralRegister()
6546 Format(instr, mnemonic, form); in VisitSVEExtractElementToGeneralRegister()
6550 const Instruction *instr) { in VisitSVEExtractElementToSIMDFPScalarRegister() argument
6554 switch (instr->Mask(SVEExtractElementToSIMDFPScalarRegisterMask)) { in VisitSVEExtractElementToSIMDFPScalarRegister()
6564 Format(instr, mnemonic, form); in VisitSVEExtractElementToSIMDFPScalarRegister()
6567 void Disassembler::VisitSVEFFRInitialise(const Instruction *instr) { in VisitSVEFFRInitialise() argument
6571 switch (instr->Mask(SVEFFRInitialiseMask)) { in VisitSVEFFRInitialise()
6579 Format(instr, mnemonic, form); in VisitSVEFFRInitialise()
6582 void Disassembler::VisitSVEFFRWriteFromPredicate(const Instruction *instr) { in VisitSVEFFRWriteFromPredicate() argument
6586 switch (instr->Mask(SVEFFRWriteFromPredicateMask)) { in VisitSVEFFRWriteFromPredicate()
6594 Format(instr, mnemonic, form); in VisitSVEFFRWriteFromPredicate()
6598 const Instruction *instr) { in VisitSVEFPArithmeticWithImm_Predicated() argument
6604 int i1 = instr->ExtractBit(5); in VisitSVEFPArithmeticWithImm_Predicated()
6607 switch (instr->Mask(SVEFPArithmeticWithImm_PredicatedMask)) { in VisitSVEFPArithmeticWithImm_Predicated()
6640 Format(instr, mnemonic, form); in VisitSVEFPArithmeticWithImm_Predicated()
6643 void Disassembler::VisitSVEFPArithmetic_Predicated(const Instruction *instr) { in VisitSVEFPArithmetic_Predicated() argument
6647 switch (instr->Mask(SVEFPArithmetic_PredicatedMask)) { in VisitSVEFPArithmetic_Predicated()
6690 Format(instr, mnemonic, form); in VisitSVEFPArithmetic_Predicated()
6693 void Disassembler::VisitSVEFPConvertPrecision(const Instruction *instr) { in VisitSVEFPConvertPrecision() argument
6697 switch (instr->Mask(SVEFPConvertPrecisionMask)) { in VisitSVEFPConvertPrecision()
6725 Format(instr, mnemonic, form); in VisitSVEFPConvertPrecision()
6728 void Disassembler::VisitSVEFPConvertToInt(const Instruction *instr) { in VisitSVEFPConvertToInt() argument
6732 switch (instr->Mask(SVEFPConvertToIntMask)) { in VisitSVEFPConvertToInt()
6792 Format(instr, mnemonic, form); in VisitSVEFPConvertToInt()
6795 void Disassembler::VisitSVEFPExponentialAccelerator(const Instruction *instr) { in VisitSVEFPExponentialAccelerator() argument
6799 unsigned size = instr->GetSVESize(); in VisitSVEFPExponentialAccelerator()
6800 switch (instr->Mask(SVEFPExponentialAcceleratorMask)) { in VisitSVEFPExponentialAccelerator()
6811 Format(instr, mnemonic, form); in VisitSVEFPExponentialAccelerator()
6814 void Disassembler::VisitSVEFPRoundToIntegralValue(const Instruction *instr) { in VisitSVEFPRoundToIntegralValue() argument
6818 switch (instr->Mask(SVEFPRoundToIntegralValueMask)) { in VisitSVEFPRoundToIntegralValue()
6843 Format(instr, mnemonic, form); in VisitSVEFPRoundToIntegralValue()
6846 void Disassembler::VisitSVEFPTrigMulAddCoefficient(const Instruction *instr) { in VisitSVEFPTrigMulAddCoefficient() argument
6850 unsigned size = instr->GetSVESize(); in VisitSVEFPTrigMulAddCoefficient()
6851 switch (instr->Mask(SVEFPTrigMulAddCoefficientMask)) { in VisitSVEFPTrigMulAddCoefficient()
6862 Format(instr, mnemonic, form); in VisitSVEFPTrigMulAddCoefficient()
6865 void Disassembler::VisitSVEFPTrigSelectCoefficient(const Instruction *instr) { in VisitSVEFPTrigSelectCoefficient() argument
6869 unsigned size = instr->GetSVESize(); in VisitSVEFPTrigSelectCoefficient()
6870 switch (instr->Mask(SVEFPTrigSelectCoefficientMask)) { in VisitSVEFPTrigSelectCoefficient()
6881 Format(instr, mnemonic, form); in VisitSVEFPTrigSelectCoefficient()
6884 void Disassembler::VisitSVEFPUnaryOp(const Instruction *instr) { in VisitSVEFPUnaryOp() argument
6888 if (instr->GetSVESize() == kBRegSizeInBytesLog2) { in VisitSVEFPUnaryOp()
6891 switch (instr->Mask(SVEFPUnaryOpMask)) { in VisitSVEFPUnaryOp()
6903 Format(instr, mnemonic, form); in VisitSVEFPUnaryOp()
6906 static const char *IncDecFormHelper(const Instruction *instr, in IncDecFormHelper() argument
6910 if (instr->ExtractBits(19, 16) == 0) { in IncDecFormHelper()
6911 if (instr->ExtractBits(9, 5) == SVE_ALL) { in IncDecFormHelper()
6923 const Instruction *instr) { in VisitSVEIncDecRegisterByElementCount() argument
6926 IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd"); in VisitSVEIncDecRegisterByElementCount()
6928 switch (instr->Mask(SVEIncDecRegisterByElementCountMask)) { in VisitSVEIncDecRegisterByElementCount()
6957 Format(instr, mnemonic, form); in VisitSVEIncDecRegisterByElementCount()
6961 const Instruction *instr) { in VisitSVEIncDecVectorByElementCount() argument
6963 const char *form = IncDecFormHelper(instr, in VisitSVEIncDecVectorByElementCount()
6968 switch (instr->Mask(SVEIncDecVectorByElementCountMask)) { in VisitSVEIncDecVectorByElementCount()
6991 Format(instr, mnemonic, form); in VisitSVEIncDecVectorByElementCount()
6994 void Disassembler::VisitSVEInsertGeneralRegister(const Instruction *instr) { in VisitSVEInsertGeneralRegister() argument
6998 switch (instr->Mask(SVEInsertGeneralRegisterMask)) { in VisitSVEInsertGeneralRegister()
7001 if (instr->GetSVESize() == kDRegSizeInBytesLog2) { in VisitSVEInsertGeneralRegister()
7010 Format(instr, mnemonic, form); in VisitSVEInsertGeneralRegister()
7014 const Instruction *instr) { in VisitSVEInsertSIMDFPScalarRegister() argument
7018 switch (instr->Mask(SVEInsertSIMDFPScalarRegisterMask)) { in VisitSVEInsertSIMDFPScalarRegister()
7026 Format(instr, mnemonic, form); in VisitSVEInsertSIMDFPScalarRegister()
7030 const Instruction *instr) { in VisitSVEIntAddSubtractImm_Unpredicated() argument
7032 const char *form = (instr->ExtractBit(13) == 0) in VisitSVEIntAddSubtractImm_Unpredicated()
7036 switch (instr->Mask(SVEIntAddSubtractImm_UnpredicatedMask)) { in VisitSVEIntAddSubtractImm_Unpredicated()
7062 Format(instr, mnemonic, form); in VisitSVEIntAddSubtractImm_Unpredicated()
7066 const Instruction *instr) { in VisitSVEIntAddSubtractVectors_Predicated() argument
7070 switch (instr->Mask(SVEIntAddSubtractVectors_PredicatedMask)) { in VisitSVEIntAddSubtractVectors_Predicated()
7083 Format(instr, mnemonic, form); in VisitSVEIntAddSubtractVectors_Predicated()
7087 const Instruction *instr) { in VisitSVEIntCompareScalarCountAndLimit() argument
7090 (instr->ExtractBit(12) == 0) ? "'Pd.'t, 'Wn, 'Wm" : "'Pd.'t, 'Xn, 'Xm"; in VisitSVEIntCompareScalarCountAndLimit()
7092 switch (instr->Mask(SVEIntCompareScalarCountAndLimitMask)) { in VisitSVEIntCompareScalarCountAndLimit()
7108 Format(instr, mnemonic, form); in VisitSVEIntCompareScalarCountAndLimit()
7111 void Disassembler::VisitSVEIntConvertToFP(const Instruction *instr) { in VisitSVEIntConvertToFP() argument
7115 switch (instr->Mask(SVEIntConvertToFPMask)) { in VisitSVEIntConvertToFP()
7175 Format(instr, mnemonic, form); in VisitSVEIntConvertToFP()
7179 const Instruction *instr) { in VisitSVEIntDivideVectors_Predicated() argument
7183 switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) { in VisitSVEIntDivideVectors_Predicated()
7200 switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) { in VisitSVEIntDivideVectors_Predicated()
7205 switch (instr->GetSVESize()) { in VisitSVEIntDivideVectors_Predicated()
7222 Format(instr, mnemonic, form); in VisitSVEIntDivideVectors_Predicated()
7226 const Instruction *instr) { in VisitSVEIntMinMaxDifference_Predicated() argument
7230 switch (instr->Mask(SVEIntMinMaxDifference_PredicatedMask)) { in VisitSVEIntMinMaxDifference_Predicated()
7252 Format(instr, mnemonic, form); in VisitSVEIntMinMaxDifference_Predicated()
7255 void Disassembler::VisitSVEIntMinMaxImm_Unpredicated(const Instruction *instr) { in VisitSVEIntMinMaxImm_Unpredicated() argument
7259 switch (instr->Mask(SVEIntMinMaxImm_UnpredicatedMask)) { in VisitSVEIntMinMaxImm_Unpredicated()
7277 Format(instr, mnemonic, form); in VisitSVEIntMinMaxImm_Unpredicated()
7280 void Disassembler::VisitSVEIntMulImm_Unpredicated(const Instruction *instr) { in VisitSVEIntMulImm_Unpredicated() argument
7284 switch (instr->Mask(SVEIntMulImm_UnpredicatedMask)) { in VisitSVEIntMulImm_Unpredicated()
7292 Format(instr, mnemonic, form); in VisitSVEIntMulImm_Unpredicated()
7295 void Disassembler::VisitSVEIntMulVectors_Predicated(const Instruction *instr) { in VisitSVEIntMulVectors_Predicated() argument
7299 switch (instr->Mask(SVEIntMulVectors_PredicatedMask)) { in VisitSVEIntMulVectors_Predicated()
7312 Format(instr, mnemonic, form); in VisitSVEIntMulVectors_Predicated()
7315 void Disassembler::VisitSVELoadAndBroadcastElement(const Instruction *instr) { in VisitSVELoadAndBroadcastElement() argument
7324 switch (instr->Mask(SVELoadAndBroadcastElementMask)) { in VisitSVELoadAndBroadcastElement()
7410 if (instr->ExtractBits(21, 16) == 0) { in VisitSVELoadAndBroadcastElement()
7414 Format(instr, mnemonic, form, suffix); in VisitSVELoadAndBroadcastElement()
7418 const Instruction *instr) { in VisitSVELoadAndBroadcastQuadword_ScalarPlusImm() argument
7423 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916*16]"; in VisitSVELoadAndBroadcastQuadword_ScalarPlusImm()
7425 switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusImmMask)) { in VisitSVELoadAndBroadcastQuadword_ScalarPlusImm()
7446 Format(instr, mnemonic, form, suffix); in VisitSVELoadAndBroadcastQuadword_ScalarPlusImm()
7450 const Instruction *instr) { in VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar() argument
7454 switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusScalarMask)) { in VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar()
7474 Format(instr, mnemonic, form); in VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar()
7478 const Instruction *instr) { in VisitSVELoadMultipleStructures_ScalarPlusImm() argument
7489 switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusImmMask)) { in VisitSVELoadMultipleStructures_ScalarPlusImm()
7541 Format(instr, mnemonic, form); in VisitSVELoadMultipleStructures_ScalarPlusImm()
7545 const Instruction *instr) { in VisitSVELoadMultipleStructures_ScalarPlusScalar() argument
7556 switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusScalarMask)) { in VisitSVELoadMultipleStructures_ScalarPlusScalar()
7608 Format(instr, mnemonic, form); in VisitSVELoadMultipleStructures_ScalarPlusScalar()
7611 void Disassembler::VisitSVELoadPredicateRegister(const Instruction *instr) { in VisitSVELoadPredicateRegister() argument
7615 switch (instr->Mask(SVELoadPredicateRegisterMask)) { in VisitSVELoadPredicateRegister()
7618 if (instr->Mask(0x003f1c00) == 0) { in VisitSVELoadPredicateRegister()
7627 Format(instr, mnemonic, form); in VisitSVELoadPredicateRegister()
7630 void Disassembler::VisitSVELoadVectorRegister(const Instruction *instr) { in VisitSVELoadVectorRegister() argument
7634 switch (instr->Mask(SVELoadVectorRegisterMask)) { in VisitSVELoadVectorRegister()
7637 if (instr->Mask(0x003f1c00) == 0) { in VisitSVELoadVectorRegister()
7646 Format(instr, mnemonic, form); in VisitSVELoadVectorRegister()
7649 void Disassembler::VisitSVEPartitionBreakCondition(const Instruction *instr) { in VisitSVEPartitionBreakCondition() argument
7653 switch (instr->Mask(SVEPartitionBreakConditionMask)) { in VisitSVEPartitionBreakCondition()
7670 Format(instr, mnemonic, form); in VisitSVEPartitionBreakCondition()
7673 void Disassembler::VisitSVEPermutePredicateElements(const Instruction *instr) { in VisitSVEPermutePredicateElements() argument
7677 switch (instr->Mask(SVEPermutePredicateElementsMask)) { in VisitSVEPermutePredicateElements()
7699 Format(instr, mnemonic, form); in VisitSVEPermutePredicateElements()
7702 void Disassembler::VisitSVEPredicateFirstActive(const Instruction *instr) { in VisitSVEPredicateFirstActive() argument
7706 switch (instr->Mask(SVEPredicateFirstActiveMask)) { in VisitSVEPredicateFirstActive()
7714 Format(instr, mnemonic, form); in VisitSVEPredicateFirstActive()
7718 const Instruction *instr) { in VisitSVEPredicateReadFromFFR_Unpredicated() argument
7722 switch (instr->Mask(SVEPredicateReadFromFFR_UnpredicatedMask)) { in VisitSVEPredicateReadFromFFR_Unpredicated()
7730 Format(instr, mnemonic, form); in VisitSVEPredicateReadFromFFR_Unpredicated()
7733 void Disassembler::VisitSVEPredicateTest(const Instruction *instr) { in VisitSVEPredicateTest() argument
7737 switch (instr->Mask(SVEPredicateTestMask)) { in VisitSVEPredicateTest()
7745 Format(instr, mnemonic, form); in VisitSVEPredicateTest()
7748 void Disassembler::VisitSVEPredicateZero(const Instruction *instr) { in VisitSVEPredicateZero() argument
7752 switch (instr->Mask(SVEPredicateZeroMask)) { in VisitSVEPredicateZero()
7760 Format(instr, mnemonic, form); in VisitSVEPredicateZero()
7764 const Instruction *instr) { in VisitSVEPropagateBreakToNextPartition() argument
7768 switch (instr->Mask(SVEPropagateBreakToNextPartitionMask)) { in VisitSVEPropagateBreakToNextPartition()
7778 Format(instr, mnemonic, form); in VisitSVEPropagateBreakToNextPartition()
7781 void Disassembler::VisitSVEReversePredicateElements(const Instruction *instr) { in VisitSVEReversePredicateElements() argument
7785 switch (instr->Mask(SVEReversePredicateElementsMask)) { in VisitSVEReversePredicateElements()
7793 Format(instr, mnemonic, form); in VisitSVEReversePredicateElements()
7796 void Disassembler::VisitSVEReverseVectorElements(const Instruction *instr) { in VisitSVEReverseVectorElements() argument
7800 switch (instr->Mask(SVEReverseVectorElementsMask)) { in VisitSVEReverseVectorElements()
7808 Format(instr, mnemonic, form); in VisitSVEReverseVectorElements()
7811 void Disassembler::VisitSVEReverseWithinElements(const Instruction *instr) { in VisitSVEReverseWithinElements() argument
7815 unsigned size = instr->GetSVESize(); in VisitSVEReverseWithinElements()
7816 switch (instr->Mask(SVEReverseWithinElementsMask)) { in VisitSVEReverseWithinElements()
7845 Format(instr, mnemonic, form); in VisitSVEReverseWithinElements()
7849 const Instruction *instr) { in VisitSVESaturatingIncDecRegisterByElementCount() argument
7851 const char *form = IncDecFormHelper(instr, in VisitSVESaturatingIncDecRegisterByElementCount()
7855 const char *form_sx = IncDecFormHelper(instr, in VisitSVESaturatingIncDecRegisterByElementCount()
7860 switch (instr->Mask(SVESaturatingIncDecRegisterByElementCountMask)) { in VisitSVESaturatingIncDecRegisterByElementCount()
7952 Format(instr, mnemonic, form); in VisitSVESaturatingIncDecRegisterByElementCount()
7956 const Instruction *instr) { in VisitSVESaturatingIncDecVectorByElementCount() argument
7958 const char *form = IncDecFormHelper(instr, in VisitSVESaturatingIncDecVectorByElementCount()
7963 switch (instr->Mask(SVESaturatingIncDecVectorByElementCountMask)) { in VisitSVESaturatingIncDecVectorByElementCount()
8004 Format(instr, mnemonic, form); in VisitSVESaturatingIncDecVectorByElementCount()
8008 const Instruction *instr) { in VisitSVEStoreMultipleStructures_ScalarPlusImm() argument
8019 switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusImmMask)) { in VisitSVEStoreMultipleStructures_ScalarPlusImm()
8071 Format(instr, mnemonic, form); in VisitSVEStoreMultipleStructures_ScalarPlusImm()
8075 const Instruction *instr) { in VisitSVEStoreMultipleStructures_ScalarPlusScalar() argument
8086 switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusScalarMask)) { in VisitSVEStoreMultipleStructures_ScalarPlusScalar()
8138 Format(instr, mnemonic, form); in VisitSVEStoreMultipleStructures_ScalarPlusScalar()
8141 void Disassembler::VisitSVEStorePredicateRegister(const Instruction *instr) { in VisitSVEStorePredicateRegister() argument
8145 switch (instr->Mask(SVEStorePredicateRegisterMask)) { in VisitSVEStorePredicateRegister()
8148 if (instr->Mask(0x003f1c00) == 0) { in VisitSVEStorePredicateRegister()
8157 Format(instr, mnemonic, form); in VisitSVEStorePredicateRegister()
8160 void Disassembler::VisitSVEStoreVectorRegister(const Instruction *instr) { in VisitSVEStoreVectorRegister() argument
8164 switch (instr->Mask(SVEStoreVectorRegisterMask)) { in VisitSVEStoreVectorRegister()
8167 if (instr->Mask(0x003f1c00) == 0) { in VisitSVEStoreVectorRegister()
8176 Format(instr, mnemonic, form); in VisitSVEStoreVectorRegister()
8179 void Disassembler::VisitSVETableLookup(const Instruction *instr) { in VisitSVETableLookup() argument
8183 switch (instr->Mask(SVETableLookupMask)) { in VisitSVETableLookup()
8191 Format(instr, mnemonic, form); in VisitSVETableLookup()
8194 void Disassembler::VisitSVEUnpackPredicateElements(const Instruction *instr) { in VisitSVEUnpackPredicateElements() argument
8198 switch (instr->Mask(SVEUnpackPredicateElementsMask)) { in VisitSVEUnpackPredicateElements()
8208 Format(instr, mnemonic, form); in VisitSVEUnpackPredicateElements()
8211 void Disassembler::VisitSVEUnpackVectorElements(const Instruction *instr) { in VisitSVEUnpackVectorElements() argument
8215 if (instr->GetSVESize() == 0) { in VisitSVEUnpackVectorElements()
8217 Format(instr, "unallocated", "(SVEUnpackVectorElements)"); in VisitSVEUnpackVectorElements()
8221 switch (instr->Mask(SVEUnpackVectorElementsMask)) { in VisitSVEUnpackVectorElements()
8237 Format(instr, mnemonic, form); in VisitSVEUnpackVectorElements()
8240 void Disassembler::VisitSVEVectorSplice_Destructive(const Instruction *instr) { in VisitSVEVectorSplice_Destructive() argument
8244 switch (instr->Mask(SVEVectorSplice_DestructiveMask)) { in VisitSVEVectorSplice_Destructive()
8252 Format(instr, mnemonic, form); in VisitSVEVectorSplice_Destructive()
8255 void Disassembler::VisitSVEAddressGeneration(const Instruction *instr) { in VisitSVEAddressGeneration() argument
8260 bool msz_is_zero = (instr->ExtractBits(11, 10) == 0); in VisitSVEAddressGeneration()
8262 switch (instr->Mask(SVEAddressGenerationMask)) { in VisitSVEAddressGeneration()
8279 Format(instr, mnemonic, form, suffix); in VisitSVEAddressGeneration()
8283 const Instruction *instr) { in VisitSVEBitwiseLogicalUnpredicated() argument
8287 switch (instr->Mask(SVEBitwiseLogicalUnpredicatedMask)) { in VisitSVEBitwiseLogicalUnpredicated()
8299 if (instr->GetRn() == instr->GetRm()) { in VisitSVEBitwiseLogicalUnpredicated()
8307 Format(instr, mnemonic, form); in VisitSVEBitwiseLogicalUnpredicated()
8310 void Disassembler::VisitSVEBitwiseShiftUnpredicated(const Instruction *instr) { in VisitSVEBitwiseShiftUnpredicated() argument
8314 (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(20, 19); in VisitSVEBitwiseShiftUnpredicated()
8315 unsigned lane_size = instr->GetSVESize(); in VisitSVEBitwiseShiftUnpredicated()
8317 switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) { in VisitSVEBitwiseShiftUnpredicated()
8361 Format(instr, mnemonic, form); in VisitSVEBitwiseShiftUnpredicated()
8364 void Disassembler::VisitSVEElementCount(const Instruction *instr) { in VisitSVEElementCount() argument
8367 IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd"); in VisitSVEElementCount()
8369 switch (instr->Mask(SVEElementCountMask)) { in VisitSVEElementCount()
8385 Format(instr, mnemonic, form); in VisitSVEElementCount()
8388 void Disassembler::VisitSVEFPAccumulatingReduction(const Instruction *instr) { in VisitSVEFPAccumulatingReduction() argument
8392 switch (instr->Mask(SVEFPAccumulatingReductionMask)) { in VisitSVEFPAccumulatingReduction()
8400 Format(instr, mnemonic, form); in VisitSVEFPAccumulatingReduction()
8403 void Disassembler::VisitSVEFPArithmeticUnpredicated(const Instruction *instr) { in VisitSVEFPArithmeticUnpredicated() argument
8407 switch (instr->Mask(SVEFPArithmeticUnpredicatedMask)) { in VisitSVEFPArithmeticUnpredicated()
8429 Format(instr, mnemonic, form); in VisitSVEFPArithmeticUnpredicated()
8432 void Disassembler::VisitSVEFPCompareVectors(const Instruction *instr) { in VisitSVEFPCompareVectors() argument
8436 switch (instr->Mask(SVEFPCompareVectorsMask)) { in VisitSVEFPCompareVectors()
8461 Format(instr, mnemonic, form); in VisitSVEFPCompareVectors()
8464 void Disassembler::VisitSVEFPCompareWithZero(const Instruction *instr) { in VisitSVEFPCompareWithZero() argument
8468 switch (instr->Mask(SVEFPCompareWithZeroMask)) { in VisitSVEFPCompareWithZero()
8490 Format(instr, mnemonic, form); in VisitSVEFPCompareWithZero()
8493 void Disassembler::VisitSVEFPComplexAddition(const Instruction *instr) { in VisitSVEFPComplexAddition() argument
8497 switch (instr->Mask(SVEFPComplexAdditionMask)) { in VisitSVEFPComplexAddition()
8500 if (instr->ExtractBit(16) == 0) { in VisitSVEFPComplexAddition()
8509 Format(instr, mnemonic, form); in VisitSVEFPComplexAddition()
8512 void Disassembler::VisitSVEFPComplexMulAdd(const Instruction *instr) { in VisitSVEFPComplexMulAdd() argument
8519 switch (instr->Mask(SVEFPComplexMulAddMask)) { in VisitSVEFPComplexMulAdd()
8523 suffix = fcmla_constants[instr->ExtractBits(14, 13)]; in VisitSVEFPComplexMulAdd()
8528 Format(instr, mnemonic, form, suffix); in VisitSVEFPComplexMulAdd()
8531 void Disassembler::VisitSVEFPComplexMulAddIndex(const Instruction *instr) { in VisitSVEFPComplexMulAddIndex() argument
8536 const char *suffix = fcmla_constants[instr->ExtractBits(11, 10)]; in VisitSVEFPComplexMulAddIndex()
8538 switch (instr->Mask(SVEFPComplexMulAddIndexMask)) { in VisitSVEFPComplexMulAddIndex()
8551 Format(instr, mnemonic, form, suffix); in VisitSVEFPComplexMulAddIndex()
8554 void Disassembler::VisitSVEFPFastReduction(const Instruction *instr) { in VisitSVEFPFastReduction() argument
8558 switch (instr->Mask(SVEFPFastReductionMask)) { in VisitSVEFPFastReduction()
8577 Format(instr, mnemonic, form); in VisitSVEFPFastReduction()
8580 void Disassembler::VisitSVEFPMulIndex(const Instruction *instr) { in VisitSVEFPMulIndex() argument
8584 switch (instr->Mask(SVEFPMulIndexMask)) { in VisitSVEFPMulIndex()
8601 Format(instr, mnemonic, form); in VisitSVEFPMulIndex()
8604 void Disassembler::VisitSVEFPMulAdd(const Instruction *instr) { in VisitSVEFPMulAdd() argument
8608 switch (instr->Mask(SVEFPMulAddMask)) { in VisitSVEFPMulAdd()
8636 Format(instr, mnemonic, form); in VisitSVEFPMulAdd()
8639 void Disassembler::VisitSVEFPMulAddIndex(const Instruction *instr) { in VisitSVEFPMulAddIndex() argument
8643 switch (instr->Mask(SVEFPMulAddIndexMask)) { in VisitSVEFPMulAddIndex()
8674 Format(instr, mnemonic, form); in VisitSVEFPMulAddIndex()
8677 void Disassembler::VisitSVEFPUnaryOpUnpredicated(const Instruction *instr) { in VisitSVEFPUnaryOpUnpredicated() argument
8681 switch (instr->Mask(SVEFPUnaryOpUnpredicatedMask)) { in VisitSVEFPUnaryOpUnpredicated()
8691 Format(instr, mnemonic, form); in VisitSVEFPUnaryOpUnpredicated()
8694 void Disassembler::VisitSVEIncDecByPredicateCount(const Instruction *instr) { in VisitSVEIncDecByPredicateCount() argument
8698 switch (instr->Mask(SVEIncDecByPredicateCountMask)) { in VisitSVEIncDecByPredicateCount()
8731 switch (instr->Mask(SVEIncDecByPredicateCountMask)) { in VisitSVEIncDecByPredicateCount()
8766 Format(instr, mnemonic, form); in VisitSVEIncDecByPredicateCount()
8769 void Disassembler::VisitSVEIndexGeneration(const Instruction *instr) { in VisitSVEIndexGeneration() argument
8774 static_cast<unsigned>(instr->GetSVESize()) <= kWRegSizeInBytesLog2; in VisitSVEIndexGeneration()
8776 switch (instr->Mask(SVEIndexGenerationMask)) { in VisitSVEIndexGeneration()
8796 Format(instr, mnemonic, form); in VisitSVEIndexGeneration()
8799 void Disassembler::VisitSVEIntArithmeticUnpredicated(const Instruction *instr) { in VisitSVEIntArithmeticUnpredicated() argument
8803 switch (instr->Mask(SVEIntArithmeticUnpredicatedMask)) { in VisitSVEIntArithmeticUnpredicated()
8825 Format(instr, mnemonic, form); in VisitSVEIntArithmeticUnpredicated()
8828 void Disassembler::VisitSVEIntCompareSignedImm(const Instruction *instr) { in VisitSVEIntCompareSignedImm() argument
8832 switch (instr->Mask(SVEIntCompareSignedImmMask)) { in VisitSVEIntCompareSignedImm()
8854 Format(instr, mnemonic, form); in VisitSVEIntCompareSignedImm()
8857 void Disassembler::VisitSVEIntCompareUnsignedImm(const Instruction *instr) { in VisitSVEIntCompareUnsignedImm() argument
8861 switch (instr->Mask(SVEIntCompareUnsignedImmMask)) { in VisitSVEIntCompareUnsignedImm()
8877 Format(instr, mnemonic, form); in VisitSVEIntCompareUnsignedImm()
8880 void Disassembler::VisitSVEIntCompareVectors(const Instruction *instr) { in VisitSVEIntCompareVectors() argument
8884 switch (instr->Mask(SVEIntCompareVectorsMask)) { in VisitSVEIntCompareVectors()
8942 Format(instr, mnemonic, form); in VisitSVEIntCompareVectors()
8945 void Disassembler::VisitSVEIntMulAddPredicated(const Instruction *instr) { in VisitSVEIntMulAddPredicated() argument
8949 switch (instr->Mask(SVEIntMulAddPredicatedMask)) { in VisitSVEIntMulAddPredicated()
8969 Format(instr, mnemonic, form); in VisitSVEIntMulAddPredicated()
8972 void Disassembler::VisitSVEIntMulAddUnpredicated(const Instruction *instr) { in VisitSVEIntMulAddUnpredicated() argument
8976 if (static_cast<unsigned>(instr->GetSVESize()) >= kSRegSizeInBytesLog2) { in VisitSVEIntMulAddUnpredicated()
8978 switch (instr->Mask(SVEIntMulAddUnpredicatedMask)) { in VisitSVEIntMulAddUnpredicated()
8990 Format(instr, mnemonic, form); in VisitSVEIntMulAddUnpredicated()
8993 void Disassembler::VisitSVEMovprfx(const Instruction *instr) { in VisitSVEMovprfx() argument
8997 if (instr->Mask(SVEMovprfxMask) == MOVPRFX_z_p_z) { in VisitSVEMovprfx()
9002 Format(instr, mnemonic, form); in VisitSVEMovprfx()
9005 void Disassembler::VisitSVEIntReduction(const Instruction *instr) { in VisitSVEIntReduction() argument
9009 if (instr->Mask(SVEIntReductionLogicalFMask) == SVEIntReductionLogicalFixed) { in VisitSVEIntReduction()
9010 switch (instr->Mask(SVEIntReductionLogicalMask)) { in VisitSVEIntReduction()
9024 switch (instr->Mask(SVEIntReductionMask)) { in VisitSVEIntReduction()
9049 Format(instr, mnemonic, form); in VisitSVEIntReduction()
9053 const Instruction *instr) { in VisitSVEIntUnaryArithmeticPredicated() argument
9057 switch (instr->Mask(SVEIntUnaryArithmeticPredicatedMask)) { in VisitSVEIntUnaryArithmeticPredicated()
9106 Format(instr, mnemonic, form); in VisitSVEIntUnaryArithmeticPredicated()
9109 void Disassembler::VisitSVEMulIndex(const Instruction *instr) { in VisitSVEMulIndex() argument
9113 switch (instr->Mask(SVEMulIndexMask)) { in VisitSVEMulIndex()
9133 Format(instr, mnemonic, form); in VisitSVEMulIndex()
9136 void Disassembler::VisitSVEPermuteVectorExtract(const Instruction *instr) { in VisitSVEPermuteVectorExtract() argument
9140 switch (instr->Mask(SVEPermuteVectorExtractMask)) { in VisitSVEPermuteVectorExtract()
9148 Format(instr, mnemonic, form); in VisitSVEPermuteVectorExtract()
9151 void Disassembler::VisitSVEPermuteVectorInterleaving(const Instruction *instr) { in VisitSVEPermuteVectorInterleaving() argument
9155 switch (instr->Mask(SVEPermuteVectorInterleavingMask)) { in VisitSVEPermuteVectorInterleaving()
9177 Format(instr, mnemonic, form); in VisitSVEPermuteVectorInterleaving()
9180 void Disassembler::VisitSVEPredicateCount(const Instruction *instr) { in VisitSVEPredicateCount() argument
9184 switch (instr->Mask(SVEPredicateCountMask)) { in VisitSVEPredicateCount()
9192 Format(instr, mnemonic, form); in VisitSVEPredicateCount()
9195 void Disassembler::VisitSVEPredicateLogical(const Instruction *instr) { in VisitSVEPredicateLogical() argument
9199 int pd = instr->GetPd(); in VisitSVEPredicateLogical()
9200 int pn = instr->GetPn(); in VisitSVEPredicateLogical()
9201 int pm = instr->GetPm(); in VisitSVEPredicateLogical()
9202 int pg = instr->ExtractBits(13, 10); in VisitSVEPredicateLogical()
9204 switch (instr->Mask(SVEPredicateLogicalMask)) { in VisitSVEPredicateLogical()
9284 Format(instr, mnemonic, form); in VisitSVEPredicateLogical()
9287 void Disassembler::VisitSVEPredicateInitialize(const Instruction *instr) { in VisitSVEPredicateInitialize() argument
9292 VIXL_ASSERT((instr->Mask(SVEPredicateInitializeMask) == PTRUE_p_s) || in VisitSVEPredicateInitialize()
9293 (instr->Mask(SVEPredicateInitializeMask) == PTRUES_p_s)); in VisitSVEPredicateInitialize()
9295 const char *mnemonic = instr->ExtractBit(16) ? "ptrues" : "ptrue"; in VisitSVEPredicateInitialize()
9298 if (instr->ExtractBits(9, 5) == SVE_ALL) form = "'Pd.'t"; in VisitSVEPredicateInitialize()
9299 Format(instr, mnemonic, form); in VisitSVEPredicateInitialize()
9302 void Disassembler::VisitSVEPredicateNextActive(const Instruction *instr) { in VisitSVEPredicateNextActive() argument
9305 VIXL_ASSERT(instr->Mask(SVEPredicateNextActiveMask) == PNEXT_p_p_p); in VisitSVEPredicateNextActive()
9307 Format(instr, "pnext", "'Pd.'t, 'Pn, 'Pd.'t"); in VisitSVEPredicateNextActive()
9311 const Instruction *instr) { in VisitSVEPredicateReadFromFFR_Predicated() argument
9314 switch (instr->Mask(SVEPredicateReadFromFFR_PredicatedMask)) { in VisitSVEPredicateReadFromFFR_Predicated()
9317 mnemonic = instr->ExtractBit(22) ? "rdffrs" : "rdffr"; in VisitSVEPredicateReadFromFFR_Predicated()
9323 Format(instr, mnemonic, form); in VisitSVEPredicateReadFromFFR_Predicated()
9326 void Disassembler::VisitSVEPropagateBreak(const Instruction *instr) { in VisitSVEPropagateBreak() argument
9330 switch (instr->Mask(SVEPropagateBreakMask)) { in VisitSVEPropagateBreak()
9346 Format(instr, mnemonic, form); in VisitSVEPropagateBreak()
9349 void Disassembler::VisitSVEStackFrameAdjustment(const Instruction *instr) { in VisitSVEStackFrameAdjustment() argument
9353 switch (instr->Mask(SVEStackFrameAdjustmentMask)) { in VisitSVEStackFrameAdjustment()
9365 Format(instr, mnemonic, form); in VisitSVEStackFrameAdjustment()
9368 void Disassembler::VisitSVEStackFrameSize(const Instruction *instr) { in VisitSVEStackFrameSize() argument
9372 switch (instr->Mask(SVEStackFrameSizeMask)) { in VisitSVEStackFrameSize()
9381 Format(instr, mnemonic, form); in VisitSVEStackFrameSize()
9384 void Disassembler::VisitSVEVectorSelect(const Instruction *instr) { in VisitSVEVectorSelect() argument
9388 switch (instr->Mask(SVEVectorSelectMask)) { in VisitSVEVectorSelect()
9390 if (instr->GetRd() == instr->GetRm()) { in VisitSVEVectorSelect()
9401 Format(instr, mnemonic, form); in VisitSVEVectorSelect()
9405 const Instruction *instr) { in VisitSVEContiguousLoad_ScalarPlusImm() argument
9409 (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]"; in VisitSVEContiguousLoad_ScalarPlusImm()
9411 switch (instr->Mask(SVEContiguousLoad_ScalarPlusImmMask)) { in VisitSVEContiguousLoad_ScalarPlusImm()
9448 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousLoad_ScalarPlusImm()
9452 const Instruction *instr) { in VisitSVEContiguousLoad_ScalarPlusScalar() argument
9457 switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) { in VisitSVEContiguousLoad_ScalarPlusScalar()
9501 Format(instr, mnemonic, form, suffix); in VisitSVEContiguousLoad_ScalarPlusScalar()
9504 void Disassembler::VisitReserved(const Instruction *instr) { in VisitReserved() argument
9506 VIXL_ASSERT(instr->Mask(ReservedMask) == UDF); in VisitReserved()
9507 Format(instr, "udf", "'IUdf"); in VisitReserved()
9511 void Disassembler::VisitUnimplemented(const Instruction *instr) { in VisitUnimplemented() argument
9512 Format(instr, "unimplemented", "(Unimplemented)"); in VisitUnimplemented()
9516 void Disassembler::VisitUnallocated(const Instruction *instr) { in VisitUnallocated() argument
9517 Format(instr, "unallocated", "(Unallocated)"); in VisitUnallocated()
9526 void Disassembler::AppendRegisterNameToOutput(const Instruction *instr, in AppendRegisterNameToOutput() argument
9528 USE(instr); in AppendRegisterNameToOutput()
9568 void Disassembler::AppendPCRelativeOffsetToOutput(const Instruction *instr, in AppendPCRelativeOffsetToOutput() argument
9570 USE(instr); in AppendPCRelativeOffsetToOutput()
9581 void Disassembler::AppendAddressToOutput(const Instruction *instr, in AppendAddressToOutput() argument
9583 USE(instr); in AppendAddressToOutput()
9588 void Disassembler::AppendCodeAddressToOutput(const Instruction *instr, in AppendCodeAddressToOutput() argument
9590 AppendAddressToOutput(instr, addr); in AppendCodeAddressToOutput()
9594 void Disassembler::AppendDataAddressToOutput(const Instruction *instr, in AppendDataAddressToOutput() argument
9596 AppendAddressToOutput(instr, addr); in AppendDataAddressToOutput()
9600 void Disassembler::AppendCodeRelativeAddressToOutput(const Instruction *instr, in AppendCodeRelativeAddressToOutput() argument
9602 USE(instr); in AppendCodeRelativeAddressToOutput()
9613 const Instruction *instr, const void *addr) { in AppendCodeRelativeCodeAddressToOutput() argument
9614 AppendCodeRelativeAddressToOutput(instr, addr); in AppendCodeRelativeCodeAddressToOutput()
9619 const Instruction *instr, const void *addr) { in AppendCodeRelativeDataAddressToOutput() argument
9620 AppendCodeRelativeAddressToOutput(instr, addr); in AppendCodeRelativeDataAddressToOutput()
9634 void Disassembler::Format(const Instruction *instr, in Format() argument
9640 Substitute(instr, mnemonic); in Format()
9644 Substitute(instr, format0); in Format()
9646 Substitute(instr, format1); in Format()
9651 ProcessOutput(instr); in Format()
9655 void Disassembler::Substitute(const Instruction *instr, const char *string) { in Substitute() argument
9659 string += SubstituteField(instr, string); in Substitute()
9669 int Disassembler::SubstituteField(const Instruction *instr, in SubstituteField() argument
9684 return SubstituteRegisterField(instr, format); in SubstituteField()
9686 return SubstitutePredicateRegisterField(instr, format); in SubstituteField()
9688 return SubstituteImmediateField(instr, format); in SubstituteField()
9690 return SubstituteLiteralField(instr, format); in SubstituteField()
9692 return SubstituteShiftField(instr, format); in SubstituteField()
9694 return SubstituteConditionField(instr, format); in SubstituteField()
9696 return SubstituteExtendField(instr, format); in SubstituteField()
9698 return SubstitutePCRelAddressField(instr, format); in SubstituteField()
9700 return SubstituteBranchTargetField(instr, format); in SubstituteField()
9702 return SubstituteLSRegOffsetField(instr, format); in SubstituteField()
9704 return SubstituteBarrierField(instr, format); in SubstituteField()
9706 return SubstituteCrField(instr, format); in SubstituteField()
9708 return SubstituteSysOpField(instr, format); in SubstituteField()
9710 return SubstitutePrefetchField(instr, format); in SubstituteField()
9713 return SubstituteIntField(instr, format); in SubstituteField()
9715 return SubstituteSVESize(instr, format); in SubstituteField()
9717 return SubstituteTernary(instr, format); in SubstituteField()
9726 const Instruction *instr, char reg_prefix, const char *field) { in GetRegNumForField() argument
9732 reg_num = instr->GetRd(); in GetRegNumForField()
9735 reg_num = instr->GetRn(); in GetRegNumForField()
9738 reg_num = instr->GetRm(); in GetRegNumForField()
9743 reg_num = instr->GetRmLow16(); in GetRegNumForField()
9746 reg_num = instr->GetRa(); in GetRegNumForField()
9749 reg_num = instr->GetRs(); in GetRegNumForField()
9752 reg_num = instr->GetRt(); in GetRegNumForField()
9768 reg_num = instr->GetRt2(); in GetRegNumForField()
9789 int Disassembler::SubstituteRegisterField(const Instruction *instr, in SubstituteRegisterField() argument
9802 bool is_x = instr->GetSixtyFourBits(); in SubstituteRegisterField()
9809 is_x = (instr->ExtractBit(bitpos) == 1); in SubstituteRegisterField()
9817 GetRegNumForField(instr, reg_prefix, reg_field); in SubstituteRegisterField()
9837 imm *= (1 << instr->GetNEONLSSize()); in SubstituteRegisterField()
9840 imm *= (instr->GetNEONQ() == 0) ? kDRegSizeInBytes in SubstituteRegisterField()
9858 switch (instr->GetFPType()) { in SubstituteRegisterField()
9902 reg_size = 1 << (instr->GetSVESize() + 3); in SubstituteRegisterField()
9915 AppendRegisterNameToOutput(instr, CPURegister(reg_num, reg_size, reg_type)); in SubstituteRegisterField()
9920 int Disassembler::SubstitutePredicateRegisterField(const Instruction *instr, in SubstitutePredicateRegisterField() argument
9928 AppendToOutput("p%u", instr->GetPt()); in SubstitutePredicateRegisterField()
9931 AppendToOutput("p%u", instr->GetPn()); in SubstitutePredicateRegisterField()
9934 AppendToOutput("p%u", instr->GetPm()); in SubstitutePredicateRegisterField()
9938 AppendToOutput("p%u", instr->GetPgLow8()); in SubstitutePredicateRegisterField()
9946 int Disassembler::SubstituteImmediateField(const Instruction *instr, in SubstituteImmediateField() argument
9953 AppendToOutput("#0x%" PRIx32, instr->GetImmMoveWide()); in SubstituteImmediateField()
9954 if (instr->GetShiftMoveWide() > 0) { in SubstituteImmediateField()
9955 AppendToOutput(", lsl #%" PRId32, 16 * instr->GetShiftMoveWide()); in SubstituteImmediateField()
9959 uint64_t imm = static_cast<uint64_t>(instr->GetImmMoveWide()) in SubstituteImmediateField()
9960 << (16 * instr->GetShiftMoveWide()); in SubstituteImmediateField()
9962 if (!instr->GetSixtyFourBits()) imm &= UINT64_C(0xffffffff); in SubstituteImmediateField()
9971 instr->GetImmLLiteral() * in SubstituteImmediateField()
9979 if (is_index || (instr->GetImmLS() != 0)) { in SubstituteImmediateField()
9980 AppendToOutput(", #%" PRId32, instr->GetImmLS()); in SubstituteImmediateField()
9989 if (is_index || (instr->GetImmLSPair() != 0)) { in SubstituteImmediateField()
9992 AppendToOutput(", #%" PRId32, instr->GetImmLSPair() * scale); in SubstituteImmediateField()
9997 if (instr->GetImmLSUnsigned() != 0) { in SubstituteImmediateField()
9998 int shift = instr->GetSizeLS(); in SubstituteImmediateField()
9999 AppendToOutput(", #%" PRId32, instr->GetImmLSUnsigned() << shift); in SubstituteImmediateField()
10004 AppendToOutput("#%" PRId32, instr->GetImmRotFcmlaSca() * 90); in SubstituteImmediateField()
10008 if (instr->GetImmLSPAC() != 0) { in SubstituteImmediateField()
10009 AppendToOutput(", #%" PRId32, instr->GetImmLSPAC()); in SubstituteImmediateField()
10020 int64_t offset = instr->GetImmCondBranch() << 2; in SubstituteImmediateField()
10021 AppendPCRelativeOffsetToOutput(instr, offset); in SubstituteImmediateField()
10025 int64_t imm = instr->GetImmAddSub() << (12 * instr->GetImmAddSubShift()); in SubstituteImmediateField()
10035 AppendToOutput("#%" PRId32, 64 - instr->GetFPScale()); in SubstituteImmediateField()
10039 imm8 = instr->GetImmNEONabcdefgh(); in SubstituteImmediateField()
10044 imm8 = instr->ExtractBits(12, 5); in SubstituteImmediateField()
10049 imm8 = instr->GetImmFP(); in SubstituteImmediateField()
10058 AppendToOutput("#%" PRId32, instr->GetImmHint()); in SubstituteImmediateField()
10067 AppendToOutput("#0x%" PRIx64, instr->GetSVEImmLogical()); in SubstituteImmediateField()
10072 instr->GetSVEImmShiftAndLaneSizeLog2( in SubstituteImmediateField()
10081 instr->GetSVEImmShiftAndLaneSizeLog2( in SubstituteImmediateField()
10089 instr->GetSVEImmShiftAndLaneSizeLog2( in SubstituteImmediateField()
10098 instr->GetSVEImmShiftAndLaneSizeLog2( in SubstituteImmediateField()
10108 AppendToOutput("#0x%" PRIx64, instr->GetImmLogical()); in SubstituteImmediateField()
10113 int nzcv = (instr->GetNzcv() << Flags_offset); in SubstituteImmediateField()
10122 AppendToOutput("#%" PRId32, instr->GetImmCondCmp()); in SubstituteImmediateField()
10126 return SubstituteBitfieldImmediateField(instr, format); in SubstituteImmediateField()
10129 AppendToOutput("#%" PRId32, instr->GetImmS()); in SubstituteImmediateField()
10134 (instr->GetImmTestBranchBit5() << 5) | in SubstituteImmediateField()
10135 instr->GetImmTestBranchBit40()); in SubstituteImmediateField()
10140 int imm = instr->ExtractSignedBits(19, 16); in SubstituteImmediateField()
10142 int reg_count = instr->ExtractBits(22, 21) + 1; in SubstituteImmediateField()
10150 int shift = 16 << HighestSetBitPosition(instr->GetImmNEONImmh()); in SubstituteImmediateField()
10151 shift -= instr->GetImmNEONImmhImmb(); in SubstituteImmediateField()
10156 int shift = instr->GetImmNEONImmhImmb(); in SubstituteImmediateField()
10157 shift -= 8 << HighestSetBitPosition(instr->GetImmNEONImmh()); in SubstituteImmediateField()
10168 AppendToOutput("#0x%" PRIx32, instr->GetImmException()); in SubstituteImmediateField()
10172 AppendToOutput("#0x%" PRIx32, instr->GetImmUdf()); in SubstituteImmediateField()
10182 instr->GetImmRotFcadd() == 1 ? 270 : 90); in SubstituteImmediateField()
10185 AppendToOutput("#%" PRId32, instr->GetImmRotFcmlaVec() * 90); in SubstituteImmediateField()
10191 AppendToOutput("#%" PRId32, instr->GetImmNEONExt()); in SubstituteImmediateField()
10196 int vm_index = (instr->GetNEONH() << 1) | instr->GetNEONL(); in SubstituteImmediateField()
10202 if (instr->GetNEONSize() == 2) { in SubstituteImmediateField()
10203 vm_index = instr->GetNEONH(); in SubstituteImmediateField()
10206 } else if (is_fhm || (instr->GetNEONSize() == 0)) { in SubstituteImmediateField()
10209 vm_index = (instr->GetNEONH() << 2) | (instr->GetNEONL() << 1) | in SubstituteImmediateField()
10210 instr->GetNEONM(); in SubstituteImmediateField()
10212 } else if (instr->GetNEONSize() == 1) { in SubstituteImmediateField()
10213 vm_index = (vm_index << 1) | instr->GetNEONM(); in SubstituteImmediateField()
10221 unsigned imm5 = instr->GetImmNEON5(); in SubstituteImmediateField()
10222 unsigned imm4 = instr->GetImmNEON4(); in SubstituteImmediateField()
10242 instr->GetSVEPermuteIndexAndLaneSizeLog2(); in SubstituteImmediateField()
10249 AppendToOutput("%d", instr->GetNEONLSIndex(format[8] - '0')); in SubstituteImmediateField()
10254 uint64_t imm8 = instr->GetImmNEONabcdefgh(); in SubstituteImmediateField()
10258 uint64_t imm8 = instr->GetImmNEONabcdefgh(); in SubstituteImmediateField()
10270 int cmode = instr->GetNEONCmode(); in SubstituteImmediateField()
10277 int cmode = instr->GetNEONCmode(); in SubstituteImmediateField()
10293 AppendToOutput("#0x%" PRIx32, instr->GetCRm()); in SubstituteImmediateField()
10297 switch (instr->GetImmSystemRegister()) { in SubstituteImmediateField()
10312 instr->GetSysOp0(), in SubstituteImmediateField()
10313 instr->GetSysOp1(), in SubstituteImmediateField()
10314 instr->GetCRn(), in SubstituteImmediateField()
10315 instr->GetCRm(), in SubstituteImmediateField()
10316 instr->GetSysOp2()); in SubstituteImmediateField()
10324 AppendToOutput("#%d", instr->GetImmRMIFRotation()); in SubstituteImmediateField()
10335 unsigned pattern = instr->GetImmSVEPredicateConstraint(); in SubstituteImmediateField()
10383 int Disassembler::SubstituteBitfieldImmediateField(const Instruction *instr, in SubstituteBitfieldImmediateField() argument
10386 unsigned r = instr->GetImmR(); in SubstituteBitfieldImmediateField()
10387 unsigned s = instr->GetImmS(); in SubstituteBitfieldImmediateField()
10407 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; in SubstituteBitfieldImmediateField()
10419 int Disassembler::SubstituteLiteralField(const Instruction *instr, in SubstituteLiteralField() argument
10424 const void *address = instr->GetLiteralAddress<const void *>(); in SubstituteLiteralField()
10425 switch (instr->Mask(LoadLiteralMask)) { in SubstituteLiteralField()
10432 AppendCodeRelativeDataAddressToOutput(instr, address); in SubstituteLiteralField()
10436 switch (instr->GetPrefetchHint()) { in SubstituteLiteralField()
10439 AppendCodeRelativeDataAddressToOutput(instr, address); in SubstituteLiteralField()
10442 AppendCodeRelativeCodeAddressToOutput(instr, address); in SubstituteLiteralField()
10445 AppendCodeRelativeAddressToOutput(instr, address); in SubstituteLiteralField()
10458 int Disassembler::SubstituteShiftField(const Instruction *instr, in SubstituteShiftField() argument
10461 VIXL_ASSERT(instr->GetShiftDP() <= 0x3); in SubstituteShiftField()
10465 VIXL_ASSERT(instr->GetShiftDP() != ROR); in SubstituteShiftField()
10469 if (instr->GetImmDPShift() != 0) { in SubstituteShiftField()
10472 shift_type[instr->GetShiftDP()], in SubstituteShiftField()
10473 instr->GetImmDPShift()); in SubstituteShiftField()
10479 int msz = instr->ExtractBits(24, 23); in SubstituteShiftField()
10492 int Disassembler::SubstituteConditionField(const Instruction *instr, in SubstituteConditionField() argument
10514 cond = instr->GetConditionBranch(); in SubstituteConditionField()
10517 cond = InvertCondition(static_cast<Condition>(instr->GetCondition())); in SubstituteConditionField()
10521 cond = instr->GetCondition(); in SubstituteConditionField()
10528 int Disassembler::SubstitutePCRelAddressField(const Instruction *instr, in SubstitutePCRelAddressField() argument
10533 int64_t offset = instr->GetImmPCRel(); in SubstitutePCRelAddressField()
10537 const Instruction *base = instr + code_address_offset(); in SubstitutePCRelAddressField()
10547 AppendPCRelativeOffsetToOutput(instr, offset); in SubstitutePCRelAddressField()
10549 AppendCodeRelativeAddressToOutput(instr, target); in SubstitutePCRelAddressField()
10554 int Disassembler::SubstituteBranchTargetField(const Instruction *instr, in SubstituteBranchTargetField() argument
10562 offset = instr->GetImmUncondBranch(); in SubstituteBranchTargetField()
10566 offset = instr->GetImmCondBranch(); in SubstituteBranchTargetField()
10570 offset = instr->GetImmCmpBranch(); in SubstituteBranchTargetField()
10574 offset = instr->GetImmTestBranch(); in SubstituteBranchTargetField()
10580 const void *target_address = reinterpret_cast<const void *>(instr + offset); in SubstituteBranchTargetField()
10581 VIXL_STATIC_ASSERT(sizeof(*instr) == 1); in SubstituteBranchTargetField()
10583 AppendPCRelativeOffsetToOutput(instr, offset); in SubstituteBranchTargetField()
10585 AppendCodeRelativeCodeAddressToOutput(instr, target_address); in SubstituteBranchTargetField()
10591 int Disassembler::SubstituteExtendField(const Instruction *instr, in SubstituteExtendField() argument
10594 VIXL_ASSERT(instr->GetExtendMode() <= 7); in SubstituteExtendField()
10602 if (((instr->GetRd() == kZeroRegCode) || (instr->GetRn() == kZeroRegCode)) && in SubstituteExtendField()
10603 (((instr->GetExtendMode() == UXTW) && (instr->GetSixtyFourBits() == 0)) || in SubstituteExtendField()
10604 (instr->GetExtendMode() == UXTX))) { in SubstituteExtendField()
10605 if (instr->GetImmExtendShift() > 0) { in SubstituteExtendField()
10606 AppendToOutput(", lsl #%" PRId32, instr->GetImmExtendShift()); in SubstituteExtendField()
10609 AppendToOutput(", %s", extend_mode[instr->GetExtendMode()]); in SubstituteExtendField()
10610 if (instr->GetImmExtendShift() > 0) { in SubstituteExtendField()
10611 AppendToOutput(" #%" PRId32, instr->GetImmExtendShift()); in SubstituteExtendField()
10618 int Disassembler::SubstituteLSRegOffsetField(const Instruction *instr, in SubstituteLSRegOffsetField() argument
10631 unsigned shift = instr->GetImmShiftLS(); in SubstituteLSRegOffsetField()
10632 Extend ext = static_cast<Extend>(instr->GetExtendMode()); in SubstituteLSRegOffsetField()
10635 unsigned rm = instr->GetRm(); in SubstituteLSRegOffsetField()
10646 AppendToOutput(" #%d", instr->GetSizeLS()); in SubstituteLSRegOffsetField()
10653 int Disassembler::SubstitutePrefetchField(const Instruction *instr, in SubstitutePrefetchField() argument
10671 is_sve ? instr->GetSVEPrefetchHint() : instr->GetPrefetchHint(); in SubstitutePrefetchField()
10672 unsigned target = instr->GetPrefetchTarget() + 1; in SubstitutePrefetchField()
10673 unsigned stream = instr->GetPrefetchStream(); in SubstitutePrefetchField()
10678 std::bitset<4> prefetch_mode(instr->GetSVEImmPrefetchOperation()); in SubstitutePrefetchField()
10681 std::bitset<5> prefetch_mode(instr->GetImmPrefetchOperation()); in SubstitutePrefetchField()
10694 int Disassembler::SubstituteBarrierField(const Instruction *instr, in SubstituteBarrierField() argument
10703 int domain = instr->GetImmBarrierDomain(); in SubstituteBarrierField()
10704 int type = instr->GetImmBarrierType(); in SubstituteBarrierField()
10710 int Disassembler::SubstituteSysOpField(const Instruction *instr, in SubstituteSysOpField() argument
10716 op = instr->GetSysOp1(); in SubstituteSysOpField()
10719 op = instr->GetSysOp2(); in SubstituteSysOpField()
10728 int Disassembler::SubstituteCrField(const Instruction *instr, in SubstituteCrField() argument
10734 cr = instr->GetCRn(); in SubstituteCrField()
10737 cr = instr->GetCRm(); in SubstituteCrField()
10746 int Disassembler::SubstituteIntField(const Instruction *instr, in SubstituteIntField() argument
10770 bits = (bits << chunk_width) | (instr->ExtractBits(msb, lsb)); in SubstituteIntField()
10804 int Disassembler::SubstituteSVESize(const Instruction *instr, in SubstituteSVESize() argument
10813 unsigned size_in_bytes_log2 = instr->GetSVESize(); in SubstituteSVESize()
10820 size_in_bytes_log2 = instr->ExtractBits(22, 21); in SubstituteSVESize()
10824 unsigned msize = instr->ExtractBits(24, 23); in SubstituteSVESize()
10830 size_in_bytes_log2 = instr->GetSVEBitwiseImmLaneSizeInBytesLog2(); in SubstituteSVESize()
10836 size_in_bytes_log2 = instr->ExtractBits(24, 23); in SubstituteSVESize()
10845 instr->GetSVEPermuteIndexAndLaneSizeLog2(); in SubstituteSVESize()
10850 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ true); in SubstituteSVESize()
10855 instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false); in SubstituteSVESize()
10881 int Disassembler::SubstituteTernary(const Instruction *instr, in SubstituteTernary() argument
10895 AppendToOutput("%c", c[1 - instr->ExtractBit(static_cast<int>(value))]); in SubstituteTernary()
10916 void PrintDisassembler::Disassemble(const Instruction *instr) { in Disassemble() argument
10922 decoder.Decode(instr); in Disassemble()
10941 void PrintDisassembler::ProcessOutput(const Instruction *instr) { in ProcessOutput() argument
10942 int64_t address = CodeRelativeAddress(instr); in ProcessOutput()
10964 instr->GetInstructionBits(), in ProcessOutput()