# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            select_f32
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $s0, $s1, $w0

    ; CHECK-LABEL: name: select_f32
    ; CHECK: liveins: $s0, $s1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s32) = COPY $s0
    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s32) = COPY $s1
    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
    ; CHECK: $s0 = COPY [[SELECT]](s32)
    ; CHECK: RET_ReallyLR implicit $s0
    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s32) = COPY $s0
    %2:_(s32) = COPY $s1
    %4:_(s32) = G_SELECT %0(s1), %1, %2
    $s0 = COPY %4(s32)
    RET_ReallyLR implicit $s0

...
---
name:            select_f64
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $d1, $w0

    ; CHECK-LABEL: name: select_f64
    ; CHECK: liveins: $d0, $d1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
    ; CHECK: $d0 = COPY [[SELECT]](s64)
    ; CHECK: RET_ReallyLR implicit $d0
    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $d0
    %2:_(s64) = COPY $d1
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $d0 = COPY %4(s64)
    RET_ReallyLR implicit $d0

...
---
name:            two_fpr_inputs_gpr_output
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $d1, $w0
    ; CHECK-LABEL: name: two_fpr_inputs_gpr_output
    ; CHECK: liveins: $d0, $d1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK: [[COPY2:%[0-9]+]]:fpr(s64) = COPY $d1
    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
    ; CHECK: $x0 = COPY [[SELECT]](s64)
    ; CHECK: RET_ReallyLR implicit $x0

    ; Verify that the G_SELECT only has FPRs.
    ; The only difference between fcsel and csel are the register banks. So,
    ; if we have two FPR inputs and a GPR output, we should do a floating point
    ; select anyway. This will cost one copy for the output, but that's less
    ; than doing two to put the inputs on GPRs.

    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $d0
    %2:_(s64) = COPY $d1
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            one_fpr_input_fpr_output
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x1, $w0
    ; CHECK-LABEL: name: one_fpr_input_fpr_output
    ; CHECK: liveins: $d0, $x1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
    ; CHECK: [[COPY3:%[0-9]+]]:fpr(s64) = COPY [[COPY2]](s64)
    ; CHECK: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY3]]
    ; CHECK: $d0 = COPY [[SELECT]](s64)
    ; CHECK: RET_ReallyLR implicit $d0

    ; Same idea as the above test. If the output is an FPR, and one of the
    ; inputs is an FPR, then it's fewer copies to just do a FCSEL.

    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $d0
    %2:_(s64) = COPY $x1
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $d0 = COPY %4(s64)
    RET_ReallyLR implicit $d0

...
---
name:            one_fpr_input_gpr_output
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $d0, $x1, $w0
    ; CHECK-LABEL: name: one_fpr_input_gpr_output
    ; CHECK: liveins: $d0, $x1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:fpr(s64) = COPY $d0
    ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
    ; CHECK: [[COPY3:%[0-9]+]]:gpr(s64) = COPY [[COPY1]](s64)
    ; CHECK: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY3]], [[COPY2]]
    ; CHECK: $x0 = COPY [[SELECT]](s64)
    ; CHECK: RET_ReallyLR implicit $x0

    ; Now we have more GPR registers on the G_SELECT. It's cheaper here to put
    ; everything on GPR.

    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $d0
    %2:_(s64) = COPY $x1
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $x0 = COPY %4(s64)
    RET_ReallyLR implicit $x0

...
---
name:            two_gpr_input_fpr_output
alignment:       4
legalized:       true
tracksRegLiveness: true
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0, $x1, $w0
    ; CHECK-LABEL: name: two_gpr_input_fpr_output
    ; CHECK: liveins: $x0, $x1, $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x0
    ; CHECK: [[COPY2:%[0-9]+]]:gpr(s64) = COPY $x1
    ; CHECK: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]
    ; CHECK: $d0 = COPY [[SELECT]](s64)
    ; CHECK: RET_ReallyLR implicit $d0

    ; Same as above. The G_SELECT should get all GPRS.

    %3:_(s32) = COPY $w0
    %0:_(s1) = G_TRUNC %3(s32)
    %1:_(s64) = COPY $x0
    %2:_(s64) = COPY $x1
    %4:_(s64) = G_SELECT %0(s1), %1, %2
    $d0 = COPY %4(s64)
    RET_ReallyLR implicit $d0