1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides basic encoding and assembly information for AArch64.
11 //
12 //===----------------------------------------------------------------------===//
13
14 /* Capstone Disassembly Engine */
15 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17 #ifdef CAPSTONE_HAS_ARM64
18
19 #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64)
20 #pragma warning(disable:4996) // disable MSVC's warning on strcpy()
21 #pragma warning(disable:28719) // disable MSVC's warning on strcpy()
22 #endif
23
24 #include "../../utils.h"
25
26 #include <stdio.h>
27 #include <stdlib.h>
28
29 #include "AArch64BaseInfo.h"
30
A64NamedImmMapper_toString(const A64NamedImmMapper * N,uint32_t Value,bool * Valid)31 const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
32 {
33 unsigned i;
34 for (i = 0; i < N->NumPairs; ++i) {
35 if (N->Pairs[i].Value == Value) {
36 *Valid = true;
37 return N->Pairs[i].Name;
38 }
39 }
40
41 *Valid = false;
42 return 0;
43 }
44
45 // compare s1 with lower(s2)
46 // return true if s1 == lower(f2), and false otherwise
compare_lower_str(const char * s1,const char * s2)47 static bool compare_lower_str(const char *s1, const char *s2)
48 {
49 bool res;
50 char *lower = cs_strdup(s2), *c;
51 for (c = lower; *c; c++)
52 *c = (char)tolower((int) *c);
53
54 res = (strcmp(s1, lower) == 0);
55 cs_mem_free(lower);
56
57 return res;
58 }
59
A64NamedImmMapper_fromString(const A64NamedImmMapper * N,char * Name,bool * Valid)60 uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid)
61 {
62 unsigned i;
63 for (i = 0; i < N->NumPairs; ++i) {
64 if (compare_lower_str(N->Pairs[i].Name, Name)) {
65 *Valid = true;
66 return N->Pairs[i].Value;
67 }
68 }
69
70 *Valid = false;
71 return (uint32_t)-1;
72 }
73
A64NamedImmMapper_validImm(const A64NamedImmMapper * N,uint32_t Value)74 bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value)
75 {
76 return Value < N->TooBigImm;
77 }
78
79 // return a string representing the number X
80 // NOTE: caller must free() the result itself to avoid memory leak
utostr(uint64_t X,bool isNeg)81 static char *utostr(uint64_t X, bool isNeg)
82 {
83 char Buffer[22];
84 char *BufPtr = Buffer+21;
85 char *result;
86
87 Buffer[21] = '\0';
88 if (X == 0) *--BufPtr = '0'; // Handle special case...
89
90 while (X) {
91 *--BufPtr = X % 10 + '0';
92 X /= 10;
93 }
94
95 if (isNeg) *--BufPtr = '-'; // Add negative sign...
96
97 result = cs_strdup(BufPtr);
98 return result;
99 }
100
101 static const A64NamedImmMapper_Mapping SysRegPairs[] = {
102 {"pan", A64SysReg_PAN},
103 {"uao", A64SysReg_UAO},
104 {"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
105 {"osdtrtx_el1", A64SysReg_OSDTRTX_EL1},
106 {"teecr32_el1", A64SysReg_TEECR32_EL1},
107 {"mdccint_el1", A64SysReg_MDCCINT_EL1},
108 {"mdscr_el1", A64SysReg_MDSCR_EL1},
109 {"dbgdtr_el0", A64SysReg_DBGDTR_EL0},
110 {"oseccr_el1", A64SysReg_OSECCR_EL1},
111 {"dbgvcr32_el2", A64SysReg_DBGVCR32_EL2},
112 {"dbgbvr0_el1", A64SysReg_DBGBVR0_EL1},
113 {"dbgbvr1_el1", A64SysReg_DBGBVR1_EL1},
114 {"dbgbvr2_el1", A64SysReg_DBGBVR2_EL1},
115 {"dbgbvr3_el1", A64SysReg_DBGBVR3_EL1},
116 {"dbgbvr4_el1", A64SysReg_DBGBVR4_EL1},
117 {"dbgbvr5_el1", A64SysReg_DBGBVR5_EL1},
118 {"dbgbvr6_el1", A64SysReg_DBGBVR6_EL1},
119 {"dbgbvr7_el1", A64SysReg_DBGBVR7_EL1},
120 {"dbgbvr8_el1", A64SysReg_DBGBVR8_EL1},
121 {"dbgbvr9_el1", A64SysReg_DBGBVR9_EL1},
122 {"dbgbvr10_el1", A64SysReg_DBGBVR10_EL1},
123 {"dbgbvr11_el1", A64SysReg_DBGBVR11_EL1},
124 {"dbgbvr12_el1", A64SysReg_DBGBVR12_EL1},
125 {"dbgbvr13_el1", A64SysReg_DBGBVR13_EL1},
126 {"dbgbvr14_el1", A64SysReg_DBGBVR14_EL1},
127 {"dbgbvr15_el1", A64SysReg_DBGBVR15_EL1},
128 {"dbgbcr0_el1", A64SysReg_DBGBCR0_EL1},
129 {"dbgbcr1_el1", A64SysReg_DBGBCR1_EL1},
130 {"dbgbcr2_el1", A64SysReg_DBGBCR2_EL1},
131 {"dbgbcr3_el1", A64SysReg_DBGBCR3_EL1},
132 {"dbgbcr4_el1", A64SysReg_DBGBCR4_EL1},
133 {"dbgbcr5_el1", A64SysReg_DBGBCR5_EL1},
134 {"dbgbcr6_el1", A64SysReg_DBGBCR6_EL1},
135 {"dbgbcr7_el1", A64SysReg_DBGBCR7_EL1},
136 {"dbgbcr8_el1", A64SysReg_DBGBCR8_EL1},
137 {"dbgbcr9_el1", A64SysReg_DBGBCR9_EL1},
138 {"dbgbcr10_el1", A64SysReg_DBGBCR10_EL1},
139 {"dbgbcr11_el1", A64SysReg_DBGBCR11_EL1},
140 {"dbgbcr12_el1", A64SysReg_DBGBCR12_EL1},
141 {"dbgbcr13_el1", A64SysReg_DBGBCR13_EL1},
142 {"dbgbcr14_el1", A64SysReg_DBGBCR14_EL1},
143 {"dbgbcr15_el1", A64SysReg_DBGBCR15_EL1},
144 {"dbgwvr0_el1", A64SysReg_DBGWVR0_EL1},
145 {"dbgwvr1_el1", A64SysReg_DBGWVR1_EL1},
146 {"dbgwvr2_el1", A64SysReg_DBGWVR2_EL1},
147 {"dbgwvr3_el1", A64SysReg_DBGWVR3_EL1},
148 {"dbgwvr4_el1", A64SysReg_DBGWVR4_EL1},
149 {"dbgwvr5_el1", A64SysReg_DBGWVR5_EL1},
150 {"dbgwvr6_el1", A64SysReg_DBGWVR6_EL1},
151 {"dbgwvr7_el1", A64SysReg_DBGWVR7_EL1},
152 {"dbgwvr8_el1", A64SysReg_DBGWVR8_EL1},
153 {"dbgwvr9_el1", A64SysReg_DBGWVR9_EL1},
154 {"dbgwvr10_el1", A64SysReg_DBGWVR10_EL1},
155 {"dbgwvr11_el1", A64SysReg_DBGWVR11_EL1},
156 {"dbgwvr12_el1", A64SysReg_DBGWVR12_EL1},
157 {"dbgwvr13_el1", A64SysReg_DBGWVR13_EL1},
158 {"dbgwvr14_el1", A64SysReg_DBGWVR14_EL1},
159 {"dbgwvr15_el1", A64SysReg_DBGWVR15_EL1},
160 {"dbgwcr0_el1", A64SysReg_DBGWCR0_EL1},
161 {"dbgwcr1_el1", A64SysReg_DBGWCR1_EL1},
162 {"dbgwcr2_el1", A64SysReg_DBGWCR2_EL1},
163 {"dbgwcr3_el1", A64SysReg_DBGWCR3_EL1},
164 {"dbgwcr4_el1", A64SysReg_DBGWCR4_EL1},
165 {"dbgwcr5_el1", A64SysReg_DBGWCR5_EL1},
166 {"dbgwcr6_el1", A64SysReg_DBGWCR6_EL1},
167 {"dbgwcr7_el1", A64SysReg_DBGWCR7_EL1},
168 {"dbgwcr8_el1", A64SysReg_DBGWCR8_EL1},
169 {"dbgwcr9_el1", A64SysReg_DBGWCR9_EL1},
170 {"dbgwcr10_el1", A64SysReg_DBGWCR10_EL1},
171 {"dbgwcr11_el1", A64SysReg_DBGWCR11_EL1},
172 {"dbgwcr12_el1", A64SysReg_DBGWCR12_EL1},
173 {"dbgwcr13_el1", A64SysReg_DBGWCR13_EL1},
174 {"dbgwcr14_el1", A64SysReg_DBGWCR14_EL1},
175 {"dbgwcr15_el1", A64SysReg_DBGWCR15_EL1},
176 {"teehbr32_el1", A64SysReg_TEEHBR32_EL1},
177 {"osdlr_el1", A64SysReg_OSDLR_EL1},
178 {"dbgprcr_el1", A64SysReg_DBGPRCR_EL1},
179 {"dbgclaimset_el1", A64SysReg_DBGCLAIMSET_EL1},
180 {"dbgclaimclr_el1", A64SysReg_DBGCLAIMCLR_EL1},
181 {"csselr_el1", A64SysReg_CSSELR_EL1},
182 {"vpidr_el2", A64SysReg_VPIDR_EL2},
183 {"vmpidr_el2", A64SysReg_VMPIDR_EL2},
184 {"sctlr_el1", A64SysReg_SCTLR_EL1},
185 {"sctlr_el12", A64SysReg_SCTLR_EL12},
186 {"sctlr_el2", A64SysReg_SCTLR_EL2},
187 {"sctlr_el3", A64SysReg_SCTLR_EL3},
188 {"actlr_el1", A64SysReg_ACTLR_EL1},
189 {"actlr_el2", A64SysReg_ACTLR_EL2},
190 {"actlr_el3", A64SysReg_ACTLR_EL3},
191 {"cpacr_el1", A64SysReg_CPACR_EL1},
192 {"cpacr_el12", A64SysReg_CPACR_EL12},
193 {"hcr_el2", A64SysReg_HCR_EL2},
194 {"scr_el3", A64SysReg_SCR_EL3},
195 {"mdcr_el2", A64SysReg_MDCR_EL2},
196 {"sder32_el3", A64SysReg_SDER32_EL3},
197 {"cptr_el2", A64SysReg_CPTR_EL2},
198 {"cptr_el3", A64SysReg_CPTR_EL3},
199 {"hstr_el2", A64SysReg_HSTR_EL2},
200 {"hacr_el2", A64SysReg_HACR_EL2},
201 {"mdcr_el3", A64SysReg_MDCR_EL3},
202 {"ttbr0_el1", A64SysReg_TTBR0_EL1},
203 {"ttbr0_el12", A64SysReg_TTBR0_EL12},
204 {"ttbr0_el2", A64SysReg_TTBR0_EL2},
205 {"ttbr0_el3", A64SysReg_TTBR0_EL3},
206 {"ttbr1_el1", A64SysReg_TTBR1_EL1},
207 {"ttbr1_el12", A64SysReg_TTBR1_EL12},
208 {"ttbr1_el2", A64SysReg_TTBR1_EL2},
209 {"tcr_el1", A64SysReg_TCR_EL1},
210 {"tcr_el12", A64SysReg_TCR_EL12},
211 {"tcr_el2", A64SysReg_TCR_EL2},
212 {"tcr_el3", A64SysReg_TCR_EL3},
213 {"vttbr_el2", A64SysReg_VTTBR_EL2},
214 {"vtcr_el2", A64SysReg_VTCR_EL2},
215 {"dacr32_el2", A64SysReg_DACR32_EL2},
216 {"spsr_el1", A64SysReg_SPSR_EL1},
217 {"spsr_el12", A64SysReg_SPSR_EL12},
218 {"spsr_el2", A64SysReg_SPSR_EL2},
219 {"spsr_el3", A64SysReg_SPSR_EL3},
220 {"elr_el1", A64SysReg_ELR_EL1},
221 {"elr_el12", A64SysReg_ELR_EL12},
222 {"elr_el2", A64SysReg_ELR_EL2},
223 {"elr_el3", A64SysReg_ELR_EL3},
224 {"sp_el0", A64SysReg_SP_EL0},
225 {"sp_el1", A64SysReg_SP_EL1},
226 {"sp_el2", A64SysReg_SP_EL2},
227 {"spsel", A64SysReg_SPSel},
228 {"nzcv", A64SysReg_NZCV},
229 {"daif", A64SysReg_DAIF},
230 {"currentel", A64SysReg_CurrentEL},
231 {"spsr_irq", A64SysReg_SPSR_irq},
232 {"spsr_abt", A64SysReg_SPSR_abt},
233 {"spsr_und", A64SysReg_SPSR_und},
234 {"spsr_fiq", A64SysReg_SPSR_fiq},
235 {"fpcr", A64SysReg_FPCR},
236 {"fpsr", A64SysReg_FPSR},
237 {"dspsr_el0", A64SysReg_DSPSR_EL0},
238 {"dlr_el0", A64SysReg_DLR_EL0},
239 {"ifsr32_el2", A64SysReg_IFSR32_EL2},
240 {"afsr0_el1", A64SysReg_AFSR0_EL1},
241 {"afsr0_el12", A64SysReg_AFSR0_EL12},
242 {"afsr0_el2", A64SysReg_AFSR0_EL2},
243 {"afsr0_el3", A64SysReg_AFSR0_EL3},
244 {"afsr1_el1", A64SysReg_AFSR1_EL1},
245 {"afsr1_el12", A64SysReg_AFSR1_EL12},
246 {"afsr1_el2", A64SysReg_AFSR1_EL2},
247 {"afsr1_el3", A64SysReg_AFSR1_EL3},
248 {"esr_el1", A64SysReg_ESR_EL1},
249 {"esr_el12", A64SysReg_ESR_EL12},
250 {"esr_el2", A64SysReg_ESR_EL2},
251 {"esr_el3", A64SysReg_ESR_EL3},
252 {"fpexc32_el2", A64SysReg_FPEXC32_EL2},
253 {"far_el1", A64SysReg_FAR_EL1},
254 {"far_el12", A64SysReg_FAR_EL12},
255 {"far_el2", A64SysReg_FAR_EL2},
256 {"far_el3", A64SysReg_FAR_EL3},
257 {"hpfar_el2", A64SysReg_HPFAR_EL2},
258 {"par_el1", A64SysReg_PAR_EL1},
259 {"pmcr_el0", A64SysReg_PMCR_EL0},
260 {"pmcntenset_el0", A64SysReg_PMCNTENSET_EL0},
261 {"pmcntenclr_el0", A64SysReg_PMCNTENCLR_EL0},
262 {"pmovsclr_el0", A64SysReg_PMOVSCLR_EL0},
263 {"pmselr_el0", A64SysReg_PMSELR_EL0},
264 {"pmccntr_el0", A64SysReg_PMCCNTR_EL0},
265 {"pmxevtyper_el0", A64SysReg_PMXEVTYPER_EL0},
266 {"pmxevcntr_el0", A64SysReg_PMXEVCNTR_EL0},
267 {"pmuserenr_el0", A64SysReg_PMUSERENR_EL0},
268 {"pmintenset_el1", A64SysReg_PMINTENSET_EL1},
269 {"pmintenclr_el1", A64SysReg_PMINTENCLR_EL1},
270 {"pmovsset_el0", A64SysReg_PMOVSSET_EL0},
271 {"mair_el1", A64SysReg_MAIR_EL1},
272 {"mair_el12", A64SysReg_MAIR_EL12},
273 {"mair_el2", A64SysReg_MAIR_EL2},
274 {"mair_el3", A64SysReg_MAIR_EL3},
275 {"amair_el1", A64SysReg_AMAIR_EL1},
276 {"amair_el12", A64SysReg_AMAIR_EL12},
277 {"amair_el2", A64SysReg_AMAIR_EL2},
278 {"amair_el3", A64SysReg_AMAIR_EL3},
279 {"vbar_el1", A64SysReg_VBAR_EL1},
280 {"vbar_el12", A64SysReg_VBAR_EL12},
281 {"vbar_el2", A64SysReg_VBAR_EL2},
282 {"vbar_el3", A64SysReg_VBAR_EL3},
283 {"rmr_el1", A64SysReg_RMR_EL1},
284 {"rmr_el2", A64SysReg_RMR_EL2},
285 {"rmr_el3", A64SysReg_RMR_EL3},
286 {"contextidr_el1", A64SysReg_CONTEXTIDR_EL1},
287 {"contextidr_el12", A64SysReg_CONTEXTIDR_EL12},
288 {"contextidr_el2", A64SysReg_CONTEXTIDR_EL2},
289 {"tpidr_el0", A64SysReg_TPIDR_EL0},
290 {"tpidr_el2", A64SysReg_TPIDR_EL2},
291 {"tpidr_el3", A64SysReg_TPIDR_EL3},
292 {"tpidrro_el0", A64SysReg_TPIDRRO_EL0},
293 {"tpidr_el1", A64SysReg_TPIDR_EL1},
294 {"cntfrq_el0", A64SysReg_CNTFRQ_EL0},
295 {"cntvoff_el2", A64SysReg_CNTVOFF_EL2},
296 {"cntkctl_el1", A64SysReg_CNTKCTL_EL1},
297 {"cntkctl_el12", A64SysReg_CNTKCTL_EL12},
298 {"cnthctl_el2", A64SysReg_CNTHCTL_EL2},
299 {"cntp_tval_el0", A64SysReg_CNTP_TVAL_EL0},
300 {"cntp_tval_el02", A64SysReg_CNTP_TVAL_EL02},
301 {"cnthp_tval_el2", A64SysReg_CNTHP_TVAL_EL2},
302 {"cntps_tval_el1", A64SysReg_CNTPS_TVAL_EL1},
303 {"cntp_ctl_el0", A64SysReg_CNTP_CTL_EL0},
304 {"cnthp_ctl_el2", A64SysReg_CNTHP_CTL_EL2},
305 {"cnthv_ctl_el2", A64SysReg_CNTHVCTL_EL2},
306 {"cnthv_cval_el2", A64SysReg_CNTHV_CVAL_EL2},
307 {"cnthv_tval_el2", A64SysReg_CNTHV_TVAL_EL2},
308 {"cntps_ctl_el1", A64SysReg_CNTPS_CTL_EL1},
309 {"cntp_cval_el0", A64SysReg_CNTP_CVAL_EL0},
310 {"cntp_cval_el02", A64SysReg_CNTP_CVAL_EL02},
311 {"cnthp_cval_el2", A64SysReg_CNTHP_CVAL_EL2},
312 {"cntps_cval_el1", A64SysReg_CNTPS_CVAL_EL1},
313 {"cntv_tval_el0", A64SysReg_CNTV_TVAL_EL0},
314 {"cntv_tval_el02", A64SysReg_CNTV_TVAL_EL02},
315 {"cntv_ctl_el0", A64SysReg_CNTV_CTL_EL0},
316 {"cntv_ctl_el02", A64SysReg_CNTV_CTL_EL02},
317 {"cntv_cval_el0", A64SysReg_CNTV_CVAL_EL0},
318 {"cntv_cval_el02", A64SysReg_CNTV_CVAL_EL02},
319 {"pmevcntr0_el0", A64SysReg_PMEVCNTR0_EL0},
320 {"pmevcntr1_el0", A64SysReg_PMEVCNTR1_EL0},
321 {"pmevcntr2_el0", A64SysReg_PMEVCNTR2_EL0},
322 {"pmevcntr3_el0", A64SysReg_PMEVCNTR3_EL0},
323 {"pmevcntr4_el0", A64SysReg_PMEVCNTR4_EL0},
324 {"pmevcntr5_el0", A64SysReg_PMEVCNTR5_EL0},
325 {"pmevcntr6_el0", A64SysReg_PMEVCNTR6_EL0},
326 {"pmevcntr7_el0", A64SysReg_PMEVCNTR7_EL0},
327 {"pmevcntr8_el0", A64SysReg_PMEVCNTR8_EL0},
328 {"pmevcntr9_el0", A64SysReg_PMEVCNTR9_EL0},
329 {"pmevcntr10_el0", A64SysReg_PMEVCNTR10_EL0},
330 {"pmevcntr11_el0", A64SysReg_PMEVCNTR11_EL0},
331 {"pmevcntr12_el0", A64SysReg_PMEVCNTR12_EL0},
332 {"pmevcntr13_el0", A64SysReg_PMEVCNTR13_EL0},
333 {"pmevcntr14_el0", A64SysReg_PMEVCNTR14_EL0},
334 {"pmevcntr15_el0", A64SysReg_PMEVCNTR15_EL0},
335 {"pmevcntr16_el0", A64SysReg_PMEVCNTR16_EL0},
336 {"pmevcntr17_el0", A64SysReg_PMEVCNTR17_EL0},
337 {"pmevcntr18_el0", A64SysReg_PMEVCNTR18_EL0},
338 {"pmevcntr19_el0", A64SysReg_PMEVCNTR19_EL0},
339 {"pmevcntr20_el0", A64SysReg_PMEVCNTR20_EL0},
340 {"pmevcntr21_el0", A64SysReg_PMEVCNTR21_EL0},
341 {"pmevcntr22_el0", A64SysReg_PMEVCNTR22_EL0},
342 {"pmevcntr23_el0", A64SysReg_PMEVCNTR23_EL0},
343 {"pmevcntr24_el0", A64SysReg_PMEVCNTR24_EL0},
344 {"pmevcntr25_el0", A64SysReg_PMEVCNTR25_EL0},
345 {"pmevcntr26_el0", A64SysReg_PMEVCNTR26_EL0},
346 {"pmevcntr27_el0", A64SysReg_PMEVCNTR27_EL0},
347 {"pmevcntr28_el0", A64SysReg_PMEVCNTR28_EL0},
348 {"pmevcntr29_el0", A64SysReg_PMEVCNTR29_EL0},
349 {"pmevcntr30_el0", A64SysReg_PMEVCNTR30_EL0},
350 {"pmccfiltr_el0", A64SysReg_PMCCFILTR_EL0},
351 {"pmevtyper0_el0", A64SysReg_PMEVTYPER0_EL0},
352 {"pmevtyper1_el0", A64SysReg_PMEVTYPER1_EL0},
353 {"pmevtyper2_el0", A64SysReg_PMEVTYPER2_EL0},
354 {"pmevtyper3_el0", A64SysReg_PMEVTYPER3_EL0},
355 {"pmevtyper4_el0", A64SysReg_PMEVTYPER4_EL0},
356 {"pmevtyper5_el0", A64SysReg_PMEVTYPER5_EL0},
357 {"pmevtyper6_el0", A64SysReg_PMEVTYPER6_EL0},
358 {"pmevtyper7_el0", A64SysReg_PMEVTYPER7_EL0},
359 {"pmevtyper8_el0", A64SysReg_PMEVTYPER8_EL0},
360 {"pmevtyper9_el0", A64SysReg_PMEVTYPER9_EL0},
361 {"pmevtyper10_el0", A64SysReg_PMEVTYPER10_EL0},
362 {"pmevtyper11_el0", A64SysReg_PMEVTYPER11_EL0},
363 {"pmevtyper12_el0", A64SysReg_PMEVTYPER12_EL0},
364 {"pmevtyper13_el0", A64SysReg_PMEVTYPER13_EL0},
365 {"pmevtyper14_el0", A64SysReg_PMEVTYPER14_EL0},
366 {"pmevtyper15_el0", A64SysReg_PMEVTYPER15_EL0},
367 {"pmevtyper16_el0", A64SysReg_PMEVTYPER16_EL0},
368 {"pmevtyper17_el0", A64SysReg_PMEVTYPER17_EL0},
369 {"pmevtyper18_el0", A64SysReg_PMEVTYPER18_EL0},
370 {"pmevtyper19_el0", A64SysReg_PMEVTYPER19_EL0},
371 {"pmevtyper20_el0", A64SysReg_PMEVTYPER20_EL0},
372 {"pmevtyper21_el0", A64SysReg_PMEVTYPER21_EL0},
373 {"pmevtyper22_el0", A64SysReg_PMEVTYPER22_EL0},
374 {"pmevtyper23_el0", A64SysReg_PMEVTYPER23_EL0},
375 {"pmevtyper24_el0", A64SysReg_PMEVTYPER24_EL0},
376 {"pmevtyper25_el0", A64SysReg_PMEVTYPER25_EL0},
377 {"pmevtyper26_el0", A64SysReg_PMEVTYPER26_EL0},
378 {"pmevtyper27_el0", A64SysReg_PMEVTYPER27_EL0},
379 {"pmevtyper28_el0", A64SysReg_PMEVTYPER28_EL0},
380 {"pmevtyper29_el0", A64SysReg_PMEVTYPER29_EL0},
381 {"pmevtyper30_el0", A64SysReg_PMEVTYPER30_EL0},
382 {"lorc_el1", A64SysReg_LORC_EL1},
383 {"lorea_el1", A64SysReg_LOREA_EL1},
384 {"lorn_el1", A64SysReg_LORN_EL1},
385 {"lorsa_el1", A64SysReg_LORSA_EL1},
386
387 // Trace registers
388 {"trcprgctlr", A64SysReg_TRCPRGCTLR},
389 {"trcprocselr", A64SysReg_TRCPROCSELR},
390 {"trcconfigr", A64SysReg_TRCCONFIGR},
391 {"trcauxctlr", A64SysReg_TRCAUXCTLR},
392 {"trceventctl0r", A64SysReg_TRCEVENTCTL0R},
393 {"trceventctl1r", A64SysReg_TRCEVENTCTL1R},
394 {"trcstallctlr", A64SysReg_TRCSTALLCTLR},
395 {"trctsctlr", A64SysReg_TRCTSCTLR},
396 {"trcsyncpr", A64SysReg_TRCSYNCPR},
397 {"trcccctlr", A64SysReg_TRCCCCTLR},
398 {"trcbbctlr", A64SysReg_TRCBBCTLR},
399 {"trctraceidr", A64SysReg_TRCTRACEIDR},
400 {"trcqctlr", A64SysReg_TRCQCTLR},
401 {"trcvictlr", A64SysReg_TRCVICTLR},
402 {"trcviiectlr", A64SysReg_TRCVIIECTLR},
403 {"trcvissctlr", A64SysReg_TRCVISSCTLR},
404 {"trcvipcssctlr", A64SysReg_TRCVIPCSSCTLR},
405 {"trcvdctlr", A64SysReg_TRCVDCTLR},
406 {"trcvdsacctlr", A64SysReg_TRCVDSACCTLR},
407 {"trcvdarcctlr", A64SysReg_TRCVDARCCTLR},
408 {"trcseqevr0", A64SysReg_TRCSEQEVR0},
409 {"trcseqevr1", A64SysReg_TRCSEQEVR1},
410 {"trcseqevr2", A64SysReg_TRCSEQEVR2},
411 {"trcseqrstevr", A64SysReg_TRCSEQRSTEVR},
412 {"trcseqstr", A64SysReg_TRCSEQSTR},
413 {"trcextinselr", A64SysReg_TRCEXTINSELR},
414 {"trccntrldvr0", A64SysReg_TRCCNTRLDVR0},
415 {"trccntrldvr1", A64SysReg_TRCCNTRLDVR1},
416 {"trccntrldvr2", A64SysReg_TRCCNTRLDVR2},
417 {"trccntrldvr3", A64SysReg_TRCCNTRLDVR3},
418 {"trccntctlr0", A64SysReg_TRCCNTCTLR0},
419 {"trccntctlr1", A64SysReg_TRCCNTCTLR1},
420 {"trccntctlr2", A64SysReg_TRCCNTCTLR2},
421 {"trccntctlr3", A64SysReg_TRCCNTCTLR3},
422 {"trccntvr0", A64SysReg_TRCCNTVR0},
423 {"trccntvr1", A64SysReg_TRCCNTVR1},
424 {"trccntvr2", A64SysReg_TRCCNTVR2},
425 {"trccntvr3", A64SysReg_TRCCNTVR3},
426 {"trcimspec0", A64SysReg_TRCIMSPEC0},
427 {"trcimspec1", A64SysReg_TRCIMSPEC1},
428 {"trcimspec2", A64SysReg_TRCIMSPEC2},
429 {"trcimspec3", A64SysReg_TRCIMSPEC3},
430 {"trcimspec4", A64SysReg_TRCIMSPEC4},
431 {"trcimspec5", A64SysReg_TRCIMSPEC5},
432 {"trcimspec6", A64SysReg_TRCIMSPEC6},
433 {"trcimspec7", A64SysReg_TRCIMSPEC7},
434 {"trcrsctlr2", A64SysReg_TRCRSCTLR2},
435 {"trcrsctlr3", A64SysReg_TRCRSCTLR3},
436 {"trcrsctlr4", A64SysReg_TRCRSCTLR4},
437 {"trcrsctlr5", A64SysReg_TRCRSCTLR5},
438 {"trcrsctlr6", A64SysReg_TRCRSCTLR6},
439 {"trcrsctlr7", A64SysReg_TRCRSCTLR7},
440 {"trcrsctlr8", A64SysReg_TRCRSCTLR8},
441 {"trcrsctlr9", A64SysReg_TRCRSCTLR9},
442 {"trcrsctlr10", A64SysReg_TRCRSCTLR10},
443 {"trcrsctlr11", A64SysReg_TRCRSCTLR11},
444 {"trcrsctlr12", A64SysReg_TRCRSCTLR12},
445 {"trcrsctlr13", A64SysReg_TRCRSCTLR13},
446 {"trcrsctlr14", A64SysReg_TRCRSCTLR14},
447 {"trcrsctlr15", A64SysReg_TRCRSCTLR15},
448 {"trcrsctlr16", A64SysReg_TRCRSCTLR16},
449 {"trcrsctlr17", A64SysReg_TRCRSCTLR17},
450 {"trcrsctlr18", A64SysReg_TRCRSCTLR18},
451 {"trcrsctlr19", A64SysReg_TRCRSCTLR19},
452 {"trcrsctlr20", A64SysReg_TRCRSCTLR20},
453 {"trcrsctlr21", A64SysReg_TRCRSCTLR21},
454 {"trcrsctlr22", A64SysReg_TRCRSCTLR22},
455 {"trcrsctlr23", A64SysReg_TRCRSCTLR23},
456 {"trcrsctlr24", A64SysReg_TRCRSCTLR24},
457 {"trcrsctlr25", A64SysReg_TRCRSCTLR25},
458 {"trcrsctlr26", A64SysReg_TRCRSCTLR26},
459 {"trcrsctlr27", A64SysReg_TRCRSCTLR27},
460 {"trcrsctlr28", A64SysReg_TRCRSCTLR28},
461 {"trcrsctlr29", A64SysReg_TRCRSCTLR29},
462 {"trcrsctlr30", A64SysReg_TRCRSCTLR30},
463 {"trcrsctlr31", A64SysReg_TRCRSCTLR31},
464 {"trcssccr0", A64SysReg_TRCSSCCR0},
465 {"trcssccr1", A64SysReg_TRCSSCCR1},
466 {"trcssccr2", A64SysReg_TRCSSCCR2},
467 {"trcssccr3", A64SysReg_TRCSSCCR3},
468 {"trcssccr4", A64SysReg_TRCSSCCR4},
469 {"trcssccr5", A64SysReg_TRCSSCCR5},
470 {"trcssccr6", A64SysReg_TRCSSCCR6},
471 {"trcssccr7", A64SysReg_TRCSSCCR7},
472 {"trcsscsr0", A64SysReg_TRCSSCSR0},
473 {"trcsscsr1", A64SysReg_TRCSSCSR1},
474 {"trcsscsr2", A64SysReg_TRCSSCSR2},
475 {"trcsscsr3", A64SysReg_TRCSSCSR3},
476 {"trcsscsr4", A64SysReg_TRCSSCSR4},
477 {"trcsscsr5", A64SysReg_TRCSSCSR5},
478 {"trcsscsr6", A64SysReg_TRCSSCSR6},
479 {"trcsscsr7", A64SysReg_TRCSSCSR7},
480 {"trcsspcicr0", A64SysReg_TRCSSPCICR0},
481 {"trcsspcicr1", A64SysReg_TRCSSPCICR1},
482 {"trcsspcicr2", A64SysReg_TRCSSPCICR2},
483 {"trcsspcicr3", A64SysReg_TRCSSPCICR3},
484 {"trcsspcicr4", A64SysReg_TRCSSPCICR4},
485 {"trcsspcicr5", A64SysReg_TRCSSPCICR5},
486 {"trcsspcicr6", A64SysReg_TRCSSPCICR6},
487 {"trcsspcicr7", A64SysReg_TRCSSPCICR7},
488 {"trcpdcr", A64SysReg_TRCPDCR},
489 {"trcacvr0", A64SysReg_TRCACVR0},
490 {"trcacvr1", A64SysReg_TRCACVR1},
491 {"trcacvr2", A64SysReg_TRCACVR2},
492 {"trcacvr3", A64SysReg_TRCACVR3},
493 {"trcacvr4", A64SysReg_TRCACVR4},
494 {"trcacvr5", A64SysReg_TRCACVR5},
495 {"trcacvr6", A64SysReg_TRCACVR6},
496 {"trcacvr7", A64SysReg_TRCACVR7},
497 {"trcacvr8", A64SysReg_TRCACVR8},
498 {"trcacvr9", A64SysReg_TRCACVR9},
499 {"trcacvr10", A64SysReg_TRCACVR10},
500 {"trcacvr11", A64SysReg_TRCACVR11},
501 {"trcacvr12", A64SysReg_TRCACVR12},
502 {"trcacvr13", A64SysReg_TRCACVR13},
503 {"trcacvr14", A64SysReg_TRCACVR14},
504 {"trcacvr15", A64SysReg_TRCACVR15},
505 {"trcacatr0", A64SysReg_TRCACATR0},
506 {"trcacatr1", A64SysReg_TRCACATR1},
507 {"trcacatr2", A64SysReg_TRCACATR2},
508 {"trcacatr3", A64SysReg_TRCACATR3},
509 {"trcacatr4", A64SysReg_TRCACATR4},
510 {"trcacatr5", A64SysReg_TRCACATR5},
511 {"trcacatr6", A64SysReg_TRCACATR6},
512 {"trcacatr7", A64SysReg_TRCACATR7},
513 {"trcacatr8", A64SysReg_TRCACATR8},
514 {"trcacatr9", A64SysReg_TRCACATR9},
515 {"trcacatr10", A64SysReg_TRCACATR10},
516 {"trcacatr11", A64SysReg_TRCACATR11},
517 {"trcacatr12", A64SysReg_TRCACATR12},
518 {"trcacatr13", A64SysReg_TRCACATR13},
519 {"trcacatr14", A64SysReg_TRCACATR14},
520 {"trcacatr15", A64SysReg_TRCACATR15},
521 {"trcdvcvr0", A64SysReg_TRCDVCVR0},
522 {"trcdvcvr1", A64SysReg_TRCDVCVR1},
523 {"trcdvcvr2", A64SysReg_TRCDVCVR2},
524 {"trcdvcvr3", A64SysReg_TRCDVCVR3},
525 {"trcdvcvr4", A64SysReg_TRCDVCVR4},
526 {"trcdvcvr5", A64SysReg_TRCDVCVR5},
527 {"trcdvcvr6", A64SysReg_TRCDVCVR6},
528 {"trcdvcvr7", A64SysReg_TRCDVCVR7},
529 {"trcdvcmr0", A64SysReg_TRCDVCMR0},
530 {"trcdvcmr1", A64SysReg_TRCDVCMR1},
531 {"trcdvcmr2", A64SysReg_TRCDVCMR2},
532 {"trcdvcmr3", A64SysReg_TRCDVCMR3},
533 {"trcdvcmr4", A64SysReg_TRCDVCMR4},
534 {"trcdvcmr5", A64SysReg_TRCDVCMR5},
535 {"trcdvcmr6", A64SysReg_TRCDVCMR6},
536 {"trcdvcmr7", A64SysReg_TRCDVCMR7},
537 {"trccidcvr0", A64SysReg_TRCCIDCVR0},
538 {"trccidcvr1", A64SysReg_TRCCIDCVR1},
539 {"trccidcvr2", A64SysReg_TRCCIDCVR2},
540 {"trccidcvr3", A64SysReg_TRCCIDCVR3},
541 {"trccidcvr4", A64SysReg_TRCCIDCVR4},
542 {"trccidcvr5", A64SysReg_TRCCIDCVR5},
543 {"trccidcvr6", A64SysReg_TRCCIDCVR6},
544 {"trccidcvr7", A64SysReg_TRCCIDCVR7},
545 {"trcvmidcvr0", A64SysReg_TRCVMIDCVR0},
546 {"trcvmidcvr1", A64SysReg_TRCVMIDCVR1},
547 {"trcvmidcvr2", A64SysReg_TRCVMIDCVR2},
548 {"trcvmidcvr3", A64SysReg_TRCVMIDCVR3},
549 {"trcvmidcvr4", A64SysReg_TRCVMIDCVR4},
550 {"trcvmidcvr5", A64SysReg_TRCVMIDCVR5},
551 {"trcvmidcvr6", A64SysReg_TRCVMIDCVR6},
552 {"trcvmidcvr7", A64SysReg_TRCVMIDCVR7},
553 {"trccidcctlr0", A64SysReg_TRCCIDCCTLR0},
554 {"trccidcctlr1", A64SysReg_TRCCIDCCTLR1},
555 {"trcvmidcctlr0", A64SysReg_TRCVMIDCCTLR0},
556 {"trcvmidcctlr1", A64SysReg_TRCVMIDCCTLR1},
557 {"trcitctrl", A64SysReg_TRCITCTRL},
558 {"trcclaimset", A64SysReg_TRCCLAIMSET},
559 {"trcclaimclr", A64SysReg_TRCCLAIMCLR},
560
561 // GICv3 registers
562 {"icc_bpr1_el1", A64SysReg_ICC_BPR1_EL1},
563 {"icc_bpr0_el1", A64SysReg_ICC_BPR0_EL1},
564 {"icc_pmr_el1", A64SysReg_ICC_PMR_EL1},
565 {"icc_ctlr_el1", A64SysReg_ICC_CTLR_EL1},
566 {"icc_ctlr_el3", A64SysReg_ICC_CTLR_EL3},
567 {"icc_sre_el1", A64SysReg_ICC_SRE_EL1},
568 {"icc_sre_el2", A64SysReg_ICC_SRE_EL2},
569 {"icc_sre_el3", A64SysReg_ICC_SRE_EL3},
570 {"icc_igrpen0_el1", A64SysReg_ICC_IGRPEN0_EL1},
571 {"icc_igrpen1_el1", A64SysReg_ICC_IGRPEN1_EL1},
572 {"icc_igrpen1_el3", A64SysReg_ICC_IGRPEN1_EL3},
573 {"icc_seien_el1", A64SysReg_ICC_SEIEN_EL1},
574 {"icc_ap0r0_el1", A64SysReg_ICC_AP0R0_EL1},
575 {"icc_ap0r1_el1", A64SysReg_ICC_AP0R1_EL1},
576 {"icc_ap0r2_el1", A64SysReg_ICC_AP0R2_EL1},
577 {"icc_ap0r3_el1", A64SysReg_ICC_AP0R3_EL1},
578 {"icc_ap1r0_el1", A64SysReg_ICC_AP1R0_EL1},
579 {"icc_ap1r1_el1", A64SysReg_ICC_AP1R1_EL1},
580 {"icc_ap1r2_el1", A64SysReg_ICC_AP1R2_EL1},
581 {"icc_ap1r3_el1", A64SysReg_ICC_AP1R3_EL1},
582 {"ich_ap0r0_el2", A64SysReg_ICH_AP0R0_EL2},
583 {"ich_ap0r1_el2", A64SysReg_ICH_AP0R1_EL2},
584 {"ich_ap0r2_el2", A64SysReg_ICH_AP0R2_EL2},
585 {"ich_ap0r3_el2", A64SysReg_ICH_AP0R3_EL2},
586 {"ich_ap1r0_el2", A64SysReg_ICH_AP1R0_EL2},
587 {"ich_ap1r1_el2", A64SysReg_ICH_AP1R1_EL2},
588 {"ich_ap1r2_el2", A64SysReg_ICH_AP1R2_EL2},
589 {"ich_ap1r3_el2", A64SysReg_ICH_AP1R3_EL2},
590 {"ich_hcr_el2", A64SysReg_ICH_HCR_EL2},
591 {"ich_misr_el2", A64SysReg_ICH_MISR_EL2},
592 {"ich_vmcr_el2", A64SysReg_ICH_VMCR_EL2},
593 {"ich_vseir_el2", A64SysReg_ICH_VSEIR_EL2},
594 {"ich_lr0_el2", A64SysReg_ICH_LR0_EL2},
595 {"ich_lr1_el2", A64SysReg_ICH_LR1_EL2},
596 {"ich_lr2_el2", A64SysReg_ICH_LR2_EL2},
597 {"ich_lr3_el2", A64SysReg_ICH_LR3_EL2},
598 {"ich_lr4_el2", A64SysReg_ICH_LR4_EL2},
599 {"ich_lr5_el2", A64SysReg_ICH_LR5_EL2},
600 {"ich_lr6_el2", A64SysReg_ICH_LR6_EL2},
601 {"ich_lr7_el2", A64SysReg_ICH_LR7_EL2},
602 {"ich_lr8_el2", A64SysReg_ICH_LR8_EL2},
603 {"ich_lr9_el2", A64SysReg_ICH_LR9_EL2},
604 {"ich_lr10_el2", A64SysReg_ICH_LR10_EL2},
605 {"ich_lr11_el2", A64SysReg_ICH_LR11_EL2},
606 {"ich_lr12_el2", A64SysReg_ICH_LR12_EL2},
607 {"ich_lr13_el2", A64SysReg_ICH_LR13_EL2},
608 {"ich_lr14_el2", A64SysReg_ICH_LR14_EL2},
609 {"ich_lr15_el2", A64SysReg_ICH_LR15_EL2},
610
611 // Statistical profiling registers
612 {"pmblimitr_el1", A64SysReg_PMBLIMITR_EL1},
613 {"pmbptr_el1", A64SysReg_PMBPTR_EL1},
614 {"pmbsr_el1", A64SysReg_PMBSR_EL1},
615 {"pmscr_el1", A64SysReg_PMSCR_EL1},
616 {"pmscr_el12", A64SysReg_PMSCR_EL12},
617 {"pmscr_el2", A64SysReg_PMSCR_EL2},
618 {"pmsicr_el1", A64SysReg_PMSICR_EL1},
619 {"pmsirr_el1", A64SysReg_PMSIRR_EL1},
620 {"pmsfcr_el1", A64SysReg_PMSFCR_EL1},
621 {"pmsevfr_el1", A64SysReg_PMSEVFR_EL1},
622 {"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
623 };
624
625 static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
626 {"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
627 };
628
629 // result must be a big enough buffer: 128 bytes is more than enough
A64SysRegMapper_toString(const A64SysRegMapper * S,uint32_t Bits,char * result)630 void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
631 {
632 int dummy;
633 uint32_t Op0, Op1, CRn, CRm, Op2;
634 char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S;
635 unsigned i;
636
637 // First search the registers shared by all
638 for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
639 if (SysRegPairs[i].Value == Bits) {
640 strcpy(result, SysRegPairs[i].Name);
641 return;
642 }
643 }
644
645 // Next search for target specific registers
646 // if (FeatureBits & AArch64_ProcCyclone) {
647 if (true) {
648 for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
649 if (CycloneSysRegPairs[i].Value == Bits) {
650 strcpy(result, CycloneSysRegPairs[i].Name);
651 return;
652 }
653 }
654 }
655
656 // Now try the instruction-specific registers (either read-only or
657 // write-only).
658 for (i = 0; i < S->NumInstPairs; ++i) {
659 if (S->InstPairs[i].Value == Bits) {
660 strcpy(result, S->InstPairs[i].Name);
661 return;
662 }
663 }
664
665 Op0 = (Bits >> 14) & 0x3;
666 Op1 = (Bits >> 11) & 0x7;
667 CRn = (Bits >> 7) & 0xf;
668 CRm = (Bits >> 3) & 0xf;
669 Op2 = Bits & 0x7;
670
671 Op0S = utostr(Op0, false);
672 Op1S = utostr(Op1, false);
673 CRnS = utostr(CRn, false);
674 CRmS = utostr(CRm, false);
675 Op2S = utostr(Op2, false);
676
677 //printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S);
678 dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
679 (void)dummy;
680
681 cs_mem_free(Op0S);
682 cs_mem_free(Op1S);
683 cs_mem_free(CRnS);
684 cs_mem_free(CRmS);
685 cs_mem_free(Op2S);
686 }
687
688 static const A64NamedImmMapper_Mapping TLBIPairs[] = {
689 {"ipas2e1is", A64TLBI_IPAS2E1IS},
690 {"ipas2le1is", A64TLBI_IPAS2LE1IS},
691 {"vmalle1is", A64TLBI_VMALLE1IS},
692 {"alle2is", A64TLBI_ALLE2IS},
693 {"alle3is", A64TLBI_ALLE3IS},
694 {"vae1is", A64TLBI_VAE1IS},
695 {"vae2is", A64TLBI_VAE2IS},
696 {"vae3is", A64TLBI_VAE3IS},
697 {"aside1is", A64TLBI_ASIDE1IS},
698 {"vaae1is", A64TLBI_VAAE1IS},
699 {"alle1is", A64TLBI_ALLE1IS},
700 {"vale1is", A64TLBI_VALE1IS},
701 {"vale2is", A64TLBI_VALE2IS},
702 {"vale3is", A64TLBI_VALE3IS},
703 {"vmalls12e1is", A64TLBI_VMALLS12E1IS},
704 {"vaale1is", A64TLBI_VAALE1IS},
705 {"ipas2e1", A64TLBI_IPAS2E1},
706 {"ipas2le1", A64TLBI_IPAS2LE1},
707 {"vmalle1", A64TLBI_VMALLE1},
708 {"alle2", A64TLBI_ALLE2},
709 {"alle3", A64TLBI_ALLE3},
710 {"vae1", A64TLBI_VAE1},
711 {"vae2", A64TLBI_VAE2},
712 {"vae3", A64TLBI_VAE3},
713 {"aside1", A64TLBI_ASIDE1},
714 {"vaae1", A64TLBI_VAAE1},
715 {"alle1", A64TLBI_ALLE1},
716 {"vale1", A64TLBI_VALE1},
717 {"vale2", A64TLBI_VALE2},
718 {"vale3", A64TLBI_VALE3},
719 {"vmalls12e1", A64TLBI_VMALLS12E1},
720 {"vaale1", A64TLBI_VAALE1}
721 };
722
723 const A64NamedImmMapper A64TLBI_TLBIMapper = {
724 TLBIPairs,
725 ARR_SIZE(TLBIPairs),
726 0,
727 };
728
729 static const A64NamedImmMapper_Mapping ATPairs[] = {
730 {"s1e1r", A64AT_S1E1R},
731 {"s1e2r", A64AT_S1E2R},
732 {"s1e3r", A64AT_S1E3R},
733 {"s1e1w", A64AT_S1E1W},
734 {"s1e2w", A64AT_S1E2W},
735 {"s1e3w", A64AT_S1E3W},
736 {"s1e0r", A64AT_S1E0R},
737 {"s1e0w", A64AT_S1E0W},
738 {"s12e1r", A64AT_S12E1R},
739 {"s12e1w", A64AT_S12E1W},
740 {"s12e0r", A64AT_S12E0R},
741 {"s12e0w", A64AT_S12E0W}
742 };
743
744 const A64NamedImmMapper A64AT_ATMapper = {
745 ATPairs,
746 ARR_SIZE(ATPairs),
747 0,
748 };
749
750 static const A64NamedImmMapper_Mapping DBarrierPairs[] = {
751 {"oshld", A64DB_OSHLD},
752 {"oshst", A64DB_OSHST},
753 {"osh", A64DB_OSH},
754 {"nshld", A64DB_NSHLD},
755 {"nshst", A64DB_NSHST},
756 {"nsh", A64DB_NSH},
757 {"ishld", A64DB_ISHLD},
758 {"ishst", A64DB_ISHST},
759 {"ish", A64DB_ISH},
760 {"ld", A64DB_LD},
761 {"st", A64DB_ST},
762 {"sy", A64DB_SY}
763 };
764
765 const A64NamedImmMapper A64DB_DBarrierMapper = {
766 DBarrierPairs,
767 ARR_SIZE(DBarrierPairs),
768 16,
769 };
770
771 static const A64NamedImmMapper_Mapping DCPairs[] = {
772 {"zva", A64DC_ZVA},
773 {"ivac", A64DC_IVAC},
774 {"isw", A64DC_ISW},
775 {"cvac", A64DC_CVAC},
776 {"csw", A64DC_CSW},
777 {"cvau", A64DC_CVAU},
778 {"civac", A64DC_CIVAC},
779 {"cisw", A64DC_CISW}
780 };
781
782 const A64NamedImmMapper A64DC_DCMapper = {
783 DCPairs,
784 ARR_SIZE(DCPairs),
785 0,
786 };
787
788 static const A64NamedImmMapper_Mapping ICPairs[] = {
789 {"ialluis", A64IC_IALLUIS},
790 {"iallu", A64IC_IALLU},
791 {"ivau", A64IC_IVAU}
792 };
793
794 const A64NamedImmMapper A64IC_ICMapper = {
795 ICPairs,
796 ARR_SIZE(ICPairs),
797 0,
798 };
799
800 static const A64NamedImmMapper_Mapping ISBPairs[] = {
801 {"sy", A64DB_SY},
802 };
803
804 const A64NamedImmMapper A64ISB_ISBMapper = {
805 ISBPairs,
806 ARR_SIZE(ISBPairs),
807 16,
808 };
809
810 static const A64NamedImmMapper_Mapping PRFMPairs[] = {
811 {"pldl1keep", A64PRFM_PLDL1KEEP},
812 {"pldl1strm", A64PRFM_PLDL1STRM},
813 {"pldl2keep", A64PRFM_PLDL2KEEP},
814 {"pldl2strm", A64PRFM_PLDL2STRM},
815 {"pldl3keep", A64PRFM_PLDL3KEEP},
816 {"pldl3strm", A64PRFM_PLDL3STRM},
817 {"plil1keep", A64PRFM_PLIL1KEEP},
818 {"plil1strm", A64PRFM_PLIL1STRM},
819 {"plil2keep", A64PRFM_PLIL2KEEP},
820 {"plil2strm", A64PRFM_PLIL2STRM},
821 {"plil3keep", A64PRFM_PLIL3KEEP},
822 {"plil3strm", A64PRFM_PLIL3STRM},
823 {"pstl1keep", A64PRFM_PSTL1KEEP},
824 {"pstl1strm", A64PRFM_PSTL1STRM},
825 {"pstl2keep", A64PRFM_PSTL2KEEP},
826 {"pstl2strm", A64PRFM_PSTL2STRM},
827 {"pstl3keep", A64PRFM_PSTL3KEEP},
828 {"pstl3strm", A64PRFM_PSTL3STRM}
829 };
830
831 const A64NamedImmMapper A64PRFM_PRFMMapper = {
832 PRFMPairs,
833 ARR_SIZE(PRFMPairs),
834 32,
835 };
836
837 static const A64NamedImmMapper_Mapping PStatePairs[] = {
838 {"spsel", A64PState_SPSel},
839 {"daifset", A64PState_DAIFSet},
840 {"daifclr", A64PState_DAIFClr},
841 {"pan", A64PState_PAN},
842 {"uao", A64PState_UAO}
843 };
844
845 const A64NamedImmMapper A64PState_PStateMapper = {
846 PStatePairs,
847 ARR_SIZE(PStatePairs),
848 0,
849 };
850
851 static const A64NamedImmMapper_Mapping MRSPairs[] = {
852 {"mdccsr_el0", A64SysReg_MDCCSR_EL0},
853 {"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
854 {"mdrar_el1", A64SysReg_MDRAR_EL1},
855 {"oslsr_el1", A64SysReg_OSLSR_EL1},
856 {"dbgauthstatus_el1", A64SysReg_DBGAUTHSTATUS_EL1},
857 {"pmceid0_el0", A64SysReg_PMCEID0_EL0},
858 {"pmceid1_el0", A64SysReg_PMCEID1_EL0},
859 {"midr_el1", A64SysReg_MIDR_EL1},
860 {"ccsidr_el1", A64SysReg_CCSIDR_EL1},
861 {"clidr_el1", A64SysReg_CLIDR_EL1},
862 {"ctr_el0", A64SysReg_CTR_EL0},
863 {"mpidr_el1", A64SysReg_MPIDR_EL1},
864 {"revidr_el1", A64SysReg_REVIDR_EL1},
865 {"aidr_el1", A64SysReg_AIDR_EL1},
866 {"dczid_el0", A64SysReg_DCZID_EL0},
867 {"id_pfr0_el1", A64SysReg_ID_PFR0_EL1},
868 {"id_pfr1_el1", A64SysReg_ID_PFR1_EL1},
869 {"id_dfr0_el1", A64SysReg_ID_DFR0_EL1},
870 {"id_afr0_el1", A64SysReg_ID_AFR0_EL1},
871 {"id_mmfr0_el1", A64SysReg_ID_MMFR0_EL1},
872 {"id_mmfr1_el1", A64SysReg_ID_MMFR1_EL1},
873 {"id_mmfr2_el1", A64SysReg_ID_MMFR2_EL1},
874 {"id_mmfr3_el1", A64SysReg_ID_MMFR3_EL1},
875 {"id_mmfr4_el1", A64SysReg_ID_MMFR4_EL1},
876 {"id_isar0_el1", A64SysReg_ID_ISAR0_EL1},
877 {"id_isar1_el1", A64SysReg_ID_ISAR1_EL1},
878 {"id_isar2_el1", A64SysReg_ID_ISAR2_EL1},
879 {"id_isar3_el1", A64SysReg_ID_ISAR3_EL1},
880 {"id_isar4_el1", A64SysReg_ID_ISAR4_EL1},
881 {"id_isar5_el1", A64SysReg_ID_ISAR5_EL1},
882 {"id_aa64pfr0_el1", A64SysReg_ID_A64PFR0_EL1},
883 {"id_aa64pfr1_el1", A64SysReg_ID_A64PFR1_EL1},
884 {"id_aa64dfr0_el1", A64SysReg_ID_A64DFR0_EL1},
885 {"id_aa64dfr1_el1", A64SysReg_ID_A64DFR1_EL1},
886 {"id_aa64afr0_el1", A64SysReg_ID_A64AFR0_EL1},
887 {"id_aa64afr1_el1", A64SysReg_ID_A64AFR1_EL1},
888 {"id_aa64isar0_el1", A64SysReg_ID_A64ISAR0_EL1},
889 {"id_aa64isar1_el1", A64SysReg_ID_A64ISAR1_EL1},
890 {"id_aa64mmfr0_el1", A64SysReg_ID_A64MMFR0_EL1},
891 {"id_aa64mmfr1_el1", A64SysReg_ID_A64MMFR1_EL1},
892 {"id_aa64mmfr2_el1", A64SysReg_ID_A64MMFR2_EL1},
893 {"lorid_el1", A64SysReg_LORID_EL1},
894 {"mvfr0_el1", A64SysReg_MVFR0_EL1},
895 {"mvfr1_el1", A64SysReg_MVFR1_EL1},
896 {"mvfr2_el1", A64SysReg_MVFR2_EL1},
897 {"rvbar_el1", A64SysReg_RVBAR_EL1},
898 {"rvbar_el2", A64SysReg_RVBAR_EL2},
899 {"rvbar_el3", A64SysReg_RVBAR_EL3},
900 {"isr_el1", A64SysReg_ISR_EL1},
901 {"cntpct_el0", A64SysReg_CNTPCT_EL0},
902 {"cntvct_el0", A64SysReg_CNTVCT_EL0},
903
904 // Trace registers
905 {"trcstatr", A64SysReg_TRCSTATR},
906 {"trcidr8", A64SysReg_TRCIDR8},
907 {"trcidr9", A64SysReg_TRCIDR9},
908 {"trcidr10", A64SysReg_TRCIDR10},
909 {"trcidr11", A64SysReg_TRCIDR11},
910 {"trcidr12", A64SysReg_TRCIDR12},
911 {"trcidr13", A64SysReg_TRCIDR13},
912 {"trcidr0", A64SysReg_TRCIDR0},
913 {"trcidr1", A64SysReg_TRCIDR1},
914 {"trcidr2", A64SysReg_TRCIDR2},
915 {"trcidr3", A64SysReg_TRCIDR3},
916 {"trcidr4", A64SysReg_TRCIDR4},
917 {"trcidr5", A64SysReg_TRCIDR5},
918 {"trcidr6", A64SysReg_TRCIDR6},
919 {"trcidr7", A64SysReg_TRCIDR7},
920 {"trcoslsr", A64SysReg_TRCOSLSR},
921 {"trcpdsr", A64SysReg_TRCPDSR},
922 {"trcdevaff0", A64SysReg_TRCDEVAFF0},
923 {"trcdevaff1", A64SysReg_TRCDEVAFF1},
924 {"trclsr", A64SysReg_TRCLSR},
925 {"trcauthstatus", A64SysReg_TRCAUTHSTATUS},
926 {"trcdevarch", A64SysReg_TRCDEVARCH},
927 {"trcdevid", A64SysReg_TRCDEVID},
928 {"trcdevtype", A64SysReg_TRCDEVTYPE},
929 {"trcpidr4", A64SysReg_TRCPIDR4},
930 {"trcpidr5", A64SysReg_TRCPIDR5},
931 {"trcpidr6", A64SysReg_TRCPIDR6},
932 {"trcpidr7", A64SysReg_TRCPIDR7},
933 {"trcpidr0", A64SysReg_TRCPIDR0},
934 {"trcpidr1", A64SysReg_TRCPIDR1},
935 {"trcpidr2", A64SysReg_TRCPIDR2},
936 {"trcpidr3", A64SysReg_TRCPIDR3},
937 {"trccidr0", A64SysReg_TRCCIDR0},
938 {"trccidr1", A64SysReg_TRCCIDR1},
939 {"trccidr2", A64SysReg_TRCCIDR2},
940 {"trccidr3", A64SysReg_TRCCIDR3},
941
942 // GICv3 registers
943 {"icc_iar1_el1", A64SysReg_ICC_IAR1_EL1},
944 {"icc_iar0_el1", A64SysReg_ICC_IAR0_EL1},
945 {"icc_hppir1_el1", A64SysReg_ICC_HPPIR1_EL1},
946 {"icc_hppir0_el1", A64SysReg_ICC_HPPIR0_EL1},
947 {"icc_rpr_el1", A64SysReg_ICC_RPR_EL1},
948 {"ich_vtr_el2", A64SysReg_ICH_VTR_EL2},
949 {"ich_eisr_el2", A64SysReg_ICH_EISR_EL2},
950 {"ich_elsr_el2", A64SysReg_ICH_ELSR_EL2},
951
952 // Statistical profiling registers
953 {"pmsidr_el1", A64SysReg_PMSIDR_EL1},
954 {"pmbidr_el1", A64SysReg_PMBIDR_EL1}
955 };
956
957 const A64SysRegMapper AArch64_MRSMapper = {
958 NULL,
959 MRSPairs,
960 ARR_SIZE(MRSPairs),
961 };
962
963 static const A64NamedImmMapper_Mapping MSRPairs[] = {
964 {"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
965 {"oslar_el1", A64SysReg_OSLAR_EL1},
966 {"pmswinc_el0", A64SysReg_PMSWINC_EL0},
967
968 // Trace registers
969 {"trcoslar", A64SysReg_TRCOSLAR},
970 {"trclar", A64SysReg_TRCLAR},
971
972 // GICv3 registers
973 {"icc_eoir1_el1", A64SysReg_ICC_EOIR1_EL1},
974 {"icc_eoir0_el1", A64SysReg_ICC_EOIR0_EL1},
975 {"icc_dir_el1", A64SysReg_ICC_DIR_EL1},
976 {"icc_sgi1r_el1", A64SysReg_ICC_SGI1R_EL1},
977 {"icc_asgi1r_el1", A64SysReg_ICC_ASGI1R_EL1},
978 {"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
979 };
980
981 const A64SysRegMapper AArch64_MSRMapper = {
982 NULL,
983 MSRPairs,
984 ARR_SIZE(MSRPairs),
985 };
986
987 #endif
988