1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares PPC TargetInfo objects. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 15 16 #include "OSTargets.h" 17 #include "clang/Basic/TargetInfo.h" 18 #include "clang/Basic/TargetOptions.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/ADT/StringSwitch.h" 21 #include "llvm/Support/Compiler.h" 22 23 namespace clang { 24 namespace targets { 25 26 // PPC abstract base class 27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { 28 29 /// Flags for architecture specific defines. 30 typedef enum { 31 ArchDefineNone = 0, 32 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 33 ArchDefinePpcgr = 1 << 1, 34 ArchDefinePpcsq = 1 << 2, 35 ArchDefine440 = 1 << 3, 36 ArchDefine603 = 1 << 4, 37 ArchDefine604 = 1 << 5, 38 ArchDefinePwr4 = 1 << 6, 39 ArchDefinePwr5 = 1 << 7, 40 ArchDefinePwr5x = 1 << 8, 41 ArchDefinePwr6 = 1 << 9, 42 ArchDefinePwr6x = 1 << 10, 43 ArchDefinePwr7 = 1 << 11, 44 ArchDefinePwr8 = 1 << 12, 45 ArchDefinePwr9 = 1 << 13, 46 ArchDefinePwr10 = 1 << 14, 47 ArchDefineFuture = 1 << 15, 48 ArchDefineA2 = 1 << 16, 49 ArchDefineE500 = 1 << 18 50 } ArchDefineTypes; 51 52 ArchDefineTypes ArchDefs = ArchDefineNone; 53 static const Builtin::Info BuiltinInfo[]; 54 static const char *const GCCRegNames[]; 55 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 56 std::string CPU; 57 enum PPCFloatABI { HardFloat, SoftFloat } FloatABI; 58 59 // Target cpu features. 60 bool HasAltivec = false; 61 bool HasMMA = false; 62 bool HasVSX = false; 63 bool HasP8Vector = false; 64 bool HasP8Crypto = false; 65 bool HasDirectMove = false; 66 bool HasHTM = false; 67 bool HasBPERMD = false; 68 bool HasExtDiv = false; 69 bool HasP9Vector = false; 70 bool HasSPE = false; 71 bool PairedVectorMemops = false; 72 bool HasP10Vector = false; 73 bool HasPCRelativeMemops = false; 74 75 protected: 76 std::string ABI; 77 78 public: PPCTargetInfo(const llvm::Triple & Triple,const TargetOptions &)79 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 80 : TargetInfo(Triple) { 81 SuitableAlign = 128; 82 SimdDefaultAlign = 128; 83 LongDoubleWidth = LongDoubleAlign = 128; 84 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 85 HasStrictFP = true; 86 } 87 88 // Set the language option for altivec based on our value. 89 void adjust(LangOptions &Opts) override; 90 91 // Note: GCC recognizes the following additional cpus: 92 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 93 // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64. 94 bool isValidCPUName(StringRef Name) const override; 95 void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; 96 setCPU(const std::string & Name)97 bool setCPU(const std::string &Name) override { 98 bool CPUKnown = isValidCPUName(Name); 99 if (CPUKnown) { 100 CPU = Name; 101 102 // CPU identification. 103 ArchDefs = 104 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 105 .Case("440", ArchDefineName) 106 .Case("450", ArchDefineName | ArchDefine440) 107 .Case("601", ArchDefineName) 108 .Case("602", ArchDefineName | ArchDefinePpcgr) 109 .Case("603", ArchDefineName | ArchDefinePpcgr) 110 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 111 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 112 .Case("604", ArchDefineName | ArchDefinePpcgr) 113 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 114 .Case("620", ArchDefineName | ArchDefinePpcgr) 115 .Case("630", ArchDefineName | ArchDefinePpcgr) 116 .Case("7400", ArchDefineName | ArchDefinePpcgr) 117 .Case("7450", ArchDefineName | ArchDefinePpcgr) 118 .Case("750", ArchDefineName | ArchDefinePpcgr) 119 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 120 ArchDefinePpcsq) 121 .Case("a2", ArchDefineA2) 122 .Cases("power3", "pwr3", ArchDefinePpcgr) 123 .Cases("power4", "pwr4", 124 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 125 .Cases("power5", "pwr5", 126 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 127 ArchDefinePpcsq) 128 .Cases("power5x", "pwr5x", 129 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 130 ArchDefinePpcgr | ArchDefinePpcsq) 131 .Cases("power6", "pwr6", 132 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 133 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 134 .Cases("power6x", "pwr6x", 135 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 136 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 137 ArchDefinePpcsq) 138 .Cases("power7", "pwr7", 139 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 140 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 141 ArchDefinePpcsq) 142 // powerpc64le automatically defaults to at least power8. 143 .Cases("power8", "pwr8", "ppc64le", 144 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 145 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 146 ArchDefinePpcgr | ArchDefinePpcsq) 147 .Cases("power9", "pwr9", 148 ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 149 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 150 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 151 .Cases("power10", "pwr10", 152 ArchDefinePwr10 | ArchDefinePwr9 | ArchDefinePwr8 | 153 ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | 154 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 155 ArchDefinePpcsq) 156 .Case("future", 157 ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | 158 ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | 159 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 160 ArchDefinePpcgr | ArchDefinePpcsq) 161 .Cases("8548", "e500", ArchDefineE500) 162 .Default(ArchDefineNone); 163 } 164 return CPUKnown; 165 } 166 getABI()167 StringRef getABI() const override { return ABI; } 168 169 ArrayRef<Builtin::Info> getTargetBuiltins() const override; 170 isCLZForZeroUndef()171 bool isCLZForZeroUndef() const override { return false; } 172 173 void getTargetDefines(const LangOptions &Opts, 174 MacroBuilder &Builder) const override; 175 176 bool 177 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 178 StringRef CPU, 179 const std::vector<std::string> &FeaturesVec) const override; 180 181 void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; 182 void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; 183 184 bool handleTargetFeatures(std::vector<std::string> &Features, 185 DiagnosticsEngine &Diags) override; 186 187 bool hasFeature(StringRef Feature) const override; 188 189 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 190 bool Enabled) const override; 191 192 ArrayRef<const char *> getGCCRegNames() const override; 193 194 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 195 196 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; 197 validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info)198 bool validateAsmConstraint(const char *&Name, 199 TargetInfo::ConstraintInfo &Info) const override { 200 switch (*Name) { 201 default: 202 return false; 203 case 'O': // Zero 204 break; 205 case 'f': // Floating point register 206 // Don't use floating point registers on soft float ABI. 207 if (FloatABI == SoftFloat) 208 return false; 209 LLVM_FALLTHROUGH; 210 case 'b': // Base register 211 Info.setAllowsRegister(); 212 break; 213 // FIXME: The following are added to allow parsing. 214 // I just took a guess at what the actions should be. 215 // Also, is more specific checking needed? I.e. specific registers? 216 case 'd': // Floating point register (containing 64-bit value) 217 case 'v': // Altivec vector register 218 // Don't use floating point and altivec vector registers 219 // on soft float ABI 220 if (FloatABI == SoftFloat) 221 return false; 222 Info.setAllowsRegister(); 223 break; 224 case 'w': 225 switch (Name[1]) { 226 case 'd': // VSX vector register to hold vector double data 227 case 'f': // VSX vector register to hold vector float data 228 case 's': // VSX vector register to hold scalar double data 229 case 'w': // VSX vector register to hold scalar double data 230 case 'a': // Any VSX register 231 case 'c': // An individual CR bit 232 case 'i': // FP or VSX register to hold 64-bit integers data 233 break; 234 default: 235 return false; 236 } 237 Info.setAllowsRegister(); 238 Name++; // Skip over 'w'. 239 break; 240 case 'h': // `MQ', `CTR', or `LINK' register 241 case 'q': // `MQ' register 242 case 'c': // `CTR' register 243 case 'l': // `LINK' register 244 case 'x': // `CR' register (condition register) number 0 245 case 'y': // `CR' register (condition register) 246 case 'z': // `XER[CA]' carry bit (part of the XER register) 247 Info.setAllowsRegister(); 248 break; 249 case 'I': // Signed 16-bit constant 250 case 'J': // Unsigned 16-bit constant shifted left 16 bits 251 // (use `L' instead for SImode constants) 252 case 'K': // Unsigned 16-bit constant 253 case 'L': // Signed 16-bit constant shifted left 16 bits 254 case 'M': // Constant larger than 31 255 case 'N': // Exact power of 2 256 case 'P': // Constant whose negation is a signed 16-bit constant 257 case 'G': // Floating point constant that can be loaded into a 258 // register with one instruction per word 259 case 'H': // Integer/Floating point constant that can be loaded 260 // into a register using three instructions 261 break; 262 case 'm': // Memory operand. Note that on PowerPC targets, m can 263 // include addresses that update the base register. It 264 // is therefore only safe to use `m' in an asm statement 265 // if that asm statement accesses the operand exactly once. 266 // The asm statement must also use `%U<opno>' as a 267 // placeholder for the "update" flag in the corresponding 268 // load or store instruction. For example: 269 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 270 // is correct but: 271 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 272 // is not. Use es rather than m if you don't want the base 273 // register to be updated. 274 case 'e': 275 if (Name[1] != 's') 276 return false; 277 // es: A "stable" memory operand; that is, one which does not 278 // include any automodification of the base register. Unlike 279 // `m', this constraint can be used in asm statements that 280 // might access the operand several times, or that might not 281 // access it at all. 282 Info.setAllowsMemory(); 283 Name++; // Skip over 'e'. 284 break; 285 case 'Q': // Memory operand that is an offset from a register (it is 286 // usually better to use `m' or `es' in asm statements) 287 Info.setAllowsRegister(); 288 LLVM_FALLTHROUGH; 289 case 'Z': // Memory operand that is an indexed or indirect from a 290 // register (it is usually better to use `m' or `es' in 291 // asm statements) 292 Info.setAllowsMemory(); 293 break; 294 case 'R': // AIX TOC entry 295 case 'a': // Address operand that is an indexed or indirect from a 296 // register (`p' is preferable for asm statements) 297 case 'S': // Constant suitable as a 64-bit mask operand 298 case 'T': // Constant suitable as a 32-bit mask operand 299 case 'U': // System V Release 4 small data area reference 300 case 't': // AND masks that can be performed by two rldic{l, r} 301 // instructions 302 case 'W': // Vector constant that does not require memory 303 case 'j': // Vector constant that is all zeros. 304 break; 305 // End FIXME. 306 } 307 return true; 308 } 309 convertConstraint(const char * & Constraint)310 std::string convertConstraint(const char *&Constraint) const override { 311 std::string R; 312 switch (*Constraint) { 313 case 'e': 314 case 'w': 315 // Two-character constraint; add "^" hint for later parsing. 316 R = std::string("^") + std::string(Constraint, 2); 317 Constraint++; 318 break; 319 default: 320 return TargetInfo::convertConstraint(Constraint); 321 } 322 return R; 323 } 324 getClobbers()325 const char *getClobbers() const override { return ""; } getEHDataRegisterNumber(unsigned RegNo)326 int getEHDataRegisterNumber(unsigned RegNo) const override { 327 if (RegNo == 0) 328 return 3; 329 if (RegNo == 1) 330 return 4; 331 return -1; 332 } 333 hasSjLjLowering()334 bool hasSjLjLowering() const override { return true; } 335 getLongDoubleMangling()336 const char *getLongDoubleMangling() const override { 337 if (LongDoubleWidth == 64) 338 return "e"; 339 return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() 340 ? "g" 341 : "u9__ieee128"; 342 } getFloat128Mangling()343 const char *getFloat128Mangling() const override { return "u9__ieee128"; } 344 hasExtIntType()345 bool hasExtIntType() const override { return true; } 346 isSPRegName(StringRef RegName)347 bool isSPRegName(StringRef RegName) const override { 348 return RegName.equals("r1") || RegName.equals("x1"); 349 } 350 }; 351 352 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { 353 public: PPC32TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)354 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 355 : PPCTargetInfo(Triple, Opts) { 356 if (Triple.isOSAIX()) 357 resetDataLayout("E-m:a-p:32:32-i64:64-n32"); 358 else 359 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 360 361 switch (getTriple().getOS()) { 362 case llvm::Triple::Linux: 363 case llvm::Triple::FreeBSD: 364 case llvm::Triple::NetBSD: 365 SizeType = UnsignedInt; 366 PtrDiffType = SignedInt; 367 IntPtrType = SignedInt; 368 break; 369 case llvm::Triple::AIX: 370 SizeType = UnsignedLong; 371 PtrDiffType = SignedLong; 372 IntPtrType = SignedLong; 373 LongDoubleWidth = 64; 374 LongDoubleAlign = DoubleAlign = 32; 375 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 376 break; 377 default: 378 break; 379 } 380 381 if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() || 382 Triple.isMusl()) { 383 LongDoubleWidth = LongDoubleAlign = 64; 384 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 385 } 386 387 // PPC32 supports atomics up to 4 bytes. 388 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 389 } 390 getBuiltinVaListKind()391 BuiltinVaListKind getBuiltinVaListKind() const override { 392 // This is the ELF definition, and is overridden by the Darwin sub-target 393 return TargetInfo::PowerABIBuiltinVaList; 394 } 395 }; 396 397 // Note: ABI differences may eventually require us to have a separate 398 // TargetInfo for little endian. 399 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo { 400 public: PPC64TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)401 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : PPCTargetInfo(Triple, Opts) { 403 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 404 IntMaxType = SignedLong; 405 Int64Type = SignedLong; 406 std::string DataLayout = ""; 407 408 if (Triple.isOSAIX()) { 409 // TODO: Set appropriate ABI for AIX platform. 410 DataLayout = "E-m:a-i64:64-n32:64"; 411 LongDoubleWidth = 64; 412 LongDoubleAlign = DoubleAlign = 32; 413 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 414 } else if ((Triple.getArch() == llvm::Triple::ppc64le)) { 415 DataLayout = "e-m:e-i64:64-n32:64"; 416 ABI = "elfv2"; 417 } else { 418 DataLayout = "E-m:e-i64:64-n32:64"; 419 ABI = "elfv1"; 420 } 421 422 if (Triple.isOSFreeBSD() || Triple.isOSOpenBSD() || Triple.isMusl()) { 423 LongDoubleWidth = LongDoubleAlign = 64; 424 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 425 } 426 427 if (Triple.isOSAIX() || Triple.isOSLinux()) 428 DataLayout += "-v256:256:256-v512:512:512"; 429 resetDataLayout(DataLayout); 430 431 // PPC64 supports atomics up to 8 bytes. 432 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 433 } 434 getBuiltinVaListKind()435 BuiltinVaListKind getBuiltinVaListKind() const override { 436 return TargetInfo::CharPtrBuiltinVaList; 437 } 438 439 // PPC64 Linux-specific ABI options. setABI(const std::string & Name)440 bool setABI(const std::string &Name) override { 441 if (Name == "elfv1" || Name == "elfv2") { 442 ABI = Name; 443 return true; 444 } 445 return false; 446 } 447 checkCallingConvention(CallingConv CC)448 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 449 switch (CC) { 450 case CC_Swift: 451 return CCCR_OK; 452 default: 453 return CCCR_Warning; 454 } 455 } 456 }; 457 458 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo 459 : public DarwinTargetInfo<PPC32TargetInfo> { 460 public: DarwinPPC32TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)461 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 462 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 463 HasAlignMac68kSupport = true; 464 BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool? 465 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 466 LongLongAlign = 32; 467 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 468 } 469 getBuiltinVaListKind()470 BuiltinVaListKind getBuiltinVaListKind() const override { 471 return TargetInfo::CharPtrBuiltinVaList; 472 } 473 }; 474 475 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo 476 : public DarwinTargetInfo<PPC64TargetInfo> { 477 public: DarwinPPC64TargetInfo(const llvm::Triple & Triple,const TargetOptions & Opts)478 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 479 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 480 HasAlignMac68kSupport = true; 481 resetDataLayout("E-m:o-i64:64-n32:64"); 482 } 483 }; 484 485 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : 486 public AIXTargetInfo<PPC32TargetInfo> { 487 public: 488 using AIXTargetInfo::AIXTargetInfo; getBuiltinVaListKind()489 BuiltinVaListKind getBuiltinVaListKind() const override { 490 return TargetInfo::CharPtrBuiltinVaList; 491 } 492 }; 493 494 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo : 495 public AIXTargetInfo<PPC64TargetInfo> { 496 public: 497 using AIXTargetInfo::AIXTargetInfo; 498 }; 499 500 } // namespace targets 501 } // namespace clang 502 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H 503