1 /* 2 * Copyright (c) 2016-2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SR_DEF_H 8 #define SR_DEF_H 9 10 #ifndef __ASSEMBLER__ 11 #include <lib/mmio.h> 12 #endif 13 14 #include <common/interrupt_props.h> 15 #include <drivers/arm/gic_common.h> 16 17 #include <crmu_def.h> 18 19 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 20 #define BRCM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 21 22 #define MHB_BASE_ADDR 0x60000000 23 #define PLAT_BRCM_CCN_BASE 0x61000000 24 #define CORESIGHT_BASE_ADDR 0x62000000 25 #define SMMU_BASE 0x64000000 26 27 /* memory map entries*/ 28 /* Grouping block device for bigger MMU region */ 29 /* covers MHB, CNN, coresight, GIC, MMU, APB, CRMU */ 30 #define PERIPH0_BASE MHB_BASE_ADDR 31 #define PERIPH0_SIZE 0x06d00000 32 33 #define PERIPH1_BASE 0x66d80000 34 #define PERIPH1_SIZE 0x00f80000 35 36 #define HSLS_BASE_ADDR 0x68900000 37 #define HSLS_SIZE 0x04500000 38 39 #define GIC500_BASE 0x63c00000 40 #define GIC500_SIZE 0x400000 41 42 /******************************************************************************* 43 * CCN related constants 44 ******************************************************************************/ 45 #define OLY_MN_REGISTERS_NODE0_SECURE_ACCESS (PLAT_BRCM_CCN_BASE + 0x0) 46 47 #define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x880500) 48 49 /* Used for acceleration of coherent ordered writes */ 50 #define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WUO BIT(4) 51 /* Wait for completion of requests at RN-I */ 52 #define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_WFC BIT(3) 53 54 /* 55 * Forces all reads from the RN-I to be sent with the request order bit set 56 * and this ensures ordered allocation of read data buffers in the RN-I 57 */ 58 #define OLY_RNI3PDVM_REGISTERS_NODE8_AUX_CTL_RQO BIT(5) 59 60 #define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x8e0500) 61 62 /* Wait for completion of requests at RN-I */ 63 #define OLY_RNI3PDVM_REGISTERS_NODE14_AUX_CTL_WFC BIT(3) 64 65 #define OLY_HNI_REGISTERS_NODE0_POS_CONTROL (PLAT_BRCM_CCN_BASE + 0x80000) 66 #define POS_CONTROL_HNI_POS_EN BIT(0) 67 68 #define OLY_HNI_REGISTERS_NODE0_PCIERC_RNI_NODEID_LIST \ 69 (PLAT_BRCM_CCN_BASE + 0x80008) 70 /* PAXB and PAXC connected to 8th Node */ 71 #define SR_RNI_PCIE_CONNECTED BIT(8) 72 /* PAXB connected to 6th Node */ 73 #define SRP_RNI_PCIE_CONNECTED BIT(6) 74 75 #define OLY_HNI_REGISTERS_NODE0_SA_AUX_CTL (PLAT_BRCM_CCN_BASE + 0x80500) 76 #define SA_AUX_CTL_POS_EARLY_WR_COMP_EN BIT(5) 77 #define SA_AUX_CTL_SER_DEVNE_WR BIT(9) 78 79 /******************************************************************************* 80 * Coresight related constants 81 ******************************************************************************/ 82 #define CORESIGHT_BASE_ADDR 0x62000000 83 84 #define IHOST0_BASE 0x66000000 85 #define IHOST_ADDR_SPACE 0x2000 86 87 /******************************************************************************* 88 * SCR related constants 89 ******************************************************************************/ 90 #define SCR_BASE 0x6600a000 91 #define SCR_ARCACHE_OFFSET 4 92 #define SCR_ARCACHE_MASK (0x3 << SCR_ARCACHE_OFFSET) 93 #define SCR_AWCACHE_OFFSET 6 94 #define SCR_AWCACHE_MASK (0x3 << SCR_AWCACHE_OFFSET) 95 #define SCR_AXCACHE_CONFIG_MASK (SCR_ARCACHE_MASK | SCR_AWCACHE_MASK) 96 #define SCR_TBUX_AXCACHE_CONFIG ((0x1 << SCR_AWCACHE_OFFSET) | \ 97 (0x1 << SCR_ARCACHE_OFFSET)) 98 99 #define SCR_REGS_SCR_SOFT_RESET (SCR_BASE + 0x1c) 100 #define SCR_REGS_GIC_SOFT_RESET BIT(0) 101 102 #define SCR_GPV_BASE 0x66100000 103 #define SCR_NOC_SECURITY0 (SCR_GPV_BASE + 0x08) 104 #define SCR_NOC_DDR_REGISTER_ACCESS (SCR_GPV_BASE + 0x30) 105 106 /******************************************************************************* 107 * MEMC and DDR related constants 108 ******************************************************************************/ 109 #define DDR0_CONTROL_ROOT 0x66200000 110 #define EMEM_SS_CFG_0_ROOT 0x66202000 111 #define EMEM_SYS_IF_0_ROOT 0x66204000 112 #define DDR_PHY0_ROOT 0x66240000 113 114 #define DDR1_CONTROL_ROOT 0x66280000 115 #define EMEM_SS_CFG_1_ROOT 0x66282000 116 #define EMEM_SYS_IF_1_ROOT 0x66284000 117 #define DDR_PHY1_ROOT 0x662c0000 118 119 #define DDR2_CONTROL_ROOT 0x66300000 120 #define EMEM_SS_CFG_2_ROOT 0x66302000 121 #define EMEM_SYS_IF_2_ROOT 0x66304000 122 #define DDR_PHY2_ROOT 0x66340000 123 124 /******************************************************************************* 125 * TZC400 related constants 126 ******************************************************************************/ 127 #define TZC_400_BASE 0x66d84000 128 129 /******************************************************************************* 130 * FS4 related constants 131 ******************************************************************************/ 132 #define FS4_SRAM_IDM_IO_CONTROL_DIRECT 0x66d8a408 133 134 #define FS4_CRYPTO_IDM_IO_CONTROL_DIRECT 0x66d8e408 135 #define FS4_CRYPTO_IDM_RESET_CONTROL 0x66d8e800 136 #define FS4_CRYPTO_BASE 0x67000000 137 #define FS4_CRYPTO_DME_BASE (FS4_CRYPTO_BASE + 0x280000) 138 139 #define FS4_RAID_IDM_IO_CONTROL_DIRECT 0x66d8f408 140 #define FS4_RAID_IDM_IO_STATUS 0x66d8f500 141 #define FS4_RAID_IDM_RESET_CONTROL 0x66d8f800 142 #define FS4_RAID_BASE 0x67400000 143 #define FS4_RAID_DME_BASE (FS4_RAID_BASE + 0x280000) 144 145 #define FS4_CRYPTO_GPV_BASE 0x67300000 146 #define FS4_RAID_GPV_BASE 0x67700000 147 148 #define FS6_PKI_BASE 0x67400000 149 #define FS6_PKI_DME_BASE 0x66D90000 150 151 #define TZC400_FS_SRAM_ROOT 0x66d84000 152 #define GATE_KEEPER_OFFSET 0x8 153 #define REGION_ATTRIBUTES_0_OFFSET 0x110 154 #define REGION_ID_ACCESS_0_OFFSET 0x114 155 156 #define NIC400_FS_NOC_ROOT 0x66e00000 157 #define NIC400_FS_NOC_SECURITY2_OFFSET 0x10 158 #define NIC400_FS_NOC_SECURITY4_OFFSET 0x18 159 #define NIC400_FS_NOC_SECURITY7_OFFSET 0x24 160 161 /******************************************************************************* 162 * SATA PHY related constants 163 ******************************************************************************/ 164 #define SATA_BASE 0x67d00000 165 166 /******************************************************************************* 167 * USB related constants 168 ******************************************************************************/ 169 #define USB_BASE 0x68500000 170 #define USB_SIZE 0x00400000 171 #define XHC_BASE (USB_BASE + 0x11000) 172 #define MAX_USB_PORTS 3 173 174 /******************************************************************************* 175 * HSLS related constants 176 ******************************************************************************/ 177 #define IPROC_ROOT 0x68900000 178 #define HSLS_ICFG_REGS_BASE IPROC_ROOT 179 #define HSLS_IDM_REGS_BASE 0x68e00000 180 #define HSLS_MODE_SEL_CONTROL 0x68a40000 181 #define HSLS_TZPC_BASE 0x68b40000 182 #define HSLS_GPV_BASE 0x6cd00000 183 184 /******************************************************************************* 185 * Chip ID related constants 186 ******************************************************************************/ 187 #define ICFG_CHIP_ID HSLS_ICFG_REGS_BASE 188 #define CHIP_ID_SR 0xd730 189 #define CHIP_ID_NS3Z 0xe56d 190 #define CHIP_ID_MASK 0xf000 191 #define ICFG_CHIP_REVISION_ID (HSLS_ICFG_REGS_BASE + 0x4) 192 #define PLAT_CHIP_ID_GET (mmio_read_32(ICFG_CHIP_ID)) 193 #define PLAT_CHIP_REV_GET (mmio_read_32(ICFG_CHIP_REVISION_ID)) 194 195 /******************************************************************************* 196 * Timers related constants 197 ******************************************************************************/ 198 /* ChipcommonG_tim0_TIM_TIMER1Load 0x68930000 */ 199 #define SP804_TIMER0_BASE 0x68930000 200 #define SP804_TIMER1_BASE 0x68940000 201 #define SP804_TIMER0_TIMER_VAL_REG_OFFSET 0x4 202 #define SP804_TIMER0_CLKMULT 2 203 #define SP804_TIMER0_CLKDIV 25 204 205 /******************************************************************************* 206 * GPIO related constants 207 ******************************************************************************/ 208 #define IPROC_GPIO_NS_BASE 0x689d0000 209 #define IPROC_GPIO_S_BASE 0x68b00000 210 #define IPROC_GPIO_NR 151 211 #define GPIO_S_CNTRL_REG 0x68b60000 212 213 /******************************************************************************* 214 * I2C SMBUS related constants 215 ******************************************************************************/ 216 #define SMBUS0_REGS_BASE 0x689b0000 217 #define SMBUS1_REGS_BASE 0x689e0000 218 219 /******************************************************************************* 220 * UART related constants 221 ******************************************************************************/ 222 #define ChipcommonG_UART0_UART_RBR_THR_DLL 0x68a00000 223 #define ChipcommonG_UART1_UART_RBR_THR_DLL 0x68a10000 224 #define ChipcommonG_UART2_UART_RBR_THR_DLL 0x68a20000 225 #define ChipcommonG_UART3_UART_RBR_THR_DLL 0x68a30000 226 227 #define UART0_BASE_ADDR ChipcommonG_UART0_UART_RBR_THR_DLL 228 #define UART1_BASE_ADDR ChipcommonG_UART1_UART_RBR_THR_DLL 229 #define UART2_BASE_ADDR ChipcommonG_UART2_UART_RBR_THR_DLL 230 #define UART3_BASE_ADDR ChipcommonG_UART3_UART_RBR_THR_DLL 231 232 #define UART_SPR_OFFSET 0x1c /* Scratch Pad Register */ 233 234 #define LOG_LEVEL_REGISTER CRMU_SPARE_REG_3 235 #define GET_LOG_LEVEL() (mmio_read_32(LOG_LEVEL_REGISTER)) 236 #define SET_LOG_LEVEL(x) (mmio_write_32(LOG_LEVEL_REGISTER, x)) 237 238 #define IO_RETRY_REGISTER CRMU_SPARE_REG_4 239 240 #define DWC_UART_REFCLK (25 * 1000 * 1000) 241 #define DWC_UART_REFCLK_DIV 16 242 /* Baud rate in emulation will vary based on setting of 25MHz SCLK */ 243 #define DWC_UART_BAUDRATE 115200 244 245 #define BRCM_CRASH_CONSOLE_BASE UART1_BASE_ADDR 246 #define BRCM_CRASH_CONSOLE_REFCLK DWC_UART_REFCLK 247 #define BRCM_CRASH_CONSOLE_BAUDRATE DWC_UART_BAUDRATE 248 249 #ifdef BOARD_CONSOLE_UART 250 #define PLAT_BRCM_BOOT_UART_BASE BOARD_CONSOLE_UART 251 #else 252 #define PLAT_BRCM_BOOT_UART_BASE UART1_BASE_ADDR 253 #endif 254 #define CONSOLE_UART_ID ((PLAT_BRCM_BOOT_UART_BASE >> 16) & 0x3) 255 256 #define PLAT_BRCM_BOOT_UART_CLK_IN_HZ DWC_UART_REFCLK 257 #define BRCM_CONSOLE_BAUDRATE DWC_UART_BAUDRATE 258 259 #define PLAT_BRCM_BL31_RUN_UART_BASE PLAT_BRCM_BOOT_UART_BASE 260 #define PLAT_BRCM_BL31_RUN_UART_CLK_IN_HZ PLAT_BRCM_BOOT_UART_CLK_IN_HZ 261 262 /******************************************************************************* 263 * IOMUX related constants 264 ******************************************************************************/ 265 #define HSLS_IOPAD_BASE HSLS_MODE_SEL_CONTROL 266 #define MODE_SEL_CONTROL_FSEL_MASK 0x7 267 #define MODE_SEL_CONTROL_FSEL_MODE0 0x0 268 #define MODE_SEL_CONTROL_FSEL_MODE1 0x1 269 #define MODE_SEL_CONTROL_FSEL_MODE2 0x2 270 #define MODE_SEL_CONTROL_FSEL_MODE3 0x3 271 #define MODE_SEL_CONTROL_FSEL_DEBUG 0x4 272 #define IPROC_IOPAD_MODE_BASE (HSLS_MODE_SEL_CONTROL + 0x29c) 273 #define UART0_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4a8) 274 #define UART0_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x4ac) 275 #define UART1_SIN_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3b8) 276 #define UART1_SOUT_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3bc) 277 #define UARTx_SIN_MODE_SEL_CONTROL_FSEL 0 278 #define UARTx_SOUT_MODE_SEL_CONTROL_FSEL 0 279 280 /******************************************************************************* 281 * PKA constants 282 ******************************************************************************/ 283 #define ICFG_PKA_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xac0) 284 #define ICFG_PKA_MEM_PWR_CTRL__POWERONIN BIT(0) 285 #define ICFG_PKA_MEM_PWR_CTRL__POWEROKIN BIT(1) 286 #define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONIN BIT(2) 287 #define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3) 288 #define ICFG_PKA_MEM_PWR_CTRL__POWERONOUT BIT(4) 289 #define ICFG_PKA_MEM_PWR_CTRL__POWEROKOUT BIT(5) 290 #define ICFG_PKA_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6) 291 #define ICFG_PKA_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7) 292 #define ICFG_PKA_MEM_PWR_CTRL__ISO BIT(8) 293 294 /******************************************************************************* 295 * RNG constants 296 ******************************************************************************/ 297 #define RNG_BASE_ADDR 0x68b20000 298 299 /******************************************************************************* 300 * Trusted Watchdog constants 301 ******************************************************************************/ 302 #define ARM_SP805_TWDG_BASE 0x68b30000 303 #define ARM_SP805_TWDG_CLK_HZ ((25 * 1000 * 1000) / 2) 304 /* 305 * The TBBR document specifies a watchdog timeout of 256 seconds. SP805 306 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) 307 */ 308 #define ARM_TWDG_TIMEOUT_SEC 128 309 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 310 ARM_TWDG_TIMEOUT_SEC) 311 312 /******************************************************************************* 313 * SOTP related constants 314 ******************************************************************************/ 315 #define SOTP_REGS_OTP_BASE 0x68b50000 316 #define SOTP_CHIP_CTRL (SOTP_REGS_OTP_BASE + 0x4c) 317 #define SOTP_CLEAR_SYSCTRL_ALL_MASTER_NS 0 318 319 /******************************************************************************* 320 * DMAC/PL330 related constants 321 ******************************************************************************/ 322 #define DMAC_M0_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x408) 323 #define BOOT_MANAGER_NS BIT(25) 324 #define DMAC_M0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x800) 325 #define ICFG_DMAC_CONFIG_0 (HSLS_ICFG_REGS_BASE + 0x190) 326 #define ICFG_DMAC_CONFIG_1 (HSLS_ICFG_REGS_BASE + 0x194) 327 #define ICFG_DMAC_CONFIG_2 (HSLS_ICFG_REGS_BASE + 0x198) 328 #define BOOT_PERIPHERAL_NS 0xffffffff 329 #define ICFG_DMAC_CONFIG_3 (HSLS_ICFG_REGS_BASE + 0x19c) 330 #define BOOT_IRQ_NS 0x0000ffff 331 #define ICFG_DMAC_SID_ARADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf0) 332 #define ICFG_DMAC_SID_AWADDR_CONTROL (HSLS_ICFG_REGS_BASE + 0xaf4) 333 #define ICFG_DMAC_MEM_PWR_CTRL__POWERONIN BIT(0) 334 #define ICFG_DMAC_MEM_PWR_CTRL__POWEROKIN BIT(1) 335 #define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONIN BIT(2) 336 #define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKIN BIT(3) 337 #define ICFG_DMAC_MEM_PWR_CTRL__POWERONOUT BIT(4) 338 #define ICFG_DMAC_MEM_PWR_CTRL__POWEROKOUT BIT(5) 339 #define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWERONOUT BIT(6) 340 #define ICFG_DMAC_MEM_PWR_CTRL__ARRPOWEROKOUT BIT(7) 341 #define ICFG_DMAC_MEM_PWR_CTRL__ISO BIT(8) 342 #define ICFG_DMAC_MEM_PWR_CTRL (HSLS_ICFG_REGS_BASE + 0xadc) 343 344 /******************************************************************************* 345 * PNOR related constants 346 ******************************************************************************/ 347 #define PNOR_ICFG_BASE (HSLS_ICFG_REGS_BASE + 0x780) 348 #define PNOR_ICFG_CS_0 PNOR_ICFG_BASE 349 #define PNOR_ICFG_CS_1 (PNOR_ICFG_BASE + 0x4) 350 #define PNOR_ICFG_CS_2 (PNOR_ICFG_BASE + 0x8) 351 #define PNOR_ICFG_CS_x_MASK0_MASK 0xff 352 #define PNOR_ICFG_CS_x_MASK0_SHIFT 8 353 #define PNOR_ICFG_CS_x_MATCH0_MASK 0xff 354 #define PNOR_ICFG_CS_x_MATCH0_SHIFT 0 355 356 #define PNOR_IDM_BASE (HSLS_IDM_REGS_BASE + 0xb000) 357 #define PNOR_IDM_IO_CONTROL_DIRECT (PNOR_IDM_BASE + 0x408) 358 #define PNOR_IDM_IO_RESET_CONTROL (PNOR_IDM_BASE + 0x800) 359 360 #define PNOR_REG_BASE 0x68c50000 361 #define PNOR_REG_DIRECT_CMD (PNOR_REG_BASE + 0x010) 362 #define PNOR_REG_SET_CYCLES (PNOR_REG_BASE + 0x014) 363 #define PNOR_REG_SET_OPMODE (PNOR_REG_BASE + 0x018) 364 #define PNOR_REG_REFRESH_0 (PNOR_REG_BASE + 0x020) 365 #define PNOR_REG_PERIPH_ID0 (PNOR_REG_BASE + 0xfe0) 366 #define PNOR_REG_PERIPH_ID1 (PNOR_REG_BASE + 0xfe4) 367 #define PNOR_REG_PERIPH_ID2 (PNOR_REG_BASE + 0xfe8) 368 #define PNOR_REG_PERIPH_ID3 (PNOR_REG_BASE + 0xfec) 369 #define PNOR_REG_PERIPH_IDx_MASK 0xff 370 371 /******************************************************************************* 372 * NAND related constants 373 ******************************************************************************/ 374 #define NAND_FLASH_REVISION 0x68c60000 375 #define NAND_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0xa408) 376 #define NAND_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xa800) 377 378 /******************************************************************************* 379 * eMMC related constants 380 ******************************************************************************/ 381 #define PLAT_SD_MAX_READ_LENGTH 0x400 382 383 #define SDIO0_EMMCSDXC_SYSADDR 0x68cf1000 384 #define SDIO_IDM0_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x2408) 385 #define SDIO_IDM1_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x3408) 386 #define SDIO_IDM0_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0x2800) 387 #define ICFG_SDIO0_BASE (HSLS_ICFG_REGS_BASE + 0x6e4) 388 #define ICFG_SDIO1_BASE (HSLS_ICFG_REGS_BASE + 0x734) 389 #define ICFG_SDIO0_CAP0 (ICFG_SDIO0_BASE + 0x10) 390 #define ICFG_SDIO0_CAP1 (ICFG_SDIO0_BASE + 0x14) 391 #define ICFG_SDIO0_SID (HSLS_ICFG_REGS_BASE + 0xb00) 392 #define ICFG_SDIO1_SID (HSLS_ICFG_REGS_BASE + 0xb08) 393 394 /******************************************************************************* 395 * Bootstrap related constants 396 ******************************************************************************/ 397 #define ROM_S0_IDM_IO_STATUS (HSLS_IDM_REGS_BASE + 0x9500) 398 399 /******************************************************************************* 400 * ROM related constants 401 ******************************************************************************/ 402 #define ROM_BASE_ADDR 0x6ce00000 403 #define ROM_VERSION_STRING_ADDR (ROM_BASE_ADDR + 0x28000) 404 #define ROM_BUILD_MESSAGE_ADDR (ROM_BASE_ADDR + 0x28018) 405 406 /******************************************************************************* 407 * Boot source peripheral related constants 408 ******************************************************************************/ 409 #define QSPI_CTRL_BASE_ADDR 0x68c70000 410 #define QSPI_BASE_ADDR 0x70000000 411 #define QSPI_SIZE 0x08000000 412 #define NOR_BASE_ADDR 0x74000000 413 #define NOR_SIZE 0x04000000 414 #define NAND_BASE_ADDR 0x78000000 415 #define NAND_SIZE 0x08000000 416 417 #define QSPI_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xc800) 418 419 #define APBR_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xe800) 420 #define APBS_IDM_IDM_RESET_CONTROL (HSLS_IDM_REGS_BASE + 0xf800) 421 422 #define APBX_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x10408) 423 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 424 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2 425 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM0_SCLK_SEL 4 426 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM1_SCLK_SEL 6 427 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM2_SCLK_SEL 8 428 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM3_SCLK_SEL 10 429 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM4_SCLK_SEL 12 430 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM5_SCLK_SEL 13 431 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM6_SCLK_SEL 14 432 #define APBX_IDM_IDM_IO_CONTROL_DIRECT_TIM7_SCLK_SEL 15 433 434 #define APBY_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x11408) 435 #define APBY_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 436 #define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART0_SCLK_SEL 2 437 #define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART1_SCLK_SEL 4 438 #define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART2_SCLK_SEL 6 439 #define APBY_IDM_IDM_IO_CONTROL_DIRECT_UART3_SCLK_SEL 8 440 441 #define APBZ_IDM_IDM_IO_CONTROL_DIRECT (HSLS_IDM_REGS_BASE + 0x12408) 442 #define APBZ_IDM_IDM_IO_CONTROL_DIRECT_CLK_ENABLE 0 443 #define APBZ_IDM_IDM_IO_CONTROL_DIRECT_WDOG_SCLK_SEL 2 444 445 /******************************************************************************* 446 * Stingray memory map related constants 447 ******************************************************************************/ 448 449 /* The last 4KB of Trusted SRAM are used as shared memory */ 450 #define BRCM_SHARED_RAM_SIZE 0x0 451 #define BRCM_SHARED_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE + \ 452 PLAT_BRCM_TRUSTED_SRAM_SIZE - \ 453 BRCM_SHARED_RAM_SIZE) 454 455 /* Reserve 4 KB to store error logs in BL2 */ 456 #define BCM_ELOG_BL2_SIZE 0x00001000 457 #define BCM_ELOG_BL2_BASE BL1_RW_LIMIT 458 459 /* The remaining Trusted SRAM is used to load the BL images */ 460 #define BRCM_BL_RAM_BASE (PLAT_BRCM_TRUSTED_SRAM_BASE) 461 #define BRCM_BL_RAM_SIZE (PLAT_BRCM_TRUSTED_SRAM_SIZE - \ 462 BRCM_SHARED_RAM_SIZE) 463 464 /* DDR Address where TMON temperature values are written */ 465 #define TMON_SHARED_DDR_ADDRESS 0x8f100000 466 467 /* Reserve 4 kB to pass data to BL33 */ 468 #define BL33_SHARED_DDR_BASE 0x8f102000 469 #define BL33_SHARED_DDR_SIZE 0x1000 470 471 /* Default AP error logging base addr */ 472 #ifndef ELOG_AP_UART_LOG_BASE 473 #define ELOG_AP_UART_LOG_BASE 0x8f110000 474 #endif 475 476 /* Reserve 16 to store error logs in BL31 */ 477 #define BCM_ELOG_BL31_BASE ELOG_AP_UART_LOG_BASE 478 #define BCM_ELOG_BL31_SIZE 0x4000 479 480 /******************************************************************************* 481 * Non-secure DDR Map 482 ******************************************************************************/ 483 #define BRCM_DRAM1_BASE ULL(0x80000000) 484 #define BRCM_DRAM1_SIZE ULL(0x10000000) 485 #define BRCM_DRAM2_BASE ULL(0x880000000) 486 #define BRCM_DRAM2_SIZE ULL(0x780000000) 487 #define BRCM_DRAM3_BASE ULL(0x8800000000) 488 #define BRCM_DRAM3_SIZE ULL(0x7800000000) 489 #define BRCM_SHARED_DRAM_BASE BL33_SHARED_DDR_BASE 490 #define BRCM_SHARED_DRAM_SIZE BL33_SHARED_DDR_SIZE 491 #define BRCM_EXT_SRAM_BASE ULL(0x74000000) 492 #define BRCM_EXT_SRAM_SIZE ULL(0x4000000) 493 494 /* Priority levels for platforms */ 495 #define PLAT_RAS_PRI 0x10 496 #define PLAT_SDEI_CRITICAL_PRI 0x60 497 #define PLAT_SDEI_NORMAL_PRI 0x70 498 499 /* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 */ 500 #define BRCM_IRQ_SEC_SGI_0 14 501 #define BRCM_IRQ_SEC_SGI_1 15 502 503 /* RTC periodic interrupt */ 504 #define BRCM_IRQ_SEC_SPI_0 49 505 506 /* 507 * Macros for local power states in SR platforms encoded by State-ID field 508 * within the power-state parameter. 509 */ 510 511 /* Local power state for power domains in Run state. */ 512 #define PLAT_LOCAL_STATE_RUN 0 513 514 /* Local power state for retention. Valid only for CPU power domains */ 515 #define PLAT_LOCAL_STATE_RET 1 516 517 /* 518 * Local power state for OFF/power-down. Valid for CPU and cluster power 519 * domains. 520 */ 521 #define PLAT_LOCAL_STATE_OFF 2 522 523 /* 524 * This macro defines the deepest retention state possible. A higher state 525 * id will represent an invalid or a power down state. 526 */ 527 #define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET 528 529 /* 530 * This macro defines the deepest power down states possible. Any state ID 531 * higher than this is invalid. 532 */ 533 #define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF 534 535 /* ChiMP-related constants */ 536 537 #define NITRO_TZPC_TZPCDECPROT0clr 0x60c01808 538 #define NITRO_TZPC_TZPCDECPROT0clr__DECPROT0_chimp_m_clr_R 1 539 540 #define NIC400_NITRO_CHIMP_S_IDM_IO_CONTROL_DIRECT 0x60e00408 541 542 #define CHIMP_INDIRECT_ADDR_MASK 0x3fffff 543 #define CHIMP_INDIRECT_BASE 0x60800000 544 545 #define CHIMP_REG_ECO_RESERVED 0x3042400 546 547 #define CHIMP_FLASH_ACCESS_DONE_BIT 2 548 549 /* indicate FRU table programming is done successfully */ 550 #define CHIMP_FRU_PROG_DONE_BIT 9 551 552 #define CHIMP_REG_CTRL_BPE_MODE_REG 0x0 553 #define CHIMP_REG_CTRL_BPE_STAT_REG 0x4 554 #define CHIMP_REG_CTRL_FSTBOOT_PTR_REG 0x8 555 #define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_L 1 556 #define CHIMP_REG_CHIMP_REG_CTRL_BPE_MODE_REG__cm3_rst_R 1 557 #define CHIMP_REG_CTRL_BASE 0x3040000 558 #define CHIMP_FAST_BOOT_MODE_BIT 2 559 #define CHIMP_REG_CHIMP_APE_SCPAD 0x3300000 560 #define CHIMP_REG_CHIMP_SCPAD 0x3100000 561 562 /* Chimp health status offset in scratch pad ram */ 563 #define CHIMP_HEALTH_STATUS_OFFSET 0x8 564 /* 565 * If not in NIC mode then FASTBOOT can be enabled. 566 * "Not in NIC mode" means that FORCE_FASTBOOT is set 567 * and a valid (1 or 2) fastboot type is specified. 568 * 569 * Three types of fastboot are supported: 570 * 0 = No fastboot. Boots Nitro/ChiMP and lets ROM loader 571 * initialize ChiMP from NVRAM (QSPI). 572 * 573 * 1 = Jump in place (need a flat image) 574 * This is intended to speedup Nitro FW boot on Palladium, 575 * can be used with a real chip as well. 576 * 2 = Jump normally with decompression 577 * Modus operandi for a real chip. Works also on Palladium 578 * Note: image decompressing takes time on Palladium. 579 * 3 = No fastboot support. No ChiMP bringup 580 * (use only for AP debug or for ChiMP's deferred setup). 581 */ 582 #define CHIMP_FASTBOOT_JUMP_DECOMPRESS 2 583 #define CHIMP_FASTBOOT_JUMP_IN_PLACE 1 584 #define CHIMP_FASTBOOT_NITRO_RESET 0 585 /* 586 * Definitions for a non-Nitro access 587 * to QSPI PAD after the handshake 588 */ 589 #define QSPI_HOLD_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3e8) 590 #define QSPI_WP_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3ec) 591 #define QSPI_SCK_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f0) 592 #define QSPI_CS_N_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f4) 593 #define QSPI_MOSI_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3f8) 594 #define QSPI_MISO_MODE_SEL_CONTROL (HSLS_MODE_SEL_CONTROL + 0x3fc) 595 596 /******************************************************************************* 597 * Stream IDs for different blocks of SR 598 * block_id for different blocks is as follows: 599 * PCIE : 0x0 600 * PAXC : 0x1 601 * FS4 : 0x2 602 * Rest of the masters(includes MHB via RNI): 0x3 603 ******************************************************************************/ 604 #define SR_SID_VAL(block_id, subblock_id, device_num) ((block_id << 13) | \ 605 (subblock_id << 11) | \ 606 (device_num)) 607 608 #define CRMU_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x7) 609 #define CRMU_SID_SHIFT 5 610 611 #define DMAC_STREAM_ID SR_SID_VAL(0x3, 0x0, 0x0) 612 #define DMAC_SID_SHIFT 5 613 614 /* DDR SHMOO Values defines */ 615 #define IDRAM_SHMOO_VALUES_ADDR CRMU_IDRAM_BASE_ADDR 616 #define DDR_SHMOO_VALUES_ADDR 0x8f103000 617 #define SHMOO_SIZE_PER_CHANNEL 0x1000 618 619 #endif /* SR_DEF_H */ 620