1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef IRIS_DEFINES_H 24 #define IRIS_DEFINES_H 25 26 /** 27 * @file iris_defines.h 28 * 29 * Random hardware #defines that we're not using GENXML for. 30 */ 31 32 #define MI_PREDICATE (0xC << 23) 33 # define MI_PREDICATE_LOADOP_KEEP (0 << 6) 34 # define MI_PREDICATE_LOADOP_LOAD (2 << 6) 35 # define MI_PREDICATE_LOADOP_LOADINV (3 << 6) 36 # define MI_PREDICATE_COMBINEOP_SET (0 << 3) 37 # define MI_PREDICATE_COMBINEOP_AND (1 << 3) 38 # define MI_PREDICATE_COMBINEOP_OR (2 << 3) 39 # define MI_PREDICATE_COMBINEOP_XOR (3 << 3) 40 # define MI_PREDICATE_COMPAREOP_TRUE (0 << 0) 41 # define MI_PREDICATE_COMPAREOP_FALSE (1 << 0) 42 # define MI_PREDICATE_COMPAREOP_SRCS_EQUAL (2 << 0) 43 # define MI_PREDICATE_COMPAREOP_DELTAS_EQUAL (3 << 0) 44 45 /* Predicate registers */ 46 #define MI_PREDICATE_SRC0 0x2400 47 #define MI_PREDICATE_SRC1 0x2408 48 #define MI_PREDICATE_DATA 0x2410 49 #define MI_PREDICATE_RESULT 0x2418 50 #define MI_PREDICATE_RESULT_1 0x241C 51 #define MI_PREDICATE_RESULT_2 0x2214 52 53 #define CS_GPR(n) (0x2600 + (n) * 8) 54 55 /* The number of bits in our TIMESTAMP queries. */ 56 #define TIMESTAMP_BITS 36 57 58 /* For gen12 we set the streamout buffers using 4 separate commands 59 * (3DSTATE_SO_BUFFER_INDEX_*) instead of 3DSTATE_SO_BUFFER. However the layout 60 * of the 3DSTATE_SO_BUFFER_INDEX_* commands is identical to that of 61 * 3DSTATE_SO_BUFFER apart from the SOBufferIndex field, so for now we use the 62 * 3DSTATE_SO_BUFFER command, but change the 3DCommandSubOpcode. 63 * SO_BUFFER_INDEX_0_CMD is actually the 3DCommandSubOpcode for 64 * 3DSTATE_SO_BUFFER_INDEX_0. 65 */ 66 #define SO_BUFFER_INDEX_0_CMD 0x60 67 68 #endif 69