1 /*
2 * \file trc_i_decode.cpp
3 * \brief OpenCSD :
4 *
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include "opencsd/ocsd_if_types.h"
36 #include "i_dec/trc_i_decode.h"
37 #include "i_dec/trc_idec_arminst.h"
38
DecodeInstruction(ocsd_instr_info * instr_info)39 ocsd_err_t TrcIDecode::DecodeInstruction(ocsd_instr_info *instr_info)
40 {
41 ocsd_err_t err = OCSD_OK;
42 struct decode_info info;
43
44 info.instr_sub_type = OCSD_S_INSTR_NONE;
45 info.arch_version = instr_info->pe_type.arch;
46
47 switch(instr_info->isa)
48 {
49 case ocsd_isa_arm:
50 err = DecodeA32(instr_info, &info);
51 break;
52
53 case ocsd_isa_thumb2:
54 err = DecodeT32(instr_info, &info);
55 break;
56
57 case ocsd_isa_aarch64:
58 err = DecodeA64(instr_info, &info);
59 break;
60
61 case ocsd_isa_tee:
62 case ocsd_isa_jazelle:
63 default:
64 // unsupported ISA
65 err = OCSD_ERR_UNSUPPORTED_ISA;
66 break;
67 }
68 instr_info->sub_type = info.instr_sub_type;
69 return err;
70 }
71
DecodeA32(ocsd_instr_info * instr_info,struct decode_info * info)72 ocsd_err_t TrcIDecode::DecodeA32(ocsd_instr_info *instr_info, struct decode_info *info)
73 {
74 uint32_t branchAddr = 0;
75 arm_barrier_t barrier;
76
77 instr_info->instr_size = 4; // instruction size A32
78 instr_info->type = OCSD_INSTR_OTHER; // default type
79 instr_info->next_isa = instr_info->isa; // assume same ISA
80 instr_info->is_link = 0;
81
82 if(inst_ARM_is_indirect_branch(instr_info->opcode, info))
83 {
84 instr_info->type = OCSD_INSTR_BR_INDIRECT;
85 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info);
86 }
87 else if(inst_ARM_is_direct_branch(instr_info->opcode))
88 {
89 inst_ARM_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr);
90 instr_info->type = OCSD_INSTR_BR;
91 if (branchAddr & 0x1)
92 {
93 instr_info->next_isa = ocsd_isa_thumb2;
94 branchAddr &= ~0x1;
95 }
96 instr_info->branch_addr = (ocsd_vaddr_t)branchAddr;
97 instr_info->is_link = inst_ARM_is_branch_and_link(instr_info->opcode, info);
98 }
99 else if((barrier = inst_ARM_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
100 {
101 switch(barrier)
102 {
103 case ARM_BARRIER_ISB:
104 instr_info->type = OCSD_INSTR_ISB;
105 break;
106
107 case ARM_BARRIER_DSB:
108 case ARM_BARRIER_DMB:
109 if(instr_info->dsb_dmb_waypoints)
110 instr_info->type = OCSD_INSTR_DSB_DMB;
111 break;
112 }
113 }
114 else if (instr_info->wfi_wfe_branch)
115 {
116 if (inst_ARM_wfiwfe(instr_info->opcode))
117 {
118 instr_info->type = OCSD_INSTR_WFI_WFE;
119 }
120 }
121 instr_info->is_conditional = inst_ARM_is_conditional(instr_info->opcode);
122
123 return OCSD_OK;
124 }
125
DecodeA64(ocsd_instr_info * instr_info,struct decode_info * info)126 ocsd_err_t TrcIDecode::DecodeA64(ocsd_instr_info *instr_info, struct decode_info *info)
127 {
128 uint64_t branchAddr = 0;
129 arm_barrier_t barrier;
130
131 instr_info->instr_size = 4; // default address update
132 instr_info->type = OCSD_INSTR_OTHER; // default type
133 instr_info->next_isa = instr_info->isa; // assume same ISA
134 instr_info->is_link = 0;
135
136 if(inst_A64_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link, info))
137 {
138 instr_info->type = OCSD_INSTR_BR_INDIRECT;
139 }
140 else if(inst_A64_is_direct_branch_link(instr_info->opcode, &instr_info->is_link, info))
141 {
142 inst_A64_branch_destination(instr_info->instr_addr,instr_info->opcode,&branchAddr);
143 instr_info->type = OCSD_INSTR_BR;
144 instr_info->branch_addr = (ocsd_vaddr_t)branchAddr;
145 }
146 else if((barrier = inst_A64_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
147 {
148 switch(barrier)
149 {
150 case ARM_BARRIER_ISB:
151 instr_info->type = OCSD_INSTR_ISB;
152 break;
153
154 case ARM_BARRIER_DSB:
155 case ARM_BARRIER_DMB:
156 if(instr_info->dsb_dmb_waypoints)
157 instr_info->type = OCSD_INSTR_DSB_DMB;
158 break;
159 }
160 }
161 else if (instr_info->wfi_wfe_branch &&
162 inst_A64_wfiwfe(instr_info->opcode, info))
163 {
164 instr_info->type = OCSD_INSTR_WFI_WFE;
165 }
166 else if (OCSD_IS_ARCH_MINVER(info->arch_version, ARCH_AA64))
167 {
168 if (inst_A64_Tstart(instr_info->opcode))
169 instr_info->type = OCSD_INSTR_TSTART;
170 }
171
172 instr_info->is_conditional = inst_A64_is_conditional(instr_info->opcode);
173
174 return OCSD_OK;
175 }
176
DecodeT32(ocsd_instr_info * instr_info,struct decode_info * info)177 ocsd_err_t TrcIDecode::DecodeT32(ocsd_instr_info *instr_info, struct decode_info *info)
178 {
179 uint32_t branchAddr = 0;
180 arm_barrier_t barrier;
181
182 // need to align the 32 bit opcode as 2 16 bit, with LS 16 as in top 16 bit of
183 // 32 bit word - T2 routines assume 16 bit in top 16 bit of 32 bit opcode.
184 uint32_t op_temp = (instr_info->opcode >> 16) & 0xFFFF;
185 op_temp |= ((instr_info->opcode & 0xFFFF) << 16);
186 instr_info->opcode = op_temp;
187
188
189 instr_info->instr_size = is_wide_thumb((uint16_t)(instr_info->opcode >> 16)) ? 4 : 2;
190 instr_info->type = OCSD_INSTR_OTHER; // default type
191 instr_info->next_isa = instr_info->isa; // assume same ISA
192 instr_info->is_link = 0;
193 instr_info->is_conditional = 0;
194
195
196 if(inst_Thumb_is_direct_branch_link(instr_info->opcode,&instr_info->is_link, &instr_info->is_conditional, info))
197 {
198 inst_Thumb_branch_destination((uint32_t)instr_info->instr_addr,instr_info->opcode,&branchAddr);
199 instr_info->type = OCSD_INSTR_BR;
200 instr_info->branch_addr = (ocsd_vaddr_t)(branchAddr & ~0x1);
201 if((branchAddr & 0x1) == 0)
202 instr_info->next_isa = ocsd_isa_arm;
203 }
204 else if (inst_Thumb_is_indirect_branch_link(instr_info->opcode, &instr_info->is_link, info))
205 {
206 instr_info->type = OCSD_INSTR_BR_INDIRECT;
207 }
208 else if((barrier = inst_Thumb_barrier(instr_info->opcode)) != ARM_BARRIER_NONE)
209 {
210 switch(barrier)
211 {
212 case ARM_BARRIER_ISB:
213 instr_info->type = OCSD_INSTR_ISB;
214 break;
215
216 case ARM_BARRIER_DSB:
217 case ARM_BARRIER_DMB:
218 if(instr_info->dsb_dmb_waypoints)
219 instr_info->type = OCSD_INSTR_DSB_DMB;
220 break;
221 }
222 }
223 else if (instr_info->wfi_wfe_branch)
224 {
225 if (inst_Thumb_wfiwfe(instr_info->opcode))
226 {
227 instr_info->type = OCSD_INSTR_WFI_WFE;
228 }
229 }
230 instr_info->is_conditional = inst_Thumb_is_conditional(instr_info->opcode);
231 instr_info->thumb_it_conditions = inst_Thumb_is_IT(instr_info->opcode);
232
233 return OCSD_OK;
234 }
235
236 /* End of File trc_i_decode.cpp */
237