1 /*
2  * Copyright © 2017-2019 Advanced Micro Devices, Inc.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * The above copyright notice and this permission notice (including the
23  * next paragraph) shall be included in all copies or substantial portions
24  * of the Software.
25  */
26 
27 #ifndef _AMDGPU_ASIC_ADDR_H
28 #define _AMDGPU_ASIC_ADDR_H
29 
30 #define ATI_VENDOR_ID         0x1002
31 #define AMD_VENDOR_ID         0x1022
32 
33 // AMDGPU_VENDOR_IS_AMD(vendorId)
34 #define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
35 
36 #define FAMILY_UNKNOWN 0x00
37 #define FAMILY_TN      0x69
38 #define FAMILY_SI      0x6E
39 #define FAMILY_CI      0x78
40 #define FAMILY_KV      0x7D
41 #define FAMILY_VI      0x82
42 #define FAMILY_POLARIS 0x82
43 #define FAMILY_CZ      0x87
44 #define FAMILY_AI      0x8D
45 #define FAMILY_RV      0x8E
46 #define FAMILY_NV      0x8F
47 #define FAMILY_VGH     0x90
48 
49 // AMDGPU_FAMILY_IS(familyId, familyName)
50 #define FAMILY_IS(f, fn)     (f == FAMILY_##fn)
51 #define FAMILY_IS_TN(f)      FAMILY_IS(f, TN)
52 #define FAMILY_IS_SI(f)      FAMILY_IS(f, SI)
53 #define FAMILY_IS_CI(f)      FAMILY_IS(f, CI)
54 #define FAMILY_IS_KV(f)      FAMILY_IS(f, KV)
55 #define FAMILY_IS_VI(f)      FAMILY_IS(f, VI)
56 #define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS)
57 #define FAMILY_IS_CZ(f)      FAMILY_IS(f, CZ)
58 #define FAMILY_IS_AI(f)      FAMILY_IS(f, AI)
59 #define FAMILY_IS_RV(f)      FAMILY_IS(f, RV)
60 #define FAMILY_IS_NV(f)      FAMILY_IS(f, NV)
61 
62 #define AMDGPU_UNKNOWN          0xFF
63 
64 #define AMDGPU_TAHITI_RANGE     0x05, 0x14
65 #define AMDGPU_PITCAIRN_RANGE   0x15, 0x28
66 #define AMDGPU_CAPEVERDE_RANGE  0x29, 0x3C
67 #define AMDGPU_OLAND_RANGE      0x3C, 0x46
68 #define AMDGPU_HAINAN_RANGE     0x46, 0xFF
69 
70 #define AMDGPU_BONAIRE_RANGE    0x14, 0x28
71 #define AMDGPU_HAWAII_RANGE     0x28, 0x3C
72 
73 #define AMDGPU_SPECTRE_RANGE    0x01, 0x41
74 #define AMDGPU_SPOOKY_RANGE     0x41, 0x81
75 #define AMDGPU_KALINDI_RANGE    0x81, 0xA1
76 #define AMDGPU_GODAVARI_RANGE   0xA1, 0xFF
77 
78 #define AMDGPU_ICELAND_RANGE    0x01, 0x14
79 #define AMDGPU_TONGA_RANGE      0x14, 0x28
80 #define AMDGPU_FIJI_RANGE       0x3C, 0x50
81 #define AMDGPU_POLARIS10_RANGE  0x50, 0x5A
82 #define AMDGPU_POLARIS11_RANGE  0x5A, 0x64
83 #define AMDGPU_POLARIS12_RANGE  0x64, 0x6E
84 #define AMDGPU_VEGAM_RANGE      0x6E, 0xFF
85 
86 #define AMDGPU_CARRIZO_RANGE    0x01, 0x21
87 #define AMDGPU_STONEY_RANGE     0x61, 0xFF
88 
89 #define AMDGPU_VEGA10_RANGE     0x01, 0x14
90 #define AMDGPU_VEGA12_RANGE     0x14, 0x28
91 #define AMDGPU_VEGA20_RANGE     0x28, 0x32
92 #define AMDGPU_ARCTURUS_RANGE   0x32, 0xFF
93 
94 #define AMDGPU_RAVEN_RANGE      0x01, 0x81
95 #define AMDGPU_RAVEN2_RANGE     0x81, 0x91
96 #define AMDGPU_RENOIR_RANGE     0x91, 0xFF
97 
98 #define AMDGPU_NAVI10_RANGE     0x01, 0x0A
99 #define AMDGPU_NAVI12_RANGE     0x0A, 0x14
100 #define AMDGPU_NAVI14_RANGE     0x14, 0x28
101 #define AMDGPU_SIENNA_CICHLID_RANGE     0x28, 0x32
102 #define AMDGPU_NAVY_FLOUNDER_RANGE      0x32, 0x3C
103 #define AMDGPU_DIMGREY_CAVEFISH_RANGE   0x3C, 0x46
104 
105 #define AMDGPU_VANGOGH_RANGE    0x01, 0xFF
106 
107 #define AMDGPU_EXPAND_FIX(x) x
108 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
109 #define AMDGPU_IN_RANGE(val, ...)   AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
110 
111 
112 // ASICREV_IS(eRevisionId, revisionName)
113 #define ASICREV_IS(r, rn)              AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
114 #define ASICREV_IS_TAHITI_P(r)         ASICREV_IS(r, TAHITI)
115 #define ASICREV_IS_PITCAIRN_PM(r)      ASICREV_IS(r, PITCAIRN)
116 #define ASICREV_IS_CAPEVERDE_M(r)      ASICREV_IS(r, CAPEVERDE)
117 #define ASICREV_IS_OLAND_M(r)          ASICREV_IS(r, OLAND)
118 #define ASICREV_IS_HAINAN_V(r)         ASICREV_IS(r, HAINAN)
119 
120 #define ASICREV_IS_BONAIRE_M(r)        ASICREV_IS(r, BONAIRE)
121 #define ASICREV_IS_HAWAII_P(r)         ASICREV_IS(r, HAWAII)
122 
123 #define ASICREV_IS_SPECTRE(r)          ASICREV_IS(r, SPECTRE)
124 #define ASICREV_IS_SPOOKY(r)           ASICREV_IS(r, SPOOKY)
125 #define ASICREV_IS_KALINDI(r)          ASICREV_IS(r, KALINDI)
126 #define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI)
127 
128 #define ASICREV_IS_ICELAND_M(r)        ASICREV_IS(r, ICELAND)
129 #define ASICREV_IS_TONGA_P(r)          ASICREV_IS(r, TONGA)
130 #define ASICREV_IS_FIJI_P(r)           ASICREV_IS(r, FIJI)
131 
132 #define ASICREV_IS_POLARIS10_P(r)      ASICREV_IS(r, POLARIS10)
133 #define ASICREV_IS_POLARIS11_M(r)      ASICREV_IS(r, POLARIS11)
134 #define ASICREV_IS_POLARIS12_V(r)      ASICREV_IS(r, POLARIS12)
135 #define ASICREV_IS_VEGAM_P(r)          ASICREV_IS(r, VEGAM)
136 
137 #define ASICREV_IS_CARRIZO(r)          ASICREV_IS(r, CARRIZO)
138 #define ASICREV_IS_STONEY(r)           ASICREV_IS(r, STONEY)
139 
140 #define ASICREV_IS_VEGA10_M(r)         ASICREV_IS(r, VEGA10)
141 #define ASICREV_IS_VEGA10_P(r)         ASICREV_IS(r, VEGA10)
142 #define ASICREV_IS_VEGA12_P(r)         ASICREV_IS(r, VEGA12)
143 #define ASICREV_IS_VEGA12_p(r)         ASICREV_IS(r, VEGA12)
144 #define ASICREV_IS_VEGA20_P(r)         ASICREV_IS(r, VEGA20)
145 #define ASICREV_IS_ARCTURUS(r)         ASICREV_IS(r, ARCTURUS)
146 
147 #define ASICREV_IS_RAVEN(r)            ASICREV_IS(r, RAVEN)
148 #define ASICREV_IS_RAVEN2(r)           ASICREV_IS(r, RAVEN2)
149 #define ASICREV_IS_RENOIR(r)           ASICREV_IS(r, RENOIR)
150 
151 #define ASICREV_IS_NAVI10_P(r)         ASICREV_IS(r, NAVI10)
152 #define ASICREV_IS_NAVI12_P(r)         ASICREV_IS(r, NAVI12)
153 #define ASICREV_IS_NAVI14_M(r)         ASICREV_IS(r, NAVI14)
154 #define ASICREV_IS_SIENNA_CICHLID(r)   ASICREV_IS(r, SIENNA_CICHLID)
155 #define ASICREV_IS_NAVY_FLOUNDER(r)    ASICREV_IS(r, NAVY_FLOUNDER)
156 #define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
157 
158 #define ASICREV_IS_VANGOGH(r)          ASICREV_IS(r, VANGOGH)
159 
160 #endif // _AMDGPU_ASIC_ADDR_H
161