1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include <stdint.h>
36 #include <stdlib.h>
37 #include "util/macros.h"
38
39 /* The following hunk, up-to "Execution Unit" is used by both the
40 * intel/compiler and i965 codebase. */
41
42 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
43 /* Using the GNU statement expression extension */
44 #define SET_FIELD(value, field) \
45 ({ \
46 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
47 assert((fieldval & ~ field ## _MASK) == 0); \
48 fieldval & field ## _MASK; \
49 })
50
51 #define SET_BITS(value, high, low) \
52 ({ \
53 const uint32_t fieldval = (uint32_t)(value) << (low); \
54 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
55 fieldval & INTEL_MASK(high, low); \
56 })
57
58 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
59 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
60
61 #define _3DPRIM_POINTLIST 0x01
62 #define _3DPRIM_LINELIST 0x02
63 #define _3DPRIM_LINESTRIP 0x03
64 #define _3DPRIM_TRILIST 0x04
65 #define _3DPRIM_TRISTRIP 0x05
66 #define _3DPRIM_TRIFAN 0x06
67 #define _3DPRIM_QUADLIST 0x07
68 #define _3DPRIM_QUADSTRIP 0x08
69 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
70 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
71 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
72 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
73 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
74 #define _3DPRIM_POLYGON 0x0E
75 #define _3DPRIM_RECTLIST 0x0F
76 #define _3DPRIM_LINELOOP 0x10
77 #define _3DPRIM_POINTLIST_BF 0x11
78 #define _3DPRIM_LINESTRIP_CONT 0x12
79 #define _3DPRIM_LINESTRIP_BF 0x13
80 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
81 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
82 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
83
84 /* Bitfields for the URB_WRITE message, DW2 of message header: */
85 #define URB_WRITE_PRIM_END 0x1
86 #define URB_WRITE_PRIM_START 0x2
87 #define URB_WRITE_PRIM_TYPE_SHIFT 2
88
89 #define BRW_SPRITE_POINT_ENABLE 16
90
91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
92 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
93
94 /* Execution Unit (EU) defines
95 */
96
97 #define BRW_ALIGN_1 0
98 #define BRW_ALIGN_16 1
99
100 #define BRW_ADDRESS_DIRECT 0
101 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
102
103 #define BRW_CHANNEL_X 0
104 #define BRW_CHANNEL_Y 1
105 #define BRW_CHANNEL_Z 2
106 #define BRW_CHANNEL_W 3
107
108 enum brw_compression {
109 BRW_COMPRESSION_NONE = 0,
110 BRW_COMPRESSION_2NDHALF = 1,
111 BRW_COMPRESSION_COMPRESSED = 2,
112 };
113
114 #define GEN6_COMPRESSION_1Q 0
115 #define GEN6_COMPRESSION_2Q 1
116 #define GEN6_COMPRESSION_3Q 2
117 #define GEN6_COMPRESSION_4Q 3
118 #define GEN6_COMPRESSION_1H 0
119 #define GEN6_COMPRESSION_2H 2
120
121 enum PACKED brw_conditional_mod {
122 BRW_CONDITIONAL_NONE = 0,
123 BRW_CONDITIONAL_Z = 1,
124 BRW_CONDITIONAL_NZ = 2,
125 BRW_CONDITIONAL_EQ = 1, /* Z */
126 BRW_CONDITIONAL_NEQ = 2, /* NZ */
127 BRW_CONDITIONAL_G = 3,
128 BRW_CONDITIONAL_GE = 4,
129 BRW_CONDITIONAL_L = 5,
130 BRW_CONDITIONAL_LE = 6,
131 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
132 BRW_CONDITIONAL_O = 8,
133 BRW_CONDITIONAL_U = 9,
134 };
135
136 #define BRW_DEBUG_NONE 0
137 #define BRW_DEBUG_BREAKPOINT 1
138
139 #define BRW_DEPENDENCY_NORMAL 0
140 #define BRW_DEPENDENCY_NOTCLEARED 1
141 #define BRW_DEPENDENCY_NOTCHECKED 2
142 #define BRW_DEPENDENCY_DISABLE 3
143
144 enum PACKED brw_execution_size {
145 BRW_EXECUTE_1 = 0,
146 BRW_EXECUTE_2 = 1,
147 BRW_EXECUTE_4 = 2,
148 BRW_EXECUTE_8 = 3,
149 BRW_EXECUTE_16 = 4,
150 BRW_EXECUTE_32 = 5,
151 };
152
153 enum PACKED brw_horizontal_stride {
154 BRW_HORIZONTAL_STRIDE_0 = 0,
155 BRW_HORIZONTAL_STRIDE_1 = 1,
156 BRW_HORIZONTAL_STRIDE_2 = 2,
157 BRW_HORIZONTAL_STRIDE_4 = 3,
158 };
159
160 enum PACKED gen10_align1_3src_src_horizontal_stride {
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
163 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
164 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
165 };
166
167 enum PACKED gen10_align1_3src_dst_horizontal_stride {
168 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
169 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
170 };
171
172 #define BRW_INSTRUCTION_NORMAL 0
173 #define BRW_INSTRUCTION_SATURATE 1
174
175 #define BRW_MASK_ENABLE 0
176 #define BRW_MASK_DISABLE 1
177
178 /** @{
179 *
180 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
181 * effectively the same but much simpler to think about. Now, there
182 * are two contributors ANDed together to whether channels are
183 * executed: The predication on the instruction, and the channel write
184 * enable.
185 */
186 /**
187 * This is the default value. It means that a channel's write enable is set
188 * if the per-channel IP is pointing at this instruction.
189 */
190 #define BRW_WE_NORMAL 0
191 /**
192 * This is used like BRW_MASK_DISABLE, and causes all channels to have
193 * their write enable set. Note that predication still contributes to
194 * whether the channel actually gets written.
195 */
196 #define BRW_WE_ALL 1
197 /** @} */
198
199 enum opcode {
200 /* These are the actual hardware instructions. */
201 BRW_OPCODE_ILLEGAL,
202 BRW_OPCODE_SYNC,
203 BRW_OPCODE_MOV,
204 BRW_OPCODE_SEL,
205 BRW_OPCODE_MOVI, /**< G45+ */
206 BRW_OPCODE_NOT,
207 BRW_OPCODE_AND,
208 BRW_OPCODE_OR,
209 BRW_OPCODE_XOR,
210 BRW_OPCODE_SHR,
211 BRW_OPCODE_SHL,
212 BRW_OPCODE_DIM, /**< Gen7.5 only */
213 BRW_OPCODE_SMOV, /**< Gen8+ */
214 BRW_OPCODE_ASR,
215 BRW_OPCODE_ROR, /**< Gen11+ */
216 BRW_OPCODE_ROL, /**< Gen11+ */
217 BRW_OPCODE_CMP,
218 BRW_OPCODE_CMPN,
219 BRW_OPCODE_CSEL, /**< Gen8+ */
220 BRW_OPCODE_F32TO16, /**< Gen7 only */
221 BRW_OPCODE_F16TO32, /**< Gen7 only */
222 BRW_OPCODE_BFREV, /**< Gen7+ */
223 BRW_OPCODE_BFE, /**< Gen7+ */
224 BRW_OPCODE_BFI1, /**< Gen7+ */
225 BRW_OPCODE_BFI2, /**< Gen7+ */
226 BRW_OPCODE_JMPI,
227 BRW_OPCODE_BRD, /**< Gen7+ */
228 BRW_OPCODE_IF,
229 BRW_OPCODE_IFF, /**< Pre-Gen6 */
230 BRW_OPCODE_BRC, /**< Gen7+ */
231 BRW_OPCODE_ELSE,
232 BRW_OPCODE_ENDIF,
233 BRW_OPCODE_DO, /**< Pre-Gen6 */
234 BRW_OPCODE_CASE, /**< Gen6 only */
235 BRW_OPCODE_WHILE,
236 BRW_OPCODE_BREAK,
237 BRW_OPCODE_CONTINUE,
238 BRW_OPCODE_HALT,
239 BRW_OPCODE_CALLA, /**< Gen7.5+ */
240 BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
241 BRW_OPCODE_CALL, /**< Gen6+ */
242 BRW_OPCODE_MREST, /**< Pre-Gen6 */
243 BRW_OPCODE_RET, /**< Gen6+ */
244 BRW_OPCODE_PUSH, /**< Pre-Gen6 */
245 BRW_OPCODE_FORK, /**< Gen6 only */
246 BRW_OPCODE_GOTO, /**< Gen8+ */
247 BRW_OPCODE_POP, /**< Pre-Gen6 */
248 BRW_OPCODE_WAIT,
249 BRW_OPCODE_SEND,
250 BRW_OPCODE_SENDC,
251 BRW_OPCODE_SENDS, /**< Gen9+ */
252 BRW_OPCODE_SENDSC, /**< Gen9+ */
253 BRW_OPCODE_MATH, /**< Gen6+ */
254 BRW_OPCODE_ADD,
255 BRW_OPCODE_MUL,
256 BRW_OPCODE_AVG,
257 BRW_OPCODE_FRC,
258 BRW_OPCODE_RNDU,
259 BRW_OPCODE_RNDD,
260 BRW_OPCODE_RNDE,
261 BRW_OPCODE_RNDZ,
262 BRW_OPCODE_MAC,
263 BRW_OPCODE_MACH,
264 BRW_OPCODE_LZD,
265 BRW_OPCODE_FBH, /**< Gen7+ */
266 BRW_OPCODE_FBL, /**< Gen7+ */
267 BRW_OPCODE_CBIT, /**< Gen7+ */
268 BRW_OPCODE_ADDC, /**< Gen7+ */
269 BRW_OPCODE_SUBB, /**< Gen7+ */
270 BRW_OPCODE_SAD2,
271 BRW_OPCODE_SADA2,
272 BRW_OPCODE_DP4,
273 BRW_OPCODE_DPH,
274 BRW_OPCODE_DP3,
275 BRW_OPCODE_DP2,
276 BRW_OPCODE_LINE,
277 BRW_OPCODE_PLN, /**< G45+ */
278 BRW_OPCODE_MAD, /**< Gen6+ */
279 BRW_OPCODE_LRP, /**< Gen6+ */
280 BRW_OPCODE_MADM, /**< Gen8+ */
281 BRW_OPCODE_NENOP, /**< G45 only */
282 BRW_OPCODE_NOP,
283
284 NUM_BRW_OPCODES,
285
286 /* These are compiler backend opcodes that get translated into other
287 * instructions.
288 */
289 FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
290
291 /**
292 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
293 * individual sources instead of as a single payload blob. The
294 * position/ordering of the arguments are defined by the enum
295 * fb_write_logical_srcs.
296 */
297 FS_OPCODE_FB_WRITE_LOGICAL,
298
299 FS_OPCODE_REP_FB_WRITE,
300
301 FS_OPCODE_FB_READ,
302 FS_OPCODE_FB_READ_LOGICAL,
303
304 SHADER_OPCODE_RCP,
305 SHADER_OPCODE_RSQ,
306 SHADER_OPCODE_SQRT,
307 SHADER_OPCODE_EXP2,
308 SHADER_OPCODE_LOG2,
309 SHADER_OPCODE_POW,
310 SHADER_OPCODE_INT_QUOTIENT,
311 SHADER_OPCODE_INT_REMAINDER,
312 SHADER_OPCODE_SIN,
313 SHADER_OPCODE_COS,
314
315 /**
316 * A generic "send" opcode. The first two sources are the message
317 * descriptor and extended message descriptor respectively. The third
318 * and optional fourth sources are the message payload
319 */
320 SHADER_OPCODE_SEND,
321
322 /**
323 * An "undefined" write which does nothing but indicates to liveness that
324 * we don't care about any values in the register which predate this
325 * instruction. Used to prevent partial writes from causing issues with
326 * live ranges.
327 */
328 SHADER_OPCODE_UNDEF,
329
330 /**
331 * Texture sampling opcodes.
332 *
333 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
334 * opcode but instead of taking a single payload blob they expect their
335 * arguments separately as individual sources. The position/ordering of the
336 * arguments are defined by the enum tex_logical_srcs.
337 */
338 SHADER_OPCODE_TEX,
339 SHADER_OPCODE_TEX_LOGICAL,
340 SHADER_OPCODE_TXD,
341 SHADER_OPCODE_TXD_LOGICAL,
342 SHADER_OPCODE_TXF,
343 SHADER_OPCODE_TXF_LOGICAL,
344 SHADER_OPCODE_TXF_LZ,
345 SHADER_OPCODE_TXL,
346 SHADER_OPCODE_TXL_LOGICAL,
347 SHADER_OPCODE_TXL_LZ,
348 SHADER_OPCODE_TXS,
349 SHADER_OPCODE_TXS_LOGICAL,
350 FS_OPCODE_TXB,
351 FS_OPCODE_TXB_LOGICAL,
352 SHADER_OPCODE_TXF_CMS,
353 SHADER_OPCODE_TXF_CMS_LOGICAL,
354 SHADER_OPCODE_TXF_CMS_W,
355 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
356 SHADER_OPCODE_TXF_UMS,
357 SHADER_OPCODE_TXF_UMS_LOGICAL,
358 SHADER_OPCODE_TXF_MCS,
359 SHADER_OPCODE_TXF_MCS_LOGICAL,
360 SHADER_OPCODE_LOD,
361 SHADER_OPCODE_LOD_LOGICAL,
362 SHADER_OPCODE_TG4,
363 SHADER_OPCODE_TG4_LOGICAL,
364 SHADER_OPCODE_TG4_OFFSET,
365 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
366 SHADER_OPCODE_SAMPLEINFO,
367 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
368
369 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
370
371 /**
372 * Combines multiple sources of size 1 into a larger virtual GRF.
373 * For example, parameters for a send-from-GRF message. Or, updating
374 * channels of a size 4 VGRF used to store vec4s such as texturing results.
375 *
376 * This will be lowered into MOVs from each source to consecutive offsets
377 * of the destination VGRF.
378 *
379 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
380 * but still reserves the first channel of the destination VGRF. This can be
381 * used to reserve space for, say, a message header set up by the generators.
382 */
383 SHADER_OPCODE_LOAD_PAYLOAD,
384
385 /**
386 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
387 * acts intra-channel, obtaining the final value for each channel by
388 * combining the sources values for the same channel, the first source
389 * occupying the lowest bits and the last source occupying the highest
390 * bits.
391 */
392 FS_OPCODE_PACK,
393
394 SHADER_OPCODE_SHADER_TIME_ADD,
395
396 /**
397 * Typed and untyped surface access opcodes.
398 *
399 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
400 * opcode but instead of taking a single payload blob they expect their
401 * arguments separately as individual sources:
402 *
403 * Source 0: [required] Surface coordinates.
404 * Source 1: [optional] Operation source.
405 * Source 2: [required] Surface index.
406 * Source 3: [required] Number of coordinate components (as UD immediate).
407 * Source 4: [required] Opcode-specific control immediate, same as source 2
408 * of the matching non-LOGICAL opcode.
409 */
410 VEC4_OPCODE_UNTYPED_ATOMIC,
411 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
412 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
413 VEC4_OPCODE_UNTYPED_SURFACE_READ,
414 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
415 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
416 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
417
418 SHADER_OPCODE_OWORD_BLOCK_READ_LOGICAL,
419 SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
420 SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL,
421
422 /**
423 * Untyped A64 surface access opcodes.
424 *
425 * Source 0: 64-bit address
426 * Source 1: Operational source
427 * Source 2: [required] Opcode-specific control immediate, same as source 2
428 * of the matching non-LOGICAL opcode.
429 */
430 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
431 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
432 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
433 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
434 SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL,
435 SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL,
436 SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL,
437 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
438 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
439 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
440
441 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
442 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
443 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
444
445 SHADER_OPCODE_RND_MODE,
446 SHADER_OPCODE_FLOAT_CONTROL_MODE,
447
448 /**
449 * Byte scattered write/read opcodes.
450 *
451 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
452 * opcode, but instead of taking a single payload blog they expect their
453 * arguments separately as individual sources, like untyped write/read.
454 */
455 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
456 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
457 SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
458 SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
459
460 /**
461 * Memory fence messages.
462 *
463 * Source 0: Must be register g0, used as header.
464 * Source 1: Immediate bool to indicate whether control is returned to the
465 * thread only after the fence has been honored.
466 * Source 2: Immediate byte indicating which memory to fence. Zero means
467 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
468 *
469 * Vec4 backend only uses Source 0.
470 */
471 SHADER_OPCODE_MEMORY_FENCE,
472
473 /**
474 * Scheduling-only fence.
475 *
476 * Sources can be used to force a stall until the registers in those are
477 * available. This might generate MOVs or SYNC_NOPs (Gen12+).
478 */
479 FS_OPCODE_SCHEDULING_FENCE,
480
481 SHADER_OPCODE_GEN4_SCRATCH_READ,
482 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
483 SHADER_OPCODE_GEN7_SCRATCH_READ,
484
485 SHADER_OPCODE_SCRATCH_HEADER,
486
487 /**
488 * Gen8+ SIMD8 URB Read messages.
489 */
490 SHADER_OPCODE_URB_READ_SIMD8,
491 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
492
493 SHADER_OPCODE_URB_WRITE_SIMD8,
494 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
495 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
496 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
497
498 /**
499 * Return the index of an arbitrary live channel (i.e. one of the channels
500 * enabled in the current execution mask) and assign it to the first
501 * component of the destination. Expected to be used as input for the
502 * BROADCAST pseudo-opcode.
503 */
504 SHADER_OPCODE_FIND_LIVE_CHANNEL,
505
506 /**
507 * Return the current execution mask in the specified flag subregister.
508 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register.
509 */
510 FS_OPCODE_LOAD_LIVE_CHANNELS,
511
512 /**
513 * Pick the channel from its first source register given by the index
514 * specified as second source. Useful for variable indexing of surfaces.
515 *
516 * Note that because the result of this instruction is by definition
517 * uniform and it can always be splatted to multiple channels using a
518 * scalar regioning mode, only the first channel of the destination region
519 * is guaranteed to be updated, which implies that BROADCAST instructions
520 * should usually be marked force_writemask_all.
521 */
522 SHADER_OPCODE_BROADCAST,
523
524 /* Pick the channel from its first source register given by the index
525 * specified as second source.
526 *
527 * This is similar to the BROADCAST instruction except that it takes a
528 * dynamic index and potentially puts a different value in each output
529 * channel.
530 */
531 SHADER_OPCODE_SHUFFLE,
532
533 /* Select between src0 and src1 based on channel enables.
534 *
535 * This instruction copies src0 into the enabled channels of the
536 * destination and copies src1 into the disabled channels.
537 */
538 SHADER_OPCODE_SEL_EXEC,
539
540 /* This turns into an align16 mov from src0 to dst with a swizzle
541 * provided as an immediate in src1.
542 */
543 SHADER_OPCODE_QUAD_SWIZZLE,
544
545 /* Take every Nth element in src0 and broadcast it to the group of N
546 * channels in which it lives in the destination. The offset within the
547 * cluster is given by src1 and the cluster size is given by src2.
548 */
549 SHADER_OPCODE_CLUSTER_BROADCAST,
550
551 SHADER_OPCODE_GET_BUFFER_SIZE,
552
553 SHADER_OPCODE_INTERLOCK,
554
555 VEC4_OPCODE_MOV_BYTES,
556 VEC4_OPCODE_PACK_BYTES,
557 VEC4_OPCODE_UNPACK_UNIFORM,
558 VEC4_OPCODE_DOUBLE_TO_F32,
559 VEC4_OPCODE_DOUBLE_TO_D32,
560 VEC4_OPCODE_DOUBLE_TO_U32,
561 VEC4_OPCODE_TO_DOUBLE,
562 VEC4_OPCODE_PICK_LOW_32BIT,
563 VEC4_OPCODE_PICK_HIGH_32BIT,
564 VEC4_OPCODE_SET_LOW_32BIT,
565 VEC4_OPCODE_SET_HIGH_32BIT,
566
567 FS_OPCODE_DDX_COARSE,
568 FS_OPCODE_DDX_FINE,
569 /**
570 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
571 */
572 FS_OPCODE_DDY_COARSE,
573 FS_OPCODE_DDY_FINE,
574 FS_OPCODE_LINTERP,
575 FS_OPCODE_PIXEL_X,
576 FS_OPCODE_PIXEL_Y,
577 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
578 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
579 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
580 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
581 FS_OPCODE_DISCARD_JUMP,
582 FS_OPCODE_SET_SAMPLE_ID,
583 FS_OPCODE_PACK_HALF_2x16_SPLIT,
584 FS_OPCODE_PLACEHOLDER_HALT,
585 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
586 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
587 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
588
589 VS_OPCODE_URB_WRITE,
590 VS_OPCODE_PULL_CONSTANT_LOAD,
591 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
592
593 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
594
595 /**
596 * Write geometry shader output data to the URB.
597 *
598 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
599 * R0 to the first MRF. This allows the geometry shader to override the
600 * "Slot {0,1} Offset" fields in the message header.
601 */
602 GS_OPCODE_URB_WRITE,
603
604 /**
605 * Write geometry shader output data to the URB and request a new URB
606 * handle (gen6).
607 *
608 * This opcode doesn't do an implied move from R0 to the first MRF.
609 */
610 GS_OPCODE_URB_WRITE_ALLOCATE,
611
612 /**
613 * Terminate the geometry shader thread by doing an empty URB write.
614 *
615 * This opcode doesn't do an implied move from R0 to the first MRF. This
616 * allows the geometry shader to override the "GS Number of Output Vertices
617 * for Slot {0,1}" fields in the message header.
618 */
619 GS_OPCODE_THREAD_END,
620
621 /**
622 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
623 *
624 * - dst is the MRF containing the message header.
625 *
626 * - src0.x indicates which portion of the URB should be written to (e.g. a
627 * vertex number)
628 *
629 * - src1 is an immediate multiplier which will be applied to src0
630 * (e.g. the size of a single vertex in the URB).
631 *
632 * Note: the hardware will apply this offset *in addition to* the offset in
633 * vec4_instruction::offset.
634 */
635 GS_OPCODE_SET_WRITE_OFFSET,
636
637 /**
638 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
639 * URB_WRITE message header.
640 *
641 * - dst is the MRF containing the message header.
642 *
643 * - src0.x is the vertex count. The upper 16 bits will be ignored.
644 */
645 GS_OPCODE_SET_VERTEX_COUNT,
646
647 /**
648 * Set DWORD 2 of dst to the value in src.
649 */
650 GS_OPCODE_SET_DWORD_2,
651
652 /**
653 * Prepare the dst register for storage in the "Channel Mask" fields of a
654 * URB_WRITE message header.
655 *
656 * DWORD 4 of dst is shifted left by 4 bits, so that later,
657 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
658 * final channel mask.
659 *
660 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
661 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
662 * have any extraneous bits set prior to execution of this opcode (that is,
663 * they should be in the range 0x0 to 0xf).
664 */
665 GS_OPCODE_PREPARE_CHANNEL_MASKS,
666
667 /**
668 * Set the "Channel Mask" fields of a URB_WRITE message header.
669 *
670 * - dst is the MRF containing the message header.
671 *
672 * - src.x is the channel mask, as prepared by
673 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
674 * form the final channel mask.
675 */
676 GS_OPCODE_SET_CHANNEL_MASKS,
677
678 /**
679 * Get the "Instance ID" fields from the payload.
680 *
681 * - dst is the GRF for gl_InvocationID.
682 */
683 GS_OPCODE_GET_INSTANCE_ID,
684
685 /**
686 * Send a FF_SYNC message to allocate initial URB handles (gen6).
687 *
688 * - dst will be used as the writeback register for the FF_SYNC operation.
689 *
690 * - src0 is the number of primitives written.
691 *
692 * - src1 is the value to hold in M0.0: number of SO vertices to write
693 * and number of SO primitives needed. Its value will be overwritten
694 * with the SVBI values if transform feedback is enabled.
695 *
696 * Note: This opcode uses an implicit MRF register for the ff_sync message
697 * header, so the caller is expected to set inst->base_mrf and initialize
698 * that MRF register to r0. This opcode will also write to this MRF register
699 * to include the allocated URB handle so it can then be reused directly as
700 * the header in the URB write operation we are allocating the handle for.
701 */
702 GS_OPCODE_FF_SYNC,
703
704 /**
705 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
706 * register.
707 *
708 * - dst is the GRF where PrimitiveID information will be moved.
709 */
710 GS_OPCODE_SET_PRIMITIVE_ID,
711
712 /**
713 * Write transform feedback data to the SVB by sending a SVB WRITE message.
714 * Used in gen6.
715 *
716 * - dst is the MRF register containing the message header.
717 *
718 * - src0 is the register where the vertex data is going to be copied from.
719 *
720 * - src1 is the destination register when write commit occurs.
721 */
722 GS_OPCODE_SVB_WRITE,
723
724 /**
725 * Set destination index in the SVB write message payload (M0.5). Used
726 * in gen6 for transform feedback.
727 *
728 * - dst is the header to save the destination indices for SVB WRITE.
729 * - src is the register that holds the destination indices value.
730 */
731 GS_OPCODE_SVB_SET_DST_INDEX,
732
733 /**
734 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
735 * Used in gen6 for transform feedback.
736 *
737 * - dst will hold the register with the final Mx.0 value.
738 *
739 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
740 *
741 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
742 *
743 * - src2 is the value to hold in M0: number of SO vertices to write
744 * and number of SO primitives needed.
745 */
746 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
747
748 /**
749 * Terminate the compute shader.
750 */
751 CS_OPCODE_CS_TERMINATE,
752
753 /**
754 * GLSL barrier()
755 */
756 SHADER_OPCODE_BARRIER,
757
758 /**
759 * Calculate the high 32-bits of a 32x32 multiply.
760 */
761 SHADER_OPCODE_MULH,
762
763 /** Signed subtraction with saturation. */
764 SHADER_OPCODE_ISUB_SAT,
765
766 /** Unsigned subtraction with saturation. */
767 SHADER_OPCODE_USUB_SAT,
768
769 /**
770 * A MOV that uses VxH indirect addressing.
771 *
772 * Source 0: A register to start from (HW_REG).
773 * Source 1: An indirect offset (in bytes, UD GRF).
774 * Source 2: The length of the region that could be accessed (in bytes,
775 * UD immediate).
776 */
777 SHADER_OPCODE_MOV_INDIRECT,
778
779 /** Fills out a relocatable immediate */
780 SHADER_OPCODE_MOV_RELOC_IMM,
781
782 VEC4_OPCODE_URB_READ,
783 TCS_OPCODE_GET_INSTANCE_ID,
784 TCS_OPCODE_URB_WRITE,
785 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
786 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
787 TCS_OPCODE_GET_PRIMITIVE_ID,
788 TCS_OPCODE_CREATE_BARRIER_HEADER,
789 TCS_OPCODE_SRC0_010_IS_ZERO,
790 TCS_OPCODE_RELEASE_INPUT,
791 TCS_OPCODE_THREAD_END,
792
793 TES_OPCODE_GET_PRIMITIVE_ID,
794 TES_OPCODE_CREATE_INPUT_READ_HEADER,
795 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
796 };
797
798 enum brw_urb_write_flags {
799 BRW_URB_WRITE_NO_FLAGS = 0,
800
801 /**
802 * Causes a new URB entry to be allocated, and its address stored in the
803 * destination register (gen < 7).
804 */
805 BRW_URB_WRITE_ALLOCATE = 0x1,
806
807 /**
808 * Causes the current URB entry to be deallocated (gen < 7).
809 */
810 BRW_URB_WRITE_UNUSED = 0x2,
811
812 /**
813 * Causes the thread to terminate.
814 */
815 BRW_URB_WRITE_EOT = 0x4,
816
817 /**
818 * Indicates that the given URB entry is complete, and may be sent further
819 * down the 3D pipeline (gen < 7).
820 */
821 BRW_URB_WRITE_COMPLETE = 0x8,
822
823 /**
824 * Indicates that an additional offset (which may be different for the two
825 * vec4 slots) is stored in the message header (gen == 7).
826 */
827 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
828
829 /**
830 * Indicates that the channel masks in the URB_WRITE message header should
831 * not be overridden to 0xff (gen == 7).
832 */
833 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
834
835 /**
836 * Indicates that the data should be sent to the URB using the
837 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
838 * causes offsets to be interpreted as multiples of an OWORD instead of an
839 * HWORD, and only allows one OWORD to be written.
840 */
841 BRW_URB_WRITE_OWORD = 0x40,
842
843 /**
844 * Convenient combination of flags: end the thread while simultaneously
845 * marking the given URB entry as complete.
846 */
847 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
848
849 /**
850 * Convenient combination of flags: mark the given URB entry as complete
851 * and simultaneously allocate a new one.
852 */
853 BRW_URB_WRITE_ALLOCATE_COMPLETE =
854 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
855 };
856
857 enum fb_write_logical_srcs {
858 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
859 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
860 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
861 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
862 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
863 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
864 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
865 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
866 FB_WRITE_LOGICAL_NUM_SRCS
867 };
868
869 enum tex_logical_srcs {
870 /** Texture coordinates */
871 TEX_LOGICAL_SRC_COORDINATE,
872 /** Shadow comparator */
873 TEX_LOGICAL_SRC_SHADOW_C,
874 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
875 TEX_LOGICAL_SRC_LOD,
876 /** dPdy if the operation takes explicit derivatives */
877 TEX_LOGICAL_SRC_LOD2,
878 /** Min LOD */
879 TEX_LOGICAL_SRC_MIN_LOD,
880 /** Sample index */
881 TEX_LOGICAL_SRC_SAMPLE_INDEX,
882 /** MCS data */
883 TEX_LOGICAL_SRC_MCS,
884 /** REQUIRED: Texture surface index */
885 TEX_LOGICAL_SRC_SURFACE,
886 /** Texture sampler index */
887 TEX_LOGICAL_SRC_SAMPLER,
888 /** Texture surface bindless handle */
889 TEX_LOGICAL_SRC_SURFACE_HANDLE,
890 /** Texture sampler bindless handle */
891 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
892 /** Texel offset for gathers */
893 TEX_LOGICAL_SRC_TG4_OFFSET,
894 /** REQUIRED: Number of coordinate components (as UD immediate) */
895 TEX_LOGICAL_SRC_COORD_COMPONENTS,
896 /** REQUIRED: Number of derivative components (as UD immediate) */
897 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
898
899 TEX_LOGICAL_NUM_SRCS,
900 };
901
902 enum surface_logical_srcs {
903 /** Surface binding table index */
904 SURFACE_LOGICAL_SRC_SURFACE,
905 /** Surface bindless handle */
906 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
907 /** Surface address; could be multi-dimensional for typed opcodes */
908 SURFACE_LOGICAL_SRC_ADDRESS,
909 /** Data to be written or used in an atomic op */
910 SURFACE_LOGICAL_SRC_DATA,
911 /** Surface number of dimensions. Affects the size of ADDRESS */
912 SURFACE_LOGICAL_SRC_IMM_DIMS,
913 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
914 SURFACE_LOGICAL_SRC_IMM_ARG,
915 /**
916 * Some instructions with side-effects should not be predicated on
917 * sample mask, e.g. lowered stores to scratch.
918 */
919 SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK,
920
921 SURFACE_LOGICAL_NUM_SRCS
922 };
923
924 #ifdef __cplusplus
925 /**
926 * Allow brw_urb_write_flags enums to be ORed together.
927 */
928 inline brw_urb_write_flags
929 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
930 {
931 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
932 static_cast<int>(y));
933 }
934 #endif
935
936 enum PACKED brw_predicate {
937 BRW_PREDICATE_NONE = 0,
938 BRW_PREDICATE_NORMAL = 1,
939 BRW_PREDICATE_ALIGN1_ANYV = 2,
940 BRW_PREDICATE_ALIGN1_ALLV = 3,
941 BRW_PREDICATE_ALIGN1_ANY2H = 4,
942 BRW_PREDICATE_ALIGN1_ALL2H = 5,
943 BRW_PREDICATE_ALIGN1_ANY4H = 6,
944 BRW_PREDICATE_ALIGN1_ALL4H = 7,
945 BRW_PREDICATE_ALIGN1_ANY8H = 8,
946 BRW_PREDICATE_ALIGN1_ALL8H = 9,
947 BRW_PREDICATE_ALIGN1_ANY16H = 10,
948 BRW_PREDICATE_ALIGN1_ALL16H = 11,
949 BRW_PREDICATE_ALIGN1_ANY32H = 12,
950 BRW_PREDICATE_ALIGN1_ALL32H = 13,
951 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
952 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
953 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
954 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
955 BRW_PREDICATE_ALIGN16_ANY4H = 6,
956 BRW_PREDICATE_ALIGN16_ALL4H = 7,
957 };
958
959 enum PACKED brw_reg_file {
960 BRW_ARCHITECTURE_REGISTER_FILE = 0,
961 BRW_GENERAL_REGISTER_FILE = 1,
962 BRW_MESSAGE_REGISTER_FILE = 2,
963 BRW_IMMEDIATE_VALUE = 3,
964
965 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
966 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
967 MRF = BRW_MESSAGE_REGISTER_FILE,
968 IMM = BRW_IMMEDIATE_VALUE,
969
970 /* These are not hardware values */
971 VGRF,
972 ATTR,
973 UNIFORM, /* prog_data->params[reg] */
974 BAD_FILE,
975 };
976
977 enum PACKED gen10_align1_3src_reg_file {
978 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
979 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
980 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
981 };
982
983 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
984 * word is "Execution Datatype" which controls whether the instruction operates
985 * on float or integer types. The register arguments have fields that offer
986 * more fine control their respective types.
987 */
988 enum PACKED gen10_align1_3src_exec_type {
989 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
990 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
991 };
992
993 #define BRW_ARF_NULL 0x00
994 #define BRW_ARF_ADDRESS 0x10
995 #define BRW_ARF_ACCUMULATOR 0x20
996 #define BRW_ARF_FLAG 0x30
997 #define BRW_ARF_MASK 0x40
998 #define BRW_ARF_MASK_STACK 0x50
999 #define BRW_ARF_MASK_STACK_DEPTH 0x60
1000 #define BRW_ARF_STATE 0x70
1001 #define BRW_ARF_CONTROL 0x80
1002 #define BRW_ARF_NOTIFICATION_COUNT 0x90
1003 #define BRW_ARF_IP 0xA0
1004 #define BRW_ARF_TDR 0xB0
1005 #define BRW_ARF_TIMESTAMP 0xC0
1006
1007 #define BRW_MRF_COMPR4 (1 << 7)
1008
1009 #define BRW_AMASK 0
1010 #define BRW_IMASK 1
1011 #define BRW_LMASK 2
1012 #define BRW_CMASK 3
1013
1014
1015
1016 #define BRW_THREAD_NORMAL 0
1017 #define BRW_THREAD_ATOMIC 1
1018 #define BRW_THREAD_SWITCH 2
1019
1020 enum PACKED brw_vertical_stride {
1021 BRW_VERTICAL_STRIDE_0 = 0,
1022 BRW_VERTICAL_STRIDE_1 = 1,
1023 BRW_VERTICAL_STRIDE_2 = 2,
1024 BRW_VERTICAL_STRIDE_4 = 3,
1025 BRW_VERTICAL_STRIDE_8 = 4,
1026 BRW_VERTICAL_STRIDE_16 = 5,
1027 BRW_VERTICAL_STRIDE_32 = 6,
1028 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1029 };
1030
1031 enum PACKED gen10_align1_3src_vertical_stride {
1032 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1033 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
1034 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1035 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1036 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1037 };
1038
1039 enum PACKED brw_width {
1040 BRW_WIDTH_1 = 0,
1041 BRW_WIDTH_2 = 1,
1042 BRW_WIDTH_4 = 2,
1043 BRW_WIDTH_8 = 3,
1044 BRW_WIDTH_16 = 4,
1045 };
1046
1047 /**
1048 * Gen12+ SWSB SBID synchronization mode.
1049 *
1050 * This is represented as a bitmask including any required SBID token
1051 * synchronization modes, used to synchronize out-of-order instructions. Only
1052 * the strongest mode of the mask will be provided to the hardware in the SWSB
1053 * field of an actual hardware instruction, but virtual instructions may be
1054 * able to take into account multiple of them.
1055 */
1056 enum tgl_sbid_mode {
1057 TGL_SBID_NULL = 0,
1058 TGL_SBID_SRC = 1,
1059 TGL_SBID_DST = 2,
1060 TGL_SBID_SET = 4
1061 };
1062
1063 #ifdef __cplusplus
1064 /**
1065 * Allow bitwise arithmetic of tgl_sbid_mode enums.
1066 */
1067 inline tgl_sbid_mode
1068 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1069 {
1070 return tgl_sbid_mode(unsigned(x) | unsigned(y));
1071 }
1072
1073 inline tgl_sbid_mode
1074 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1075 {
1076 return tgl_sbid_mode(unsigned(x) & unsigned(y));
1077 }
1078
1079 inline tgl_sbid_mode &
1080 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1081 {
1082 return x = x | y;
1083 }
1084
1085 #endif
1086
1087 /**
1088 * Logical representation of the SWSB scheduling information of a hardware
1089 * instruction. The binary representation is slightly more compact.
1090 */
1091 struct tgl_swsb {
1092 unsigned regdist : 3;
1093 unsigned sbid : 4;
1094 enum tgl_sbid_mode mode : 3;
1095 };
1096
1097 /**
1098 * Construct a scheduling annotation with a single RegDist dependency. This
1099 * synchronizes with the completion of the d-th previous in-order instruction.
1100 * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1101 */
1102 static inline struct tgl_swsb
tgl_swsb_regdist(unsigned d)1103 tgl_swsb_regdist(unsigned d)
1104 {
1105 const struct tgl_swsb swsb = { d };
1106 assert(swsb.regdist == d);
1107 return swsb;
1108 }
1109
1110 /**
1111 * Construct a scheduling annotation that synchronizes with the specified SBID
1112 * token.
1113 */
1114 static inline struct tgl_swsb
tgl_swsb_sbid(enum tgl_sbid_mode mode,unsigned sbid)1115 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1116 {
1117 const struct tgl_swsb swsb = { 0, sbid, mode };
1118 assert(swsb.sbid == sbid);
1119 return swsb;
1120 }
1121
1122 /**
1123 * Construct a no-op scheduling annotation.
1124 */
1125 static inline struct tgl_swsb
tgl_swsb_null(void)1126 tgl_swsb_null(void)
1127 {
1128 return tgl_swsb_regdist(0);
1129 }
1130
1131 /**
1132 * Return a scheduling annotation that allocates the same SBID synchronization
1133 * token as \p swsb. In addition it will synchronize against a previous
1134 * in-order instruction if \p regdist is non-zero.
1135 */
1136 static inline struct tgl_swsb
tgl_swsb_dst_dep(struct tgl_swsb swsb,unsigned regdist)1137 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1138 {
1139 swsb.regdist = regdist;
1140 swsb.mode = swsb.mode & TGL_SBID_SET;
1141 return swsb;
1142 }
1143
1144 /**
1145 * Return a scheduling annotation that synchronizes against the same SBID and
1146 * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1147 */
1148 static inline struct tgl_swsb
tgl_swsb_src_dep(struct tgl_swsb swsb)1149 tgl_swsb_src_dep(struct tgl_swsb swsb)
1150 {
1151 swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1152 return swsb;
1153 }
1154
1155 /**
1156 * Convert the provided tgl_swsb to the hardware's binary representation of an
1157 * SWSB annotation.
1158 */
1159 static inline uint8_t
tgl_swsb_encode(struct tgl_swsb swsb)1160 tgl_swsb_encode(struct tgl_swsb swsb)
1161 {
1162 if (!swsb.mode) {
1163 return swsb.regdist;
1164 } else if (swsb.regdist) {
1165 return 0x80 | swsb.regdist << 4 | swsb.sbid;
1166 } else {
1167 return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1168 swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1169 }
1170 }
1171
1172 /**
1173 * Convert the provided binary representation of an SWSB annotation to a
1174 * tgl_swsb.
1175 */
1176 static inline struct tgl_swsb
tgl_swsb_decode(enum opcode opcode,uint8_t x)1177 tgl_swsb_decode(enum opcode opcode, uint8_t x)
1178 {
1179 if (x & 0x80) {
1180 const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1181 (opcode == BRW_OPCODE_SEND ||
1182 opcode == BRW_OPCODE_SENDC ||
1183 opcode == BRW_OPCODE_MATH) ?
1184 TGL_SBID_SET : TGL_SBID_DST };
1185 return swsb;
1186 } else if ((x & 0x70) == 0x20) {
1187 return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1188 } else if ((x & 0x70) == 0x30) {
1189 return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1190 } else if ((x & 0x70) == 0x40) {
1191 return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1192 } else {
1193 return tgl_swsb_regdist(x & 0x7u);
1194 }
1195 }
1196
1197 enum tgl_sync_function {
1198 TGL_SYNC_NOP = 0x0,
1199 TGL_SYNC_ALLRD = 0x2,
1200 TGL_SYNC_ALLWR = 0x3,
1201 TGL_SYNC_BAR = 0xe,
1202 TGL_SYNC_HOST = 0xf
1203 };
1204
1205 /**
1206 * Message target: Shared Function ID for where to SEND a message.
1207 *
1208 * These are enumerated in the ISA reference under "send - Send Message".
1209 * In particular, see the following tables:
1210 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1211 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1212 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1213 */
1214 enum brw_message_target {
1215 BRW_SFID_NULL = 0,
1216 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1217 BRW_SFID_SAMPLER = 2,
1218 BRW_SFID_MESSAGE_GATEWAY = 3,
1219 BRW_SFID_DATAPORT_READ = 4,
1220 BRW_SFID_DATAPORT_WRITE = 5,
1221 BRW_SFID_URB = 6,
1222 BRW_SFID_THREAD_SPAWNER = 7,
1223 BRW_SFID_VME = 8,
1224
1225 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1226 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1227 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1228
1229 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1230 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1231 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1232 HSW_SFID_CRE = 13,
1233 };
1234
1235 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1236
1237 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1238 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1239 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1240
1241 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1242 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1243 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1244 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1245 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1246 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1247 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1248 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1249 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1250 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1251 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1252 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1253 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1254 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1255 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1256 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1257 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1258 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1259
1260 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1261 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1262 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1263 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1264 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1265 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1266 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1267 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1268 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1269 #define GEN5_SAMPLER_MESSAGE_LOD 9
1270 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1271 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1272 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1273 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1274 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1275 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1276 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1277 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1278 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1279 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1280 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1281 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1282 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1283
1284 /* for GEN5 only */
1285 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1286 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1287 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1288 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1289
1290 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1291 * behavior by setting bit 22 of dword 2 in the message header. */
1292 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1293 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1294
1295 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1296 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1297 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1298 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1299 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1300 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1301 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1302 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1303 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1304 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1305 (abort(), ~0))
1306
1307 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1308 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1309
1310 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1311 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1312
1313 /* This one stays the same across generations. */
1314 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1315 /* GEN4 */
1316 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1317 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1318 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1319 /* G45, GEN5 */
1320 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1321 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1322 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1323 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1324 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1325 /* GEN6 */
1326 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1327 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1328 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1329 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1330 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1331
1332 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1333 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1334 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1335
1336 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1337 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1338 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1339 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1340 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1341
1342 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1343 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1344 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1345 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1346 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1347 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1348 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1349
1350 /* GEN6 */
1351 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1352 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1353 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1354 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1355 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1356 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1357 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1358 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1359
1360 /* GEN7 */
1361 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1362 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1363 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1364 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1365 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1366 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1367 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1368 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1369 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1370 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1371 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1372 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1373 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1374 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1375 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1376 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1377 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1378 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1379 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1380 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1381
1382 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1383 (0 << 17))
1384 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1385 (1 << 17))
1386 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1387
1388 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1389 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1390 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1391 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1392
1393 /* HSW */
1394 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1395 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1396 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1397 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1398 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1399 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1400 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1401 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1402 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1403 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1404
1405 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1406 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1407 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1408 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1409 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1410 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1411 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1412 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1413 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1414 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1415 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1416 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1417 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1418 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1419 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1420 #define GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ 0x14
1421 #define GEN9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE 0x15
1422 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1423 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1424 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1425 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1426
1427 /* GEN9 */
1428 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1429 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1430
1431 /* A64 scattered message subtype */
1432 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1433 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1434 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1435 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1436
1437 /* Dataport special binding table indices: */
1438 #define BRW_BTI_STATELESS 255
1439 #define GEN7_BTI_SLM 254
1440
1441 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255
1442 #define HSW_BTI_STATELESS_NON_COHERENT 253
1443 #define HSW_BTI_STATELESS_GLOBALLY_COHERENT 252
1444 #define HSW_BTI_STATELESS_LLC_COHERENT 251
1445 #define HSW_BTI_STATELESS_L3_UNCACHED 250
1446
1447 /* The hardware docs are a bit contradictory here. On Haswell, where they
1448 * first added cache ability control, there were 5 different cache modes (see
1449 * HSW_BTI_STATELESS_* above). On Broadwell, they reduced to two:
1450 *
1451 * - IA-Coherent (BTI=255): Coherent within Gen and coherent within the
1452 * entire IA cache memory hierarchy.
1453 *
1454 * - Non-Coherent (BTI=253): Coherent within Gen, same cache type.
1455 *
1456 * Information about stateless cache coherency can be found in the "A32
1457 * Stateless" section of the "3D Media GPGPU" volume of the PRM for each
1458 * hardware generation.
1459 *
1460 * Unfortunately, the docs for MDC_STATELESS appear to have been copied and
1461 * pasted from Haswell and give the Haswell definitions for the BTI values of
1462 * 255 and 253 including a warning about accessing 253 surfaces from multiple
1463 * threads. This seems to be a copy+paste error and the definitions from the
1464 * "A32 Stateless" section should be trusted instead.
1465 *
1466 * Note that because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, CHV and at
1467 * least some pre-production steppings of SKL due to WaForceEnableNonCoherent,
1468 * HDC memory access may have been overridden by the kernel to be non-coherent
1469 * (matching the behavior of the same BTI on pre-Gen8 hardware) and BTI 255
1470 * may actually be an alias for BTI 253.
1471 */
1472 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1473 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1474 #define GEN9_BTI_BINDLESS 252
1475
1476 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1477 * (and others).
1478 */
1479 #define BRW_AOP_AND 1
1480 #define BRW_AOP_OR 2
1481 #define BRW_AOP_XOR 3
1482 #define BRW_AOP_MOV 4
1483 #define BRW_AOP_INC 5
1484 #define BRW_AOP_DEC 6
1485 #define BRW_AOP_ADD 7
1486 #define BRW_AOP_SUB 8
1487 #define BRW_AOP_REVSUB 9
1488 #define BRW_AOP_IMAX 10
1489 #define BRW_AOP_IMIN 11
1490 #define BRW_AOP_UMAX 12
1491 #define BRW_AOP_UMIN 13
1492 #define BRW_AOP_CMPWR 14
1493 #define BRW_AOP_PREDEC 15
1494
1495 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1496 #define BRW_AOP_FMAX 1
1497 #define BRW_AOP_FMIN 2
1498 #define BRW_AOP_FCMPWR 3
1499
1500 #define BRW_MATH_FUNCTION_INV 1
1501 #define BRW_MATH_FUNCTION_LOG 2
1502 #define BRW_MATH_FUNCTION_EXP 3
1503 #define BRW_MATH_FUNCTION_SQRT 4
1504 #define BRW_MATH_FUNCTION_RSQ 5
1505 #define BRW_MATH_FUNCTION_SIN 6
1506 #define BRW_MATH_FUNCTION_COS 7
1507 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1508 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1509 #define BRW_MATH_FUNCTION_POW 10
1510 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1511 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1512 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1513 #define GEN8_MATH_FUNCTION_INVM 14
1514 #define GEN8_MATH_FUNCTION_RSQRTM 15
1515
1516 #define BRW_MATH_INTEGER_UNSIGNED 0
1517 #define BRW_MATH_INTEGER_SIGNED 1
1518
1519 #define BRW_MATH_PRECISION_FULL 0
1520 #define BRW_MATH_PRECISION_PARTIAL 1
1521
1522 #define BRW_MATH_SATURATE_NONE 0
1523 #define BRW_MATH_SATURATE_SATURATE 1
1524
1525 #define BRW_MATH_DATA_VECTOR 0
1526 #define BRW_MATH_DATA_SCALAR 1
1527
1528 #define BRW_URB_OPCODE_WRITE_HWORD 0
1529 #define BRW_URB_OPCODE_WRITE_OWORD 1
1530 #define BRW_URB_OPCODE_READ_HWORD 2
1531 #define BRW_URB_OPCODE_READ_OWORD 3
1532 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1533 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1534 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1535 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1536 #define GEN8_URB_OPCODE_SIMD8_READ 8
1537
1538 #define BRW_URB_SWIZZLE_NONE 0
1539 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1540 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1541
1542 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1543 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1544 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1545 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1546 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1547 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1548 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1549 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1550 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1551 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1552 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1553 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1554
1555 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1556 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1557 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1558 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1559 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1560 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1561 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1562
1563
1564 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1565 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1566 *
1567 * Identical for VS, DS, and HS.
1568 */
1569 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1570 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1571 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1572 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1573
1574 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1575 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1576 */
1577 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1578
1579 /* GS Thread Payload
1580 */
1581
1582 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1583 * counted in multiples of 16 bytes.
1584 */
1585 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1586
1587
1588 /* R0 */
1589 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1590
1591 /* CR0.0[5:4] Floating-Point Rounding Modes
1592 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1593 */
1594
1595 #define BRW_CR0_RND_MODE_MASK 0x30
1596 #define BRW_CR0_RND_MODE_SHIFT 4
1597
1598 enum PACKED brw_rnd_mode {
1599 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1600 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1601 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1602 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1603 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1604 };
1605
1606 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1607 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1608 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1609
1610 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1611 BRW_CR0_FP32_DENORM_PRESERVE | \
1612 BRW_CR0_FP16_DENORM_PRESERVE | \
1613 BRW_CR0_RND_MODE_MASK)
1614
1615 /* MDC_DS - Data Size Message Descriptor Control Field
1616 * Skylake PRM, Volume 2d, page 129
1617 *
1618 * Specifies the number of Bytes to be read or written per Dword used at
1619 * byte_scattered read/write and byte_scaled read/write messages.
1620 */
1621 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1622 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1623 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1624
1625 #endif /* BRW_EU_DEFINES_H */
1626