1 #ifndef GEN7_MEDIA_H
2 #define GEN7_MEDIA_H
3 
4 #include <stdint.h>
5 #include "surfaceformat.h"
6 
7 #define GEN7_FLOATING_POINT_IEEE_754		0
8 #define GEN7_FLOATING_POINT_NON_IEEE_754	1
9 
10 #define GFXPIPE(Pipeline,Opcode,Subopcode) ((3 << 29) |			\
11 						((Pipeline) << 27) |	\
12 						((Opcode) << 24) |	\
13 						((Subopcode) << 16))
14 
15 #define GEN7_PIPELINE_SELECT			GFXPIPE(1, 1, 4)
16 # define PIPELINE_SELECT_3D			(0 << 0)
17 # define PIPELINE_SELECT_MEDIA			(1 << 0)
18 # define PIPELINE_SELECT_GPGPU			(2 << 0)
19 
20 #define GEN7_STATE_BASE_ADDRESS			GFXPIPE(0, 1, 1)
21 # define BASE_ADDRESS_MODIFY			(1 << 0)
22 
23 #define GEN7_MEDIA_VFE_STATE			GFXPIPE(2, 0, 0)
24 #define GEN7_MEDIA_CURBE_LOAD			GFXPIPE(2, 0, 1)
25 #define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD	GFXPIPE(2, 0, 2)
26 #define GEN7_MEDIA_OBJECT			GFXPIPE(2, 1, 0)
27 #define GEN7_GPGPU_WALKER                       GFXPIPE(2, 1, 5)
28 
29 struct gen7_interface_descriptor_data
30 {
31 	struct {
32 		uint32_t pad0:6;
33 		uint32_t kernel_start_pointer:26;
34 	} desc0;
35 
36 	struct {
37 		uint32_t pad0:7;
38 		uint32_t software_exception_enable:1;
39 		uint32_t pad1:3;
40 		uint32_t maskstack_exception_enable:1;
41 		uint32_t pad2:1;
42 		uint32_t illegal_opcode_exception_enable:1;
43 		uint32_t pad3:2;
44 		uint32_t floating_point_mode:1;
45 		uint32_t thread_priority:1;
46 		uint32_t single_program_flow:1;
47 		uint32_t pad4:13;
48 	} desc1;
49 
50 	struct {
51 		uint32_t pad0:2;
52 		uint32_t sampler_count:3;
53 		uint32_t sampler_state_pointer:27;
54 	} desc2;
55 
56 	struct {
57 		uint32_t binding_table_entry_count:5;
58 		uint32_t binding_table_pointer:27;
59 	} desc3;
60 
61 	struct {
62 		uint32_t constant_urb_entry_read_offset:16;
63 		uint32_t constant_urb_entry_read_length:16;
64 	} desc4;
65 
66 	struct {
67 		uint32_t num_threads:8;
68 		uint32_t barrier_return_byte:8;
69 		uint32_t shared_local_memory_size:5;
70 		uint32_t barrier_enable:1;
71 		uint32_t rounding_mode:2;
72 		uint32_t barrier_return_grf_offset:8;
73 	} desc5;
74 
75 	struct {
76 		uint32_t cross_thread_constant_data_read_length:8;
77 		uint32_t pad0:24;
78 	} desc6;
79 
80 	struct {
81 		uint32_t pad0;
82 	} desc7;
83 };
84 
85 struct gen7_surface_state
86 {
87     struct {
88         uint32_t cube_pos_z:1;
89         uint32_t cube_neg_z:1;
90         uint32_t cube_pos_y:1;
91         uint32_t cube_neg_y:1;
92         uint32_t cube_pos_x:1;
93         uint32_t cube_neg_x:1;
94         uint32_t pad2:2;
95         uint32_t render_cache_read_write:1;
96         uint32_t pad1:1;
97         uint32_t surface_array_spacing:1;
98         uint32_t vert_line_stride_ofs:1;
99         uint32_t vert_line_stride:1;
100         uint32_t tiled_mode:2;
101         uint32_t horizontal_alignment:1;
102         uint32_t vertical_alignment:2;
103         uint32_t surface_format:9;     /**< BRW_SURFACEFORMAT_x */
104         uint32_t pad0:1;
105         uint32_t is_array:1;
106         uint32_t surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
107     } ss0;
108 
109     struct {
110         uint32_t base_addr;
111     } ss1;
112 
113     struct {
114         uint32_t width:14;
115         uint32_t pad1:2;
116         uint32_t height:14;
117         uint32_t pad0:2;
118     } ss2;
119 
120     struct {
121         uint32_t pitch:18;
122         uint32_t pad:3;
123         uint32_t depth:11;
124     } ss3;
125 
126     struct {
127         uint32_t multisample_position_palette_index:3;
128         uint32_t num_multisamples:3;
129         uint32_t multisampled_surface_storage_format:1;
130         uint32_t render_target_view_extent:11;
131         uint32_t min_array_elt:11;
132         uint32_t rotation:2;
133         uint32_t pad0:1;
134     } ss4;
135 
136     struct {
137         uint32_t mip_count:4;
138         uint32_t min_lod:4;
139         uint32_t pad1:12;
140         uint32_t y_offset:4;
141         uint32_t pad0:1;
142         uint32_t x_offset:7;
143     } ss5;
144 
145     struct {
146         uint32_t pad; /* Multisample Control Surface stuff */
147     } ss6;
148 
149     struct {
150         uint32_t resource_min_lod:12;
151         uint32_t pad0:4;
152         uint32_t shader_chanel_select_a:3;
153         uint32_t shader_chanel_select_b:3;
154         uint32_t shader_chanel_select_g:3;
155         uint32_t shader_chanel_select_r:3;
156         uint32_t alpha_clear_color:1;
157         uint32_t blue_clear_color:1;
158         uint32_t green_clear_color:1;
159         uint32_t red_clear_color:1;
160     } ss7;
161 };
162 
163 #endif /* GEN7_MEDIA_H */
164