1# 2# Copyright (C) 2018 Red Hat 3# Copyright (C) 2014 Intel Corporation 4# 5# Permission is hereby granted, free of charge, to any person obtaining a 6# copy of this software and associated documentation files (the "Software"), 7# to deal in the Software without restriction, including without limitation 8# the rights to use, copy, modify, merge, publish, distribute, sublicense, 9# and/or sell copies of the Software, and to permit persons to whom the 10# Software is furnished to do so, subject to the following conditions: 11# 12# The above copyright notice and this permission notice (including the next 13# paragraph) shall be included in all copies or substantial portions of the 14# Software. 15# 16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22# IN THE SOFTWARE. 23# 24 25# This file defines all the available intrinsics in one place. 26# 27# The Intrinsic class corresponds one-to-one with nir_intrinsic_info 28# structure. 29 30class Intrinsic(object): 31 """Class that represents all the information about an intrinsic opcode. 32 NOTE: this must be kept in sync with nir_intrinsic_info. 33 """ 34 def __init__(self, name, src_components, dest_components, 35 indices, flags, sysval, bit_sizes): 36 """Parameters: 37 38 - name: the intrinsic name 39 - src_components: list of the number of components per src, 0 means 40 vectorized instruction with number of components given in the 41 num_components field in nir_intrinsic_instr. 42 - dest_components: number of destination components, -1 means no 43 dest, 0 means number of components given in num_components field 44 in nir_intrinsic_instr. 45 - indices: list of constant indicies 46 - flags: list of semantic flags 47 - sysval: is this a system-value intrinsic 48 - bit_sizes: allowed dest bit_sizes 49 """ 50 assert isinstance(name, str) 51 assert isinstance(src_components, list) 52 if src_components: 53 assert isinstance(src_components[0], int) 54 assert isinstance(dest_components, int) 55 assert isinstance(indices, list) 56 if indices: 57 assert isinstance(indices[0], str) 58 assert isinstance(flags, list) 59 if flags: 60 assert isinstance(flags[0], str) 61 assert isinstance(sysval, bool) 62 if bit_sizes: 63 assert isinstance(bit_sizes[0], int) 64 65 self.name = name 66 self.num_srcs = len(src_components) 67 self.src_components = src_components 68 self.has_dest = (dest_components >= 0) 69 self.dest_components = dest_components 70 self.num_indices = len(indices) 71 self.indices = indices 72 self.flags = flags 73 self.sysval = sysval 74 self.bit_sizes = bit_sizes 75 76# 77# Possible indices: 78# 79 80# A constant 'base' value that is added to an offset src: 81BASE = "NIR_INTRINSIC_BASE" 82# For store instructions, a writemask: 83WRMASK = "NIR_INTRINSIC_WRMASK" 84# The stream-id for GS emit_vertex/end_primitive intrinsics: 85STREAM_ID = "NIR_INTRINSIC_STREAM_ID" 86# The clip-plane id for load_user_clip_plane intrinsics: 87UCP_ID = "NIR_INTRINSIC_UCP_ID" 88# The amount of data, starting from BASE, that this instruction 89# may access. This is used to provide bounds if the offset is 90# not constant. 91RANGE = "NIR_INTRINSIC_RANGE" 92# The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative 93# to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't 94# have the implicit addition of a base to the offset. 95RANGE_BASE = "NIR_INTRINSIC_RANGE_BASE" 96# The vulkan descriptor set binding for vulkan_resource_index 97# intrinsic 98DESC_SET = "NIR_INTRINSIC_DESC_SET" 99# The vulkan descriptor set binding for vulkan_resource_index 100# intrinsic 101BINDING = "NIR_INTRINSIC_BINDING" 102# Component offset 103COMPONENT = "NIR_INTRINSIC_COMPONENT" 104# Column index for matrix system values 105COLUMN = "NIR_INTRINSIC_COLUMN" 106# Interpolation mode (only meaningful for FS inputs) 107INTERP_MODE = "NIR_INTRINSIC_INTERP_MODE" 108# A binary nir_op to use when performing a reduction or scan operation 109REDUCTION_OP = "NIR_INTRINSIC_REDUCTION_OP" 110# Cluster size for reduction operations 111CLUSTER_SIZE = "NIR_INTRINSIC_CLUSTER_SIZE" 112# Parameter index for a load_param intrinsic 113PARAM_IDX = "NIR_INTRINSIC_PARAM_IDX" 114# Image dimensionality for image intrinsics 115IMAGE_DIM = "NIR_INTRINSIC_IMAGE_DIM" 116# Non-zero if we are accessing an array image 117IMAGE_ARRAY = "NIR_INTRINSIC_IMAGE_ARRAY" 118# Access qualifiers for image and memory access intrinsics 119ACCESS = "NIR_INTRINSIC_ACCESS" 120DST_ACCESS = "NIR_INTRINSIC_DST_ACCESS" 121SRC_ACCESS = "NIR_INTRINSIC_SRC_ACCESS" 122# Image format for image intrinsics 123FORMAT = "NIR_INTRINSIC_FORMAT" 124# Offset or address alignment 125ALIGN_MUL = "NIR_INTRINSIC_ALIGN_MUL" 126ALIGN_OFFSET = "NIR_INTRINSIC_ALIGN_OFFSET" 127# The vulkan descriptor type for vulkan_resource_index 128DESC_TYPE = "NIR_INTRINSIC_DESC_TYPE" 129# The nir_alu_type of input data to a store or conversion 130SRC_TYPE = "NIR_INTRINSIC_SRC_TYPE" 131# The nir_alu_type of the data output from a load or conversion 132DEST_TYPE = "NIR_INTRINSIC_DEST_TYPE" 133# The swizzle mask for quad_swizzle_amd & masked_swizzle_amd 134SWIZZLE_MASK = "NIR_INTRINSIC_SWIZZLE_MASK" 135# Driver location of attribute 136DRIVER_LOCATION = "NIR_INTRINSIC_DRIVER_LOCATION" 137# Ordering and visibility of a memory operation 138MEMORY_SEMANTICS = "NIR_INTRINSIC_MEMORY_SEMANTICS" 139# Modes affected by a memory operation 140MEMORY_MODES = "NIR_INTRINSIC_MEMORY_MODES" 141# Scope of a memory operation 142MEMORY_SCOPE = "NIR_INTRINSIC_MEMORY_SCOPE" 143# Scope of a control barrier 144EXECUTION_SCOPE = "NIR_INTRINSIC_EXECUTION_SCOPE" 145IO_SEMANTICS = "NIR_INTRINSIC_IO_SEMANTICS" 146# Rounding mode for conversions 147ROUNDING_MODE = "NIR_INTRINSIC_ROUNDING_MODE" 148# Whether or not to saturate in conversions 149SATURATE = "NIR_INTRINSIC_SATURATE" 150 151# 152# Possible flags: 153# 154 155CAN_ELIMINATE = "NIR_INTRINSIC_CAN_ELIMINATE" 156CAN_REORDER = "NIR_INTRINSIC_CAN_REORDER" 157 158INTR_OPCODES = {} 159 160# Defines a new NIR intrinsic. By default, the intrinsic will have no sources 161# and no destination. 162# 163# You can set dest_comp=n to enable a destination for the intrinsic, in which 164# case it will have that many components, or =0 for "as many components as the 165# NIR destination value." 166# 167# Set src_comp=n to enable sources for the intruction. It can be an array of 168# component counts, or (for convenience) a scalar component count if there's 169# only one source. If a component count is 0, it will be as many components as 170# the intrinsic has based on the dest_comp. 171def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], 172 flags=[], sysval=False, bit_sizes=[]): 173 assert name not in INTR_OPCODES 174 INTR_OPCODES[name] = Intrinsic(name, src_comp, dest_comp, 175 indices, flags, sysval, bit_sizes) 176 177intrinsic("nop", flags=[CAN_ELIMINATE]) 178 179intrinsic("convert_alu_types", dest_comp=0, src_comp=[0], 180 indices=[SRC_TYPE, DEST_TYPE, ROUNDING_MODE, SATURATE], 181 flags=[CAN_ELIMINATE, CAN_REORDER]) 182 183intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE]) 184 185intrinsic("load_deref", dest_comp=0, src_comp=[-1], 186 indices=[ACCESS], flags=[CAN_ELIMINATE]) 187intrinsic("store_deref", src_comp=[-1, 0], indices=[WRMASK, ACCESS]) 188intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS]) 189intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS]) 190 191# Interpolation of input. The interp_deref_at* intrinsics are similar to the 192# load_var intrinsic acting on a shader input except that they interpolate the 193# input differently. The at_sample, at_offset and at_vertex intrinsics take an 194# additional source that is an integer sample id, a vec2 position offset, or a 195# vertex ID respectively. 196 197intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1], 198 flags=[ CAN_ELIMINATE, CAN_REORDER]) 199intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0, 200 flags=[CAN_ELIMINATE, CAN_REORDER]) 201intrinsic("interp_deref_at_offset", src_comp=[1, 2], dest_comp=0, 202 flags=[CAN_ELIMINATE, CAN_REORDER]) 203intrinsic("interp_deref_at_vertex", src_comp=[1, 1], dest_comp=0, 204 flags=[CAN_ELIMINATE, CAN_REORDER]) 205 206# Gets the length of an unsized array at the end of a buffer 207intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1, 208 flags=[CAN_ELIMINATE, CAN_REORDER]) 209 210# Ask the driver for the size of a given SSBO. It takes the buffer index 211# as source. 212intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, 213 flags=[CAN_ELIMINATE, CAN_REORDER]) 214intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1, 215 flags=[CAN_ELIMINATE, CAN_REORDER]) 216 217# Intrinsics which provide a run-time mode-check. Unlike the compile-time 218# mode checks, a pointer can only have exactly one mode at runtime. 219intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1, 220 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 221intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1, 222 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 223 224# a barrier is an intrinsic with no inputs/outputs but which can't be moved 225# around/optimized in general 226def barrier(name): 227 intrinsic(name) 228 229barrier("discard") 230 231# Demote fragment shader invocation to a helper invocation. Any stores to 232# memory after this instruction are suppressed and the fragment does not write 233# outputs to the framebuffer. Unlike discard, demote needs to ensure that 234# derivatives will still work for invocations that were not demoted. 235# 236# As specified by SPV_EXT_demote_to_helper_invocation. 237barrier("demote") 238intrinsic("is_helper_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 239 240# SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real". 241barrier("terminate") 242 243# A workgroup-level control barrier. Any thread which hits this barrier will 244# pause until all threads within the current workgroup have also hit the 245# barrier. For compute shaders, the workgroup is defined as the local group. 246# For tessellation control shaders, the workgroup is defined as the current 247# patch. This intrinsic does not imply any sort of memory barrier. 248barrier("control_barrier") 249 250# Memory barrier with semantics analogous to the memoryBarrier() GLSL 251# intrinsic. 252barrier("memory_barrier") 253 254# Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V 255# OpMemoryBarrier and OpControlBarrier, used to implement Vulkan Memory Model. 256# Storage that the barrier applies is represented using NIR variable modes. 257# For an OpMemoryBarrier, set EXECUTION_SCOPE to NIR_SCOPE_NONE. 258intrinsic("scoped_barrier", 259 indices=[EXECUTION_SCOPE, MEMORY_SEMANTICS, MEMORY_MODES, MEMORY_SCOPE]) 260 261# Shader clock intrinsic with semantics analogous to the clock2x32ARB() 262# GLSL intrinsic. 263# The latter can be used as code motion barrier, which is currently not 264# feasible with NIR. 265intrinsic("shader_clock", dest_comp=2, flags=[CAN_ELIMINATE], 266 indices=[MEMORY_SCOPE]) 267 268# Shader ballot intrinsics with semantics analogous to the 269# 270# ballotARB() 271# readInvocationARB() 272# readFirstInvocationARB() 273# 274# GLSL functions from ARB_shader_ballot. 275intrinsic("ballot", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 276intrinsic("read_invocation", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 277intrinsic("read_first_invocation", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 278 279# Additional SPIR-V ballot intrinsics 280# 281# These correspond to the SPIR-V opcodes 282# 283# OpGroupNonUniformElect 284# OpSubgroupFirstInvocationKHR 285intrinsic("elect", dest_comp=1, flags=[CAN_ELIMINATE]) 286intrinsic("first_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 287intrinsic("last_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 288 289# Memory barrier with semantics analogous to the compute shader 290# groupMemoryBarrier(), memoryBarrierAtomicCounter(), memoryBarrierBuffer(), 291# memoryBarrierImage() and memoryBarrierShared() GLSL intrinsics. 292barrier("group_memory_barrier") 293barrier("memory_barrier_atomic_counter") 294barrier("memory_barrier_buffer") 295barrier("memory_barrier_image") 296barrier("memory_barrier_shared") 297barrier("begin_invocation_interlock") 298barrier("end_invocation_interlock") 299 300# Memory barrier for synchronizing TCS patch outputs 301barrier("memory_barrier_tcs_patch") 302 303# A conditional discard/demote/terminate, with a single boolean source. 304intrinsic("discard_if", src_comp=[1]) 305intrinsic("demote_if", src_comp=[1]) 306intrinsic("terminate_if", src_comp=[1]) 307 308# ARB_shader_group_vote intrinsics 309intrinsic("vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 310intrinsic("vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 311intrinsic("vote_feq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 312intrinsic("vote_ieq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 313 314# Ballot ALU operations from SPIR-V. 315# 316# These operations work like their ALU counterparts except that the operate 317# on a uvec4 which is treated as a 128bit integer. Also, they are, in 318# general, free to ignore any bits which are above the subgroup size. 319intrinsic("ballot_bitfield_extract", src_comp=[4, 1], dest_comp=1, flags=[CAN_ELIMINATE]) 320intrinsic("ballot_bit_count_reduce", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 321intrinsic("ballot_bit_count_inclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 322intrinsic("ballot_bit_count_exclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 323intrinsic("ballot_find_lsb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 324intrinsic("ballot_find_msb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 325 326# Shuffle operations from SPIR-V. 327intrinsic("shuffle", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 328intrinsic("shuffle_xor", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 329intrinsic("shuffle_up", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 330intrinsic("shuffle_down", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 331 332# Quad operations from SPIR-V. 333intrinsic("quad_broadcast", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 334intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 335intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 336intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 337 338intrinsic("reduce", src_comp=[0], dest_comp=0, indices=[REDUCTION_OP, CLUSTER_SIZE], 339 flags=[CAN_ELIMINATE]) 340intrinsic("inclusive_scan", src_comp=[0], dest_comp=0, indices=[REDUCTION_OP], 341 flags=[CAN_ELIMINATE]) 342intrinsic("exclusive_scan", src_comp=[0], dest_comp=0, indices=[REDUCTION_OP], 343 flags=[CAN_ELIMINATE]) 344 345# AMD shader ballot operations 346intrinsic("quad_swizzle_amd", src_comp=[0], dest_comp=0, indices=[SWIZZLE_MASK], 347 flags=[CAN_ELIMINATE]) 348intrinsic("masked_swizzle_amd", src_comp=[0], dest_comp=0, indices=[SWIZZLE_MASK], 349 flags=[CAN_ELIMINATE]) 350intrinsic("write_invocation_amd", src_comp=[0, 0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 351intrinsic("mbcnt_amd", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 352 353# Basic Geometry Shader intrinsics. 354# 355# emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single 356# index, which is the stream ID to write to. 357# 358# end_primitive implements GLSL's EndPrimitive() built-in. 359intrinsic("emit_vertex", indices=[STREAM_ID]) 360intrinsic("end_primitive", indices=[STREAM_ID]) 361 362# Geometry Shader intrinsics with a vertex count. 363# 364# Alternatively, drivers may implement these intrinsics, and use 365# nir_lower_gs_intrinsics() to convert from the basic intrinsics. 366# 367# These contain two additional unsigned integer sources: 368# 1. The total number of vertices emitted so far. 369# 2. The number of vertices emitted for the current primitive 370# so far if we're counting, otherwise undef. 371intrinsic("emit_vertex_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 372intrinsic("end_primitive_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 373# Contains the final total vertex and primitive counts in the current GS thread. 374intrinsic("set_vertex_and_primitive_count", src_comp=[1, 1], indices=[STREAM_ID]) 375 376# Trace a ray through an acceleration structure 377# 378# This instruction has a lot of parameters: 379# 0. Acceleration Structure 380# 1. Ray Flags 381# 2. Cull Mask 382# 3. SBT Offset 383# 4. SBT Stride 384# 5. Miss shader index 385# 6. Ray Origin 386# 7. Ray Tmin 387# 8. Ray Direction 388# 9. Ray Tmax 389# 10. Payload 390intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1]) 391# src[] = { hit_t, hit_kind } 392intrinsic("report_ray_intersection", src_comp=[1, 1], dest_comp=1) 393intrinsic("ignore_ray_intersection") 394intrinsic("terminate_ray") 395# src[] = { sbt_index, payload } 396intrinsic("execute_callable", src_comp=[1, -1]) 397 398# Atomic counters 399# 400# The *_var variants take an atomic_uint nir_variable, while the other, 401# lowered, variants take a constant buffer index and register offset. 402 403def atomic(name, flags=[]): 404 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags) 405 intrinsic(name, src_comp=[1], dest_comp=1, indices=[BASE], flags=flags) 406 407def atomic2(name): 408 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1) 409 intrinsic(name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 410 411def atomic3(name): 412 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1) 413 intrinsic(name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 414 415atomic("atomic_counter_inc") 416atomic("atomic_counter_pre_dec") 417atomic("atomic_counter_post_dec") 418atomic("atomic_counter_read", flags=[CAN_ELIMINATE]) 419atomic2("atomic_counter_add") 420atomic2("atomic_counter_min") 421atomic2("atomic_counter_max") 422atomic2("atomic_counter_and") 423atomic2("atomic_counter_or") 424atomic2("atomic_counter_xor") 425atomic2("atomic_counter_exchange") 426atomic3("atomic_counter_comp_swap") 427 428# Image load, store and atomic intrinsics. 429# 430# All image intrinsics come in three versions. One which take an image target 431# passed as a deref chain as the first source, one which takes an index as the 432# first source, and one which takes a bindless handle as the first source. 433# In the first version, the image variable contains the memory and layout 434# qualifiers that influence the semantics of the intrinsic. In the second and 435# third, the image format and access qualifiers are provided as constant 436# indices. 437# 438# All image intrinsics take a four-coordinate vector and a sample index as 439# 2nd and 3rd sources, determining the location within the image that will be 440# accessed by the intrinsic. Components not applicable to the image target 441# in use are undefined. Image store takes an additional four-component 442# argument with the value to be written, and image atomic operations take 443# either one or two additional scalar arguments with the same meaning as in 444# the ARB_shader_image_load_store specification. 445def image(name, src_comp=[], extra_indices=[], **kwargs): 446 intrinsic("image_deref_" + name, src_comp=[1] + src_comp, 447 indices=[ACCESS] + extra_indices, **kwargs) 448 intrinsic("image_" + name, src_comp=[1] + src_comp, 449 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 450 intrinsic("bindless_image_" + name, src_comp=[1] + src_comp, 451 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 452 453image("load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 454image("store", src_comp=[4, 1, 0, 1], extra_indices=[SRC_TYPE]) 455image("atomic_add", src_comp=[4, 1, 1], dest_comp=1) 456image("atomic_imin", src_comp=[4, 1, 1], dest_comp=1) 457image("atomic_umin", src_comp=[4, 1, 1], dest_comp=1) 458image("atomic_imax", src_comp=[4, 1, 1], dest_comp=1) 459image("atomic_umax", src_comp=[4, 1, 1], dest_comp=1) 460image("atomic_and", src_comp=[4, 1, 1], dest_comp=1) 461image("atomic_or", src_comp=[4, 1, 1], dest_comp=1) 462image("atomic_xor", src_comp=[4, 1, 1], dest_comp=1) 463image("atomic_exchange", src_comp=[4, 1, 1], dest_comp=1) 464image("atomic_comp_swap", src_comp=[4, 1, 1, 1], dest_comp=1) 465image("atomic_fadd", src_comp=[4, 1, 1], dest_comp=1) 466image("size", dest_comp=0, src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 467image("samples", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 468image("atomic_inc_wrap", src_comp=[4, 1, 1], dest_comp=1) 469image("atomic_dec_wrap", src_comp=[4, 1, 1], dest_comp=1) 470# CL-specific format queries 471image("format", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 472image("order", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 473 474# Vulkan descriptor set intrinsics 475# 476# The Vulkan API uses a different binding model from GL. In the Vulkan 477# API, all external resources are represented by a tuple: 478# 479# (descriptor set, binding, array index) 480# 481# where the array index is the only thing allowed to be indirect. The 482# vulkan_surface_index intrinsic takes the descriptor set and binding as 483# its first two indices and the array index as its source. The third 484# index is a nir_variable_mode in case that's useful to the backend. 485# 486# The intended usage is that the shader will call vulkan_surface_index to 487# get an index and then pass that as the buffer index ubo/ssbo calls. 488# 489# The vulkan_resource_reindex intrinsic takes a resource index in src0 490# (the result of a vulkan_resource_index or vulkan_resource_reindex) which 491# corresponds to the tuple (set, binding, index) and computes an index 492# corresponding to tuple (set, binding, idx + src1). 493intrinsic("vulkan_resource_index", src_comp=[1], dest_comp=0, 494 indices=[DESC_SET, BINDING, DESC_TYPE], 495 flags=[CAN_ELIMINATE, CAN_REORDER]) 496intrinsic("vulkan_resource_reindex", src_comp=[0, 1], dest_comp=0, 497 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 498intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0, 499 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 500 501# variable atomic intrinsics 502# 503# All of these variable atomic memory operations read a value from memory, 504# compute a new value using one of the operations below, write the new value 505# to memory, and return the original value read. 506# 507# All operations take 2 sources except CompSwap that takes 3. These sources 508# represent: 509# 510# 0: A deref to the memory on which to perform the atomic 511# 1: The data parameter to the atomic function (i.e. the value to add 512# in shared_atomic_add, etc). 513# 2: For CompSwap only: the second data parameter. 514intrinsic("deref_atomic_add", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 515intrinsic("deref_atomic_imin", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 516intrinsic("deref_atomic_umin", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 517intrinsic("deref_atomic_imax", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 518intrinsic("deref_atomic_umax", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 519intrinsic("deref_atomic_and", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 520intrinsic("deref_atomic_or", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 521intrinsic("deref_atomic_xor", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 522intrinsic("deref_atomic_exchange", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 523intrinsic("deref_atomic_comp_swap", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 524intrinsic("deref_atomic_fadd", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 525intrinsic("deref_atomic_fmin", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 526intrinsic("deref_atomic_fmax", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 527intrinsic("deref_atomic_fcomp_swap", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 528 529# SSBO atomic intrinsics 530# 531# All of the SSBO atomic memory operations read a value from memory, 532# compute a new value using one of the operations below, write the new 533# value to memory, and return the original value read. 534# 535# All operations take 3 sources except CompSwap that takes 4. These 536# sources represent: 537# 538# 0: The SSBO buffer index. 539# 1: The offset into the SSBO buffer of the variable that the atomic 540# operation will operate on. 541# 2: The data parameter to the atomic function (i.e. the value to add 542# in ssbo_atomic_add, etc). 543# 3: For CompSwap only: the second data parameter. 544intrinsic("ssbo_atomic_add", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 545intrinsic("ssbo_atomic_imin", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 546intrinsic("ssbo_atomic_umin", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 547intrinsic("ssbo_atomic_imax", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 548intrinsic("ssbo_atomic_umax", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 549intrinsic("ssbo_atomic_and", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 550intrinsic("ssbo_atomic_or", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 551intrinsic("ssbo_atomic_xor", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 552intrinsic("ssbo_atomic_exchange", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 553intrinsic("ssbo_atomic_comp_swap", src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 554intrinsic("ssbo_atomic_fadd", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 555intrinsic("ssbo_atomic_fmin", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 556intrinsic("ssbo_atomic_fmax", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 557intrinsic("ssbo_atomic_fcomp_swap", src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 558 559# CS shared variable atomic intrinsics 560# 561# All of the shared variable atomic memory operations read a value from 562# memory, compute a new value using one of the operations below, write the 563# new value to memory, and return the original value read. 564# 565# All operations take 2 sources except CompSwap that takes 3. These 566# sources represent: 567# 568# 0: The offset into the shared variable storage region that the atomic 569# operation will operate on. 570# 1: The data parameter to the atomic function (i.e. the value to add 571# in shared_atomic_add, etc). 572# 2: For CompSwap only: the second data parameter. 573intrinsic("shared_atomic_add", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 574intrinsic("shared_atomic_imin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 575intrinsic("shared_atomic_umin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 576intrinsic("shared_atomic_imax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 577intrinsic("shared_atomic_umax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 578intrinsic("shared_atomic_and", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 579intrinsic("shared_atomic_or", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 580intrinsic("shared_atomic_xor", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 581intrinsic("shared_atomic_exchange", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 582intrinsic("shared_atomic_comp_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 583intrinsic("shared_atomic_fadd", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 584intrinsic("shared_atomic_fmin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 585intrinsic("shared_atomic_fmax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 586intrinsic("shared_atomic_fcomp_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 587 588# Global atomic intrinsics 589# 590# All of the shared variable atomic memory operations read a value from 591# memory, compute a new value using one of the operations below, write the 592# new value to memory, and return the original value read. 593# 594# All operations take 2 sources except CompSwap that takes 3. These 595# sources represent: 596# 597# 0: The memory address that the atomic operation will operate on. 598# 1: The data parameter to the atomic function (i.e. the value to add 599# in shared_atomic_add, etc). 600# 2: For CompSwap only: the second data parameter. 601intrinsic("global_atomic_add", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 602intrinsic("global_atomic_imin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 603intrinsic("global_atomic_umin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 604intrinsic("global_atomic_imax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 605intrinsic("global_atomic_umax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 606intrinsic("global_atomic_and", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 607intrinsic("global_atomic_or", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 608intrinsic("global_atomic_xor", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 609intrinsic("global_atomic_exchange", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 610intrinsic("global_atomic_comp_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 611intrinsic("global_atomic_fadd", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 612intrinsic("global_atomic_fmin", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 613intrinsic("global_atomic_fmax", src_comp=[1, 1], dest_comp=1, indices=[BASE]) 614intrinsic("global_atomic_fcomp_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 615 616def system_value(name, dest_comp, indices=[], bit_sizes=[32]): 617 intrinsic("load_" + name, [], dest_comp, indices, 618 flags=[CAN_ELIMINATE, CAN_REORDER], sysval=True, 619 bit_sizes=bit_sizes) 620 621system_value("frag_coord", 4) 622system_value("point_coord", 2) 623system_value("line_coord", 1) 624system_value("front_face", 1, bit_sizes=[1, 32]) 625system_value("vertex_id", 1) 626system_value("vertex_id_zero_base", 1) 627system_value("first_vertex", 1) 628system_value("is_indexed_draw", 1) 629system_value("base_vertex", 1) 630system_value("instance_id", 1) 631system_value("base_instance", 1) 632system_value("draw_id", 1) 633system_value("sample_id", 1) 634# sample_id_no_per_sample is like sample_id but does not imply per- 635# sample shading. See the lower_helper_invocation option. 636system_value("sample_id_no_per_sample", 1) 637system_value("sample_pos", 2) 638system_value("sample_mask_in", 1) 639system_value("primitive_id", 1) 640system_value("invocation_id", 1) 641system_value("tess_coord", 3) 642system_value("tess_level_outer", 4) 643system_value("tess_level_inner", 2) 644system_value("tess_level_outer_default", 4) 645system_value("tess_level_inner_default", 2) 646system_value("patch_vertices_in", 1) 647system_value("local_invocation_id", 3) 648system_value("local_invocation_index", 1) 649# zero_base indicates it starts from 0 for the current dispatch 650# non-zero_base indicates the base is included 651system_value("work_group_id", 3, bit_sizes=[32, 64]) 652system_value("work_group_id_zero_base", 3) 653system_value("base_work_group_id", 3, bit_sizes=[32, 64]) 654system_value("user_clip_plane", 4, indices=[UCP_ID]) 655system_value("num_work_groups", 3, bit_sizes=[32, 64]) 656system_value("helper_invocation", 1, bit_sizes=[1, 32]) 657system_value("layer_id", 1) 658system_value("view_index", 1) 659system_value("subgroup_size", 1) 660system_value("subgroup_invocation", 1) 661system_value("subgroup_eq_mask", 0, bit_sizes=[32, 64]) 662system_value("subgroup_ge_mask", 0, bit_sizes=[32, 64]) 663system_value("subgroup_gt_mask", 0, bit_sizes=[32, 64]) 664system_value("subgroup_le_mask", 0, bit_sizes=[32, 64]) 665system_value("subgroup_lt_mask", 0, bit_sizes=[32, 64]) 666system_value("num_subgroups", 1) 667system_value("subgroup_id", 1) 668system_value("local_group_size", 3) 669# note: the definition of global_invocation_id_zero_base is based on 670# (work_group_id * local_group_size) + local_invocation_id. 671# it is *not* based on work_group_id_zero_base, meaning the work group 672# base is already accounted for, and the global base is additive on top of that 673system_value("global_invocation_id", 3, bit_sizes=[32, 64]) 674system_value("global_invocation_id_zero_base", 3, bit_sizes=[32, 64]) 675system_value("base_global_invocation_id", 3, bit_sizes=[32, 64]) 676system_value("global_invocation_index", 1, bit_sizes=[32, 64]) 677system_value("work_dim", 1) 678system_value("line_width", 1) 679system_value("aa_line_width", 1) 680# BASE=0 for global/shader, BASE=1 for local/function 681system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE]) 682system_value("constant_base_ptr", 0, bit_sizes=[32,64]) 683system_value("shared_base_ptr", 0, bit_sizes=[32,64]) 684 685# System values for ray tracing. 686system_value("ray_launch_id", 3) 687system_value("ray_launch_size", 3) 688system_value("ray_world_origin", 3) 689system_value("ray_world_direction", 3) 690system_value("ray_object_origin", 3) 691system_value("ray_object_direction", 3) 692system_value("ray_t_min", 1) 693system_value("ray_t_max", 1) 694system_value("ray_object_to_world", 3, indices=[COLUMN]) 695system_value("ray_world_to_object", 3, indices=[COLUMN]) 696system_value("ray_hit_kind", 1) 697system_value("ray_flags", 1) 698system_value("ray_geometry_index", 1) 699system_value("ray_instance_custom_index", 1) 700system_value("shader_record_ptr", 1, bit_sizes=[64]) 701 702# Driver-specific viewport scale/offset parameters. 703# 704# VC4 and V3D need to emit a scaled version of the position in the vertex 705# shaders for binning, and having system values lets us move the math for that 706# into NIR. 707# 708# Panfrost needs to implement all coordinate transformation in the 709# vertex shader; system values allow us to share this routine in NIR. 710system_value("viewport_x_scale", 1) 711system_value("viewport_y_scale", 1) 712system_value("viewport_z_scale", 1) 713system_value("viewport_z_offset", 1) 714system_value("viewport_scale", 3) 715system_value("viewport_offset", 3) 716 717# Blend constant color values. Float values are clamped. Vectored versions are 718# provided as well for driver convenience 719 720system_value("blend_const_color_r_float", 1) 721system_value("blend_const_color_g_float", 1) 722system_value("blend_const_color_b_float", 1) 723system_value("blend_const_color_a_float", 1) 724system_value("blend_const_color_rgba", 4) 725system_value("blend_const_color_rgba8888_unorm", 1) 726system_value("blend_const_color_aaaa8888_unorm", 1) 727 728# System values for gl_Color, for radeonsi which interpolates these in the 729# shader prolog to handle two-sided color without recompiles and therefore 730# doesn't handle these in the main shader part like normal varyings. 731system_value("color0", 4) 732system_value("color1", 4) 733 734# System value for internal compute shaders in radeonsi. 735system_value("user_data_amd", 4) 736 737# Barycentric coordinate intrinsics. 738# 739# These set up the barycentric coordinates for a particular interpolation. 740# The first four are for the simple cases: pixel, centroid, per-sample 741# (at gl_SampleID), or pull model (1/W, 1/I, 1/J) at the pixel center. The next 742# three two handle interpolating at a specified sample location, or 743# interpolating with a vec2 offset, 744# 745# The interp_mode index should be either the INTERP_MODE_SMOOTH or 746# INTERP_MODE_NOPERSPECTIVE enum values. 747# 748# The vec2 value produced by these intrinsics is intended for use as the 749# barycoord source of a load_interpolated_input intrinsic. 750 751def barycentric(name, dst_comp, src_comp=[]): 752 intrinsic("load_barycentric_" + name, src_comp=src_comp, dest_comp=dst_comp, 753 indices=[INTERP_MODE], flags=[CAN_ELIMINATE, CAN_REORDER]) 754 755# no sources. 756barycentric("pixel", 2) 757barycentric("centroid", 2) 758barycentric("sample", 2) 759barycentric("model", 3) 760# src[] = { sample_id }. 761barycentric("at_sample", 2, [1]) 762# src[] = { offset.xy }. 763barycentric("at_offset", 2, [2]) 764 765# Load sample position: 766# 767# Takes a sample # and returns a sample position. Used for lowering 768# interpolateAtSample() to interpolateAtOffset() 769intrinsic("load_sample_pos_from_id", src_comp=[1], dest_comp=2, 770 flags=[CAN_ELIMINATE, CAN_REORDER]) 771 772# Loads what I believe is the primitive size, for scaling ij to pixel size: 773intrinsic("load_size_ir3", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 774 775# Fragment shader input interpolation delta intrinsic. 776# 777# For hw where fragment shader input interpolation is handled in shader, the 778# load_fs_input_interp deltas intrinsics can be used to load the input deltas 779# used for interpolation as follows: 780# 781# vec3 iid = load_fs_input_interp_deltas(varying_slot) 782# vec2 bary = load_barycentric_*(...) 783# float result = iid.x + iid.y * bary.y + iid.z * bary.x 784 785intrinsic("load_fs_input_interp_deltas", src_comp=[1], dest_comp=3, 786 indices=[BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 787 788# Load operations pull data from some piece of GPU memory. All load 789# operations operate in terms of offsets into some piece of theoretical 790# memory. Loads from externally visible memory (UBO and SSBO) simply take a 791# byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.) 792# take a base+offset pair where the nir_intrinsic_base() gives the location 793# of the start of the variable being loaded and and the offset source is a 794# offset into that variable. 795# 796# Uniform load operations have a nir_intrinsic_range() index that specifies the 797# range (starting at base) of the data from which we are loading. If 798# range == 0, then the range is unknown. 799# 800# UBO load operations have a nir_intrinsic_range_base() and 801# nir_intrinsic_range() that specify the byte range [range_base, 802# range_base+range] of the UBO that the src offset access must lie within. 803# 804# Some load operations such as UBO/SSBO load and per_vertex loads take an 805# additional source to specify which UBO/SSBO/vertex to load from. 806# 807# The exact address type depends on the lowering pass that generates the 808# load/store intrinsics. Typically, this is vec4 units for things such as 809# varying slots and float units for fragment shader inputs. UBO and SSBO 810# offsets are always in bytes. 811 812def load(name, src_comp, indices=[], flags=[]): 813 intrinsic("load_" + name, src_comp, dest_comp=0, indices=indices, 814 flags=flags) 815 816# src[] = { offset }. 817load("uniform", [1], [BASE, RANGE, DEST_TYPE], [CAN_ELIMINATE, CAN_REORDER]) 818# src[] = { buffer_index, offset }. 819load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CAN_REORDER]) 820# src[] = { buffer_index, offset in vec4 units } 821load("ubo_vec4", [-1, 1], [ACCESS, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER]) 822# src[] = { offset }. 823load("input", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 824# src[] = { vertex_id, offset }. 825load("input_vertex", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 826# src[] = { vertex, offset }. 827load("per_vertex_input", [1, 1], [BASE, COMPONENT, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 828# src[] = { barycoord, offset }. 829load("interpolated_input", [2, 1], [BASE, COMPONENT, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 830 831# src[] = { buffer_index, offset }. 832load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 833# src[] = { buffer_index } 834load("ssbo_address", [1], [], [CAN_ELIMINATE, CAN_REORDER]) 835# src[] = { offset }. 836load("output", [1], [BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 837# src[] = { vertex, offset }. 838load("per_vertex_output", [1, 1], [BASE, COMPONENT, IO_SEMANTICS], [CAN_ELIMINATE]) 839# src[] = { offset }. 840load("shared", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 841# src[] = { offset }. 842load("push_constant", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 843# src[] = { offset }. 844load("constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], 845 [CAN_ELIMINATE, CAN_REORDER]) 846# src[] = { address }. 847load("global", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 848# src[] = { address }. 849load("global_constant", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 850 [CAN_ELIMINATE, CAN_REORDER]) 851# src[] = { address }. 852load("kernel_input", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 853# src[] = { offset }. 854load("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 855 856# Stores work the same way as loads, except now the first source is the value 857# to store and the second (and possibly third) source specify where to store 858# the value. SSBO and shared memory stores also have a 859# nir_intrinsic_write_mask() 860 861def store(name, srcs, indices=[], flags=[]): 862 intrinsic("store_" + name, [0] + srcs, indices=indices, flags=flags) 863 864# src[] = { value, offset }. 865store("output", [1], [BASE, WRMASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 866# src[] = { value, vertex, offset }. 867store("per_vertex_output", [1, 1], [BASE, WRMASK, COMPONENT, IO_SEMANTICS]) 868# src[] = { value, block_index, offset } 869store("ssbo", [-1, 1], [WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 870# src[] = { value, offset }. 871store("shared", [1], [BASE, WRMASK, ALIGN_MUL, ALIGN_OFFSET]) 872# src[] = { value, address }. 873store("global", [1], [WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 874# src[] = { value, offset }. 875store("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET, WRMASK]) 876 877# IR3-specific version of most SSBO intrinsics. The only different 878# compare to the originals is that they add an extra source to hold 879# the dword-offset, which is needed by the backend code apart from 880# the byte-offset already provided by NIR in one of the sources. 881# 882# NIR lowering pass 'ir3_nir_lower_io_offset' will replace the 883# original SSBO intrinsics by these, placing the computed 884# dword-offset always in the last source. 885# 886# The float versions are not handled because those are not supported 887# by the backend. 888store("ssbo_ir3", [1, 1, 1], 889 indices=[WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 890load("ssbo_ir3", [1, 1, 1], 891 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 892intrinsic("ssbo_atomic_add_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 893intrinsic("ssbo_atomic_imin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 894intrinsic("ssbo_atomic_umin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 895intrinsic("ssbo_atomic_imax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 896intrinsic("ssbo_atomic_umax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 897intrinsic("ssbo_atomic_and_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 898intrinsic("ssbo_atomic_or_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 899intrinsic("ssbo_atomic_xor_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 900intrinsic("ssbo_atomic_exchange_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 901intrinsic("ssbo_atomic_comp_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 902 903# System values for freedreno geometry shaders. 904system_value("vs_primitive_stride_ir3", 1) 905system_value("vs_vertex_stride_ir3", 1) 906system_value("gs_header_ir3", 1) 907system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) 908 909# System values for freedreno tessellation shaders. 910system_value("hs_patch_stride_ir3", 1) 911system_value("tess_factor_base_ir3", 2) 912system_value("tess_param_base_ir3", 2) 913system_value("tcs_header_ir3", 1) 914 915# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end 916# the shader when src0 is false and is used to narrow down the TCS shader to 917# just thread 0 before writing out tessellation levels. 918intrinsic("cond_end_ir3", src_comp=[1]) 919# end_patch_ir3 is used just before thread 0 exist the TCS and presumably 920# signals the TE that the patch is complete and can be tessellated. 921intrinsic("end_patch_ir3") 922 923# IR3-specific load/store intrinsics. These access a buffer used to pass data 924# between geometry stages - perhaps it's explicit access to the vertex cache. 925 926# src[] = { value, offset }. 927store("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) 928# src[] = { offset }. 929load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 930 931# IR3-specific load/store global intrinsics. They take a 64-bit base address 932# and a 32-bit offset. The hardware will add the base and the offset, which 933# saves us from doing 64-bit math on the base address. 934 935# src[] = { value, address(vec2 of hi+lo uint32_t), offset }. 936# const_index[] = { write_mask, align_mul, align_offset } 937store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 938# src[] = { address(vec2 of hi+lo uint32_t), offset }. 939# const_index[] = { access, align_mul, align_offset } 940load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 941 942# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but 943# without the binding because the hardware expects a single flattened index 944# rather than a (binding, index) pair. We may also want to use this with GL. 945# Note that this doesn't actually turn into a HW instruction. 946intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER]) 947 948# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined 949# within a blend shader to read/write the raw value from the tile buffer, 950# without applying any format conversion in the process. If the shader needs 951# usable pixel values, it must apply format conversions itself. 952# 953# These definitions are generic, but they are explicitly vendored to prevent 954# other drivers from using them, as their semantics is defined in terms of the 955# Midgard/Bifrost hardware tile buffer and may not line up with anything sane. 956# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires 957# an sRGB->linear conversion, but linear values should be written to 958# raw_output_pan and the hardware handles linear->sRGB. 959 960# src[] = { value } 961store("raw_output_pan", [], []) 962store("combined_output_pan", [1, 1, 1], [BASE, COMPONENT, SRC_TYPE]) 963load("raw_output_pan", [1], [BASE], [CAN_ELIMINATE, CAN_REORDER]) 964 965# Loads the sampler paramaters <min_lod, max_lod, lod_bias> 966# src[] = { sampler_index } 967load("sampler_lod_parameters_pan", [1], flags=[CAN_ELIMINATE, CAN_REORDER]) 968 969# R600 specific instrincs 970# 971# location where the tesselation data is stored in LDS 972system_value("tcs_in_param_base_r600", 4) 973system_value("tcs_out_param_base_r600", 4) 974system_value("tcs_rel_patch_id_r600", 1) 975system_value("tcs_tess_factor_base_r600", 1) 976 977# load as many components as needed giving per-component addresses 978intrinsic("load_local_shared_r600", src_comp=[0], dest_comp=0, indices = [COMPONENT], flags = [CAN_ELIMINATE, CAN_REORDER]) 979 980store("local_shared_r600", [1], [WRMASK]) 981store("tf_r600", []) 982 983# V3D-specific instrinc for tile buffer color reads. 984# 985# The hardware requires that we read the samples and components of a pixel 986# in order, so we cannot eliminate or remove any loads in a sequence. 987# 988# src[] = { render_target } 989# BASE = sample index 990load("tlb_color_v3d", [1], [BASE, COMPONENT], []) 991 992# V3D-specific instrinc for per-sample tile buffer color writes. 993# 994# The driver backend needs to identify per-sample color writes and emit 995# specific code for them. 996# 997# src[] = { value, render_target } 998# BASE = sample index 999store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], []) 1000 1001# V3D-specific intrinsic to load the number of layers attached to 1002# the target framebuffer 1003intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1004 1005# Intel-specific query for loading from the brw_image_param struct passed 1006# into the shader as a uniform. The variable is a deref to the image 1007# variable. The const index specifies which of the six parameters to load. 1008intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0, 1009 indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1010image("load_raw_intel", src_comp=[1], dest_comp=0, 1011 flags=[CAN_ELIMINATE]) 1012image("store_raw_intel", src_comp=[1, 0]) 1013 1014# Number of data items being operated on for a SIMD program. 1015system_value("simd_width_intel", 1) 1016 1017# Load a relocatable 32-bit value 1018intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], 1019 indices=[PARAM_IDX], flags=[CAN_ELIMINATE, CAN_REORDER]) 1020 1021# OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. 1022intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], 1023 indices=[ACCESS], flags=[CAN_ELIMINATE]) 1024intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRMASK, ACCESS]) 1025 1026# src[] = { address }. 1027load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1028 1029# src[] = { buffer_index, offset }. 1030load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1031 1032# src[] = { offset }. 1033load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1034 1035# src[] = { value, address }. 1036store("global_block_intel", [1], [WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1037 1038# src[] = { value, block_index, offset } 1039store("ssbo_block_intel", [-1, 1], [WRMASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1040 1041# src[] = { value, offset }. 1042store("shared_block_intel", [1], [BASE, WRMASK, ALIGN_MUL, ALIGN_OFFSET]) 1043 1044