1 /*
2 * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #ifndef IR3_H_
25 #define IR3_H_
26
27 #include <stdint.h>
28 #include <stdbool.h>
29
30 #include "compiler/shader_enums.h"
31
32 #include "util/bitscan.h"
33 #include "util/list.h"
34 #include "util/set.h"
35 #include "util/u_debug.h"
36
37 #include "instr-a3xx.h"
38
39 /* low level intermediate representation of an adreno shader program */
40
41 struct ir3_compiler;
42 struct ir3;
43 struct ir3_instruction;
44 struct ir3_block;
45
46 struct ir3_info {
47 void *data; /* used internally in ir3 assembler */
48 uint16_t sizedwords;
49 uint16_t instrs_count; /* expanded to account for rpt's */
50 uint16_t nops_count; /* # of nop instructions, including nopN */
51 uint16_t mov_count;
52 uint16_t cov_count;
53 /* NOTE: max_reg, etc, does not include registers not touched
54 * by the shader (ie. vertex fetched via VFD_DECODE but not
55 * touched by shader)
56 */
57 int8_t max_reg; /* highest GPR # used by shader */
58 int8_t max_half_reg;
59 int16_t max_const;
60
61 /* number of sync bits: */
62 uint16_t ss, sy;
63
64 /* estimate of number of cycles stalled on (ss) */
65 uint16_t sstall;
66
67 uint16_t last_baryf; /* instruction # of last varying fetch */
68
69 /* Number of instructions of a given category: */
70 uint16_t instrs_per_cat[8];
71 };
72
73 struct ir3_register {
74 enum {
75 IR3_REG_CONST = 0x001,
76 IR3_REG_IMMED = 0x002,
77 IR3_REG_HALF = 0x004,
78 /* high registers are used for some things in compute shaders,
79 * for example. Seems to be for things that are global to all
80 * threads in a wave, so possibly these are global/shared by
81 * all the threads in the wave?
82 */
83 IR3_REG_HIGH = 0x008,
84 IR3_REG_RELATIV= 0x010,
85 IR3_REG_R = 0x020,
86 /* Most instructions, it seems, can do float abs/neg but not
87 * integer. The CP pass needs to know what is intended (int or
88 * float) in order to do the right thing. For this reason the
89 * abs/neg flags are split out into float and int variants. In
90 * addition, .b (bitwise) operations, the negate is actually a
91 * bitwise not, so split that out into a new flag to make it
92 * more clear.
93 */
94 IR3_REG_FNEG = 0x040,
95 IR3_REG_FABS = 0x080,
96 IR3_REG_SNEG = 0x100,
97 IR3_REG_SABS = 0x200,
98 IR3_REG_BNOT = 0x400,
99 IR3_REG_EVEN = 0x800,
100 IR3_REG_POS_INF= 0x1000,
101 /* (ei) flag, end-input? Set on last bary, presumably to signal
102 * that the shader needs no more input:
103 */
104 IR3_REG_EI = 0x2000,
105 /* meta-flags, for intermediate stages of IR, ie.
106 * before register assignment is done:
107 */
108 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */
109 IR3_REG_ARRAY = 0x8000,
110
111 } flags;
112
113 /* used for cat5 instructions, but also for internal/IR level
114 * tracking of what registers are read/written by an instruction.
115 * wrmask may be a bad name since it is used to represent both
116 * src and dst that touch multiple adjacent registers.
117 */
118 unsigned wrmask : 16; /* up to vec16 */
119
120 /* for relative addressing, 32bits for array size is too small,
121 * but otoh we don't need to deal with disjoint sets, so instead
122 * use a simple size field (number of scalar components).
123 *
124 * Note the size field isn't important for relative const (since
125 * we don't have to do register allocation for constants).
126 */
127 unsigned size : 16;
128
129 /* normal registers:
130 * the component is in the low two bits of the reg #, so
131 * rN.x becomes: (N << 2) | x
132 */
133 uint16_t num;
134 union {
135 /* immediate: */
136 int32_t iim_val;
137 uint32_t uim_val;
138 float fim_val;
139 /* relative: */
140 struct {
141 uint16_t id;
142 int16_t offset;
143 } array;
144 };
145
146 /* For IR3_REG_SSA, src registers contain ptr back to assigning
147 * instruction.
148 *
149 * For IR3_REG_ARRAY, the pointer is back to the last dependent
150 * array access (although the net effect is the same, it points
151 * back to a previous instruction that we depend on).
152 */
153 struct ir3_instruction *instr;
154 };
155
156 /*
157 * Stupid/simple growable array implementation:
158 */
159 #define DECLARE_ARRAY(type, name) \
160 unsigned name ## _count, name ## _sz; \
161 type * name;
162
163 #define array_insert(ctx, arr, val) do { \
164 if (arr ## _count == arr ## _sz) { \
165 arr ## _sz = MAX2(2 * arr ## _sz, 16); \
166 arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \
167 } \
168 arr[arr ##_count++] = val; \
169 } while (0)
170
171 struct ir3_instruction {
172 struct ir3_block *block;
173 opc_t opc;
174 enum {
175 /* (sy) flag is set on first instruction, and after sample
176 * instructions (probably just on RAW hazard).
177 */
178 IR3_INSTR_SY = 0x001,
179 /* (ss) flag is set on first instruction, and first instruction
180 * to depend on the result of "long" instructions (RAW hazard):
181 *
182 * rcp, rsq, log2, exp2, sin, cos, sqrt
183 *
184 * It seems to synchronize until all in-flight instructions are
185 * completed, for example:
186 *
187 * rsq hr1.w, hr1.w
188 * add.f hr2.z, (neg)hr2.z, hc0.y
189 * mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
190 * rsq hr2.x, hr2.x
191 * (rpt1)nop
192 * mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
193 * nop
194 * mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
195 * (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
196 * (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
197 *
198 * The last mul.f does not have (ss) set, presumably because the
199 * (ss) on the previous instruction does the job.
200 *
201 * The blob driver also seems to set it on WAR hazards, although
202 * not really clear if this is needed or just blob compiler being
203 * sloppy. So far I haven't found a case where removing the (ss)
204 * causes problems for WAR hazard, but I could just be getting
205 * lucky:
206 *
207 * rcp r1.y, r3.y
208 * (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
209 *
210 */
211 IR3_INSTR_SS = 0x002,
212 /* (jp) flag is set on jump targets:
213 */
214 IR3_INSTR_JP = 0x004,
215 IR3_INSTR_UL = 0x008,
216 IR3_INSTR_3D = 0x010,
217 IR3_INSTR_A = 0x020,
218 IR3_INSTR_O = 0x040,
219 IR3_INSTR_P = 0x080,
220 IR3_INSTR_S = 0x100,
221 IR3_INSTR_S2EN = 0x200,
222 IR3_INSTR_G = 0x400,
223 IR3_INSTR_SAT = 0x800,
224 /* (cat5/cat6) Bindless */
225 IR3_INSTR_B = 0x1000,
226 /* (cat5-only) Get some parts of the encoding from a1.x */
227 IR3_INSTR_A1EN = 0x2000,
228 /* meta-flags, for intermediate stages of IR, ie.
229 * before register assignment is done:
230 */
231 IR3_INSTR_MARK = 0x4000,
232 IR3_INSTR_UNUSED= 0x8000,
233 } flags;
234 uint8_t repeat;
235 uint8_t nop;
236 #ifdef DEBUG
237 unsigned regs_max;
238 #endif
239 unsigned regs_count;
240 struct ir3_register **regs;
241 union {
242 struct {
243 char inv;
244 char comp;
245 int immed;
246 struct ir3_block *target;
247 } cat0;
248 struct {
249 type_t src_type, dst_type;
250 } cat1;
251 struct {
252 enum {
253 IR3_COND_LT = 0,
254 IR3_COND_LE = 1,
255 IR3_COND_GT = 2,
256 IR3_COND_GE = 3,
257 IR3_COND_EQ = 4,
258 IR3_COND_NE = 5,
259 } condition;
260 } cat2;
261 struct {
262 unsigned samp, tex;
263 unsigned tex_base : 3;
264 type_t type;
265 } cat5;
266 struct {
267 type_t type;
268 int src_offset;
269 int dst_offset;
270 int iim_val : 3; /* for ldgb/stgb, # of components */
271 unsigned d : 3; /* for ldc, component offset */
272 bool typed : 1;
273 unsigned base : 3;
274 } cat6;
275 struct {
276 unsigned w : 1; /* write */
277 unsigned r : 1; /* read */
278 unsigned l : 1; /* local */
279 unsigned g : 1; /* global */
280 } cat7;
281 /* for meta-instructions, just used to hold extra data
282 * before instruction scheduling, etc
283 */
284 struct {
285 int off; /* component/offset */
286 } split;
287 struct {
288 /* for output collects, this maps back to the entry in the
289 * ir3_shader_variant::outputs table.
290 */
291 int outidx;
292 } collect;
293 struct {
294 unsigned samp, tex;
295 unsigned input_offset;
296 unsigned samp_base : 3;
297 unsigned tex_base : 3;
298 } prefetch;
299 struct {
300 /* maps back to entry in ir3_shader_variant::inputs table: */
301 int inidx;
302 /* for sysvals, identifies the sysval type. Mostly so we can
303 * identify the special cases where a sysval should not be DCE'd
304 * (currently, just pre-fs texture fetch)
305 */
306 gl_system_value sysval;
307 } input;
308 };
309
310 /* When we get to the RA stage, we need instruction's position/name: */
311 uint16_t ip;
312 uint16_t name;
313
314 /* used for per-pass extra instruction data.
315 *
316 * TODO we should remove the per-pass data like this and 'use_count'
317 * and do something similar to what RA does w/ ir3_ra_instr_data..
318 * ie. use the ir3_count_instructions pass, and then use instr->ip
319 * to index into a table of pass-private data.
320 */
321 void *data;
322
323 /**
324 * Valid if pass calls ir3_find_ssa_uses().. see foreach_ssa_use()
325 */
326 struct set *uses;
327
328 int use_count; /* currently just updated/used by cp */
329
330 /* Used during CP and RA stages. For collect and shader inputs/
331 * outputs where we need a sequence of consecutive registers,
332 * keep track of each src instructions left (ie 'n-1') and right
333 * (ie 'n+1') neighbor. The front-end must insert enough mov's
334 * to ensure that each instruction has at most one left and at
335 * most one right neighbor. During the copy-propagation pass,
336 * we only remove mov's when we can preserve this constraint.
337 * And during the RA stage, we use the neighbor information to
338 * allocate a block of registers in one shot.
339 *
340 * TODO: maybe just add something like:
341 * struct ir3_instruction_ref {
342 * struct ir3_instruction *instr;
343 * unsigned cnt;
344 * }
345 *
346 * Or can we get away without the refcnt stuff? It seems like
347 * it should be overkill.. the problem is if, potentially after
348 * already eliminating some mov's, if you have a single mov that
349 * needs to be grouped with it's neighbors in two different
350 * places (ex. shader output and a collect).
351 */
352 struct {
353 struct ir3_instruction *left, *right;
354 uint16_t left_cnt, right_cnt;
355 } cp;
356
357 /* an instruction can reference at most one address register amongst
358 * it's src/dst registers. Beyond that, you need to insert mov's.
359 *
360 * NOTE: do not write this directly, use ir3_instr_set_address()
361 */
362 struct ir3_instruction *address;
363
364 /* Tracking for additional dependent instructions. Used to handle
365 * barriers, WAR hazards for arrays/SSBOs/etc.
366 */
367 DECLARE_ARRAY(struct ir3_instruction *, deps);
368
369 /*
370 * From PoV of instruction scheduling, not execution (ie. ignores global/
371 * local distinction):
372 * shared image atomic SSBO everything
373 * barrier()/ - R/W R/W R/W R/W X
374 * groupMemoryBarrier()
375 * memoryBarrier() - R/W R/W
376 * (but only images declared coherent?)
377 * memoryBarrierAtomic() - R/W
378 * memoryBarrierBuffer() - R/W
379 * memoryBarrierImage() - R/W
380 * memoryBarrierShared() - R/W
381 *
382 * TODO I think for SSBO/image/shared, in cases where we can determine
383 * which variable is accessed, we don't need to care about accesses to
384 * different variables (unless declared coherent??)
385 */
386 enum {
387 IR3_BARRIER_EVERYTHING = 1 << 0,
388 IR3_BARRIER_SHARED_R = 1 << 1,
389 IR3_BARRIER_SHARED_W = 1 << 2,
390 IR3_BARRIER_IMAGE_R = 1 << 3,
391 IR3_BARRIER_IMAGE_W = 1 << 4,
392 IR3_BARRIER_BUFFER_R = 1 << 5,
393 IR3_BARRIER_BUFFER_W = 1 << 6,
394 IR3_BARRIER_ARRAY_R = 1 << 7,
395 IR3_BARRIER_ARRAY_W = 1 << 8,
396 } barrier_class, barrier_conflict;
397
398 /* Entry in ir3_block's instruction list: */
399 struct list_head node;
400
401 #ifdef DEBUG
402 uint32_t serialno;
403 #endif
404
405 // TODO only computerator/assembler:
406 int line;
407 };
408
409 static inline struct ir3_instruction *
ir3_neighbor_first(struct ir3_instruction * instr)410 ir3_neighbor_first(struct ir3_instruction *instr)
411 {
412 int cnt = 0;
413 while (instr->cp.left) {
414 instr = instr->cp.left;
415 if (++cnt > 0xffff) {
416 debug_assert(0);
417 break;
418 }
419 }
420 return instr;
421 }
422
ir3_neighbor_count(struct ir3_instruction * instr)423 static inline int ir3_neighbor_count(struct ir3_instruction *instr)
424 {
425 int num = 1;
426
427 debug_assert(!instr->cp.left);
428
429 while (instr->cp.right) {
430 num++;
431 instr = instr->cp.right;
432 if (num > 0xffff) {
433 debug_assert(0);
434 break;
435 }
436 }
437
438 return num;
439 }
440
441 struct ir3 {
442 struct ir3_compiler *compiler;
443 gl_shader_stage type;
444
445 DECLARE_ARRAY(struct ir3_instruction *, inputs);
446 DECLARE_ARRAY(struct ir3_instruction *, outputs);
447
448 /* Track bary.f (and ldlv) instructions.. this is needed in
449 * scheduling to ensure that all varying fetches happen before
450 * any potential kill instructions. The hw gets grumpy if all
451 * threads in a group are killed before the last bary.f gets
452 * a chance to signal end of input (ei).
453 */
454 DECLARE_ARRAY(struct ir3_instruction *, baryfs);
455
456 /* Track all indirect instructions (read and write). To avoid
457 * deadlock scenario where an address register gets scheduled,
458 * but other dependent src instructions cannot be scheduled due
459 * to dependency on a *different* address register value, the
460 * scheduler needs to ensure that all dependencies other than
461 * the instruction other than the address register are scheduled
462 * before the one that writes the address register. Having a
463 * convenient list of instructions that reference some address
464 * register simplifies this.
465 */
466 DECLARE_ARRAY(struct ir3_instruction *, a0_users);
467
468 /* same for a1.x: */
469 DECLARE_ARRAY(struct ir3_instruction *, a1_users);
470
471 /* and same for instructions that consume predicate register: */
472 DECLARE_ARRAY(struct ir3_instruction *, predicates);
473
474 /* Track texture sample instructions which need texture state
475 * patched in (for astc-srgb workaround):
476 */
477 DECLARE_ARRAY(struct ir3_instruction *, astc_srgb);
478
479 /* List of blocks: */
480 struct list_head block_list;
481
482 /* List of ir3_array's: */
483 struct list_head array_list;
484
485 #ifdef DEBUG
486 unsigned block_count, instr_count;
487 #endif
488 };
489
490 struct ir3_array {
491 struct list_head node;
492 unsigned length;
493 unsigned id;
494
495 struct nir_register *r;
496
497 /* To avoid array write's from getting DCE'd, keep track of the
498 * most recent write. Any array access depends on the most
499 * recent write. This way, nothing depends on writes after the
500 * last read. But all the writes that happen before that have
501 * something depending on them
502 */
503 struct ir3_instruction *last_write;
504
505 /* extra stuff used in RA pass: */
506 unsigned base; /* base vreg name */
507 unsigned reg; /* base physical reg */
508 uint16_t start_ip, end_ip;
509
510 /* Indicates if half-precision */
511 bool half;
512
513 bool unused;
514 };
515
516 struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
517
518 struct ir3_block {
519 struct list_head node;
520 struct ir3 *shader;
521
522 const struct nir_block *nblock;
523
524 struct list_head instr_list; /* list of ir3_instruction */
525
526 /* each block has either one or two successors.. in case of
527 * two successors, 'condition' decides which one to follow.
528 * A block preceding an if/else has two successors.
529 */
530 struct ir3_instruction *condition;
531 struct ir3_block *successors[2];
532
533 struct set *predecessors; /* set of ir3_block */
534
535 uint16_t start_ip, end_ip;
536
537 /* Track instructions which do not write a register but other-
538 * wise must not be discarded (such as kill, stg, etc)
539 */
540 DECLARE_ARRAY(struct ir3_instruction *, keeps);
541
542 /* used for per-pass extra block data. Mainly used right
543 * now in RA step to track livein/liveout.
544 */
545 void *data;
546
547 #ifdef DEBUG
548 uint32_t serialno;
549 #endif
550 };
551
552 static inline uint32_t
block_id(struct ir3_block * block)553 block_id(struct ir3_block *block)
554 {
555 #ifdef DEBUG
556 return block->serialno;
557 #else
558 return (uint32_t)(unsigned long)block;
559 #endif
560 }
561
562 struct ir3_shader_variant;
563
564 struct ir3 * ir3_create(struct ir3_compiler *compiler, struct ir3_shader_variant *v);
565 void ir3_destroy(struct ir3 *shader);
566
567 void * ir3_assemble(struct ir3_shader_variant *v);
568 void * ir3_alloc(struct ir3 *shader, int sz);
569
570 struct ir3_block * ir3_block_create(struct ir3 *shader);
571
572 struct ir3_instruction * ir3_instr_create(struct ir3_block *block, opc_t opc);
573 struct ir3_instruction * ir3_instr_create2(struct ir3_block *block,
574 opc_t opc, int nreg);
575 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
576 void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
577 const char *ir3_instr_name(struct ir3_instruction *instr);
578
579 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
580 int num, int flags);
581 struct ir3_register * ir3_reg_clone(struct ir3 *shader,
582 struct ir3_register *reg);
583
584 void ir3_instr_set_address(struct ir3_instruction *instr,
585 struct ir3_instruction *addr);
586
ir3_instr_check_mark(struct ir3_instruction * instr)587 static inline bool ir3_instr_check_mark(struct ir3_instruction *instr)
588 {
589 if (instr->flags & IR3_INSTR_MARK)
590 return true; /* already visited */
591 instr->flags |= IR3_INSTR_MARK;
592 return false;
593 }
594
595 void ir3_block_clear_mark(struct ir3_block *block);
596 void ir3_clear_mark(struct ir3 *shader);
597
598 unsigned ir3_count_instructions(struct ir3 *ir);
599 unsigned ir3_count_instructions_ra(struct ir3 *ir);
600
601 /**
602 * Move 'instr' to just before 'after'
603 */
604 static inline void
ir3_instr_move_before(struct ir3_instruction * instr,struct ir3_instruction * after)605 ir3_instr_move_before(struct ir3_instruction *instr,
606 struct ir3_instruction *after)
607 {
608 list_delinit(&instr->node);
609 list_addtail(&instr->node, &after->node);
610 }
611
612 /**
613 * Move 'instr' to just after 'before':
614 */
615 static inline void
ir3_instr_move_after(struct ir3_instruction * instr,struct ir3_instruction * before)616 ir3_instr_move_after(struct ir3_instruction *instr,
617 struct ir3_instruction *before)
618 {
619 list_delinit(&instr->node);
620 list_add(&instr->node, &before->node);
621 }
622
623 void ir3_find_ssa_uses(struct ir3 *ir, void *mem_ctx, bool falsedeps);
624
625 void ir3_set_dst_type(struct ir3_instruction *instr, bool half);
626 void ir3_fixup_src_type(struct ir3_instruction *instr);
627
628 bool ir3_valid_flags(struct ir3_instruction *instr, unsigned n, unsigned flags);
629
630 #include "util/set.h"
631 #define foreach_ssa_use(__use, __instr) \
632 for (struct ir3_instruction *__use = (void *)~0; \
633 __use && (__instr)->uses; __use = NULL) \
634 set_foreach ((__instr)->uses, __entry) \
635 if ((__use = (void *)__entry->key))
636
reg_num(struct ir3_register * reg)637 static inline uint32_t reg_num(struct ir3_register *reg)
638 {
639 return reg->num >> 2;
640 }
641
reg_comp(struct ir3_register * reg)642 static inline uint32_t reg_comp(struct ir3_register *reg)
643 {
644 return reg->num & 0x3;
645 }
646
is_flow(struct ir3_instruction * instr)647 static inline bool is_flow(struct ir3_instruction *instr)
648 {
649 return (opc_cat(instr->opc) == 0);
650 }
651
is_kill(struct ir3_instruction * instr)652 static inline bool is_kill(struct ir3_instruction *instr)
653 {
654 return instr->opc == OPC_KILL;
655 }
656
is_nop(struct ir3_instruction * instr)657 static inline bool is_nop(struct ir3_instruction *instr)
658 {
659 return instr->opc == OPC_NOP;
660 }
661
is_same_type_reg(struct ir3_register * reg1,struct ir3_register * reg2)662 static inline bool is_same_type_reg(struct ir3_register *reg1,
663 struct ir3_register *reg2)
664 {
665 unsigned type_reg1 = (reg1->flags & (IR3_REG_HIGH | IR3_REG_HALF));
666 unsigned type_reg2 = (reg2->flags & (IR3_REG_HIGH | IR3_REG_HALF));
667
668 if (type_reg1 ^ type_reg2)
669 return false;
670 else
671 return true;
672 }
673
674 /* Is it a non-transformative (ie. not type changing) mov? This can
675 * also include absneg.s/absneg.f, which for the most part can be
676 * treated as a mov (single src argument).
677 */
is_same_type_mov(struct ir3_instruction * instr)678 static inline bool is_same_type_mov(struct ir3_instruction *instr)
679 {
680 struct ir3_register *dst;
681
682 switch (instr->opc) {
683 case OPC_MOV:
684 if (instr->cat1.src_type != instr->cat1.dst_type)
685 return false;
686 /* If the type of dest reg and src reg are different,
687 * it shouldn't be considered as same type mov
688 */
689 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
690 return false;
691 break;
692 case OPC_ABSNEG_F:
693 case OPC_ABSNEG_S:
694 if (instr->flags & IR3_INSTR_SAT)
695 return false;
696 /* If the type of dest reg and src reg are different,
697 * it shouldn't be considered as same type mov
698 */
699 if (!is_same_type_reg(instr->regs[0], instr->regs[1]))
700 return false;
701 break;
702 default:
703 return false;
704 }
705
706 dst = instr->regs[0];
707
708 /* mov's that write to a0 or p0.x are special: */
709 if (dst->num == regid(REG_P0, 0))
710 return false;
711 if (reg_num(dst) == REG_A0)
712 return false;
713
714 if (dst->flags & (IR3_REG_RELATIV | IR3_REG_ARRAY))
715 return false;
716
717 return true;
718 }
719
720 /* A move from const, which changes size but not type, can also be
721 * folded into dest instruction in some cases.
722 */
is_const_mov(struct ir3_instruction * instr)723 static inline bool is_const_mov(struct ir3_instruction *instr)
724 {
725 if (instr->opc != OPC_MOV)
726 return false;
727
728 if (!(instr->regs[1]->flags & IR3_REG_CONST))
729 return false;
730
731 type_t src_type = instr->cat1.src_type;
732 type_t dst_type = instr->cat1.dst_type;
733
734 return (type_float(src_type) && type_float(dst_type)) ||
735 (type_uint(src_type) && type_uint(dst_type)) ||
736 (type_sint(src_type) && type_sint(dst_type));
737 }
738
is_alu(struct ir3_instruction * instr)739 static inline bool is_alu(struct ir3_instruction *instr)
740 {
741 return (1 <= opc_cat(instr->opc)) && (opc_cat(instr->opc) <= 3);
742 }
743
is_sfu(struct ir3_instruction * instr)744 static inline bool is_sfu(struct ir3_instruction *instr)
745 {
746 return (opc_cat(instr->opc) == 4);
747 }
748
is_tex(struct ir3_instruction * instr)749 static inline bool is_tex(struct ir3_instruction *instr)
750 {
751 return (opc_cat(instr->opc) == 5);
752 }
753
is_tex_or_prefetch(struct ir3_instruction * instr)754 static inline bool is_tex_or_prefetch(struct ir3_instruction *instr)
755 {
756 return is_tex(instr) || (instr->opc == OPC_META_TEX_PREFETCH);
757 }
758
is_mem(struct ir3_instruction * instr)759 static inline bool is_mem(struct ir3_instruction *instr)
760 {
761 return (opc_cat(instr->opc) == 6);
762 }
763
is_barrier(struct ir3_instruction * instr)764 static inline bool is_barrier(struct ir3_instruction *instr)
765 {
766 return (opc_cat(instr->opc) == 7);
767 }
768
769 static inline bool
is_half(struct ir3_instruction * instr)770 is_half(struct ir3_instruction *instr)
771 {
772 return !!(instr->regs[0]->flags & IR3_REG_HALF);
773 }
774
775 static inline bool
is_high(struct ir3_instruction * instr)776 is_high(struct ir3_instruction *instr)
777 {
778 return !!(instr->regs[0]->flags & IR3_REG_HIGH);
779 }
780
781 static inline bool
is_store(struct ir3_instruction * instr)782 is_store(struct ir3_instruction *instr)
783 {
784 /* these instructions, the "destination" register is
785 * actually a source, the address to store to.
786 */
787 switch (instr->opc) {
788 case OPC_STG:
789 case OPC_STGB:
790 case OPC_STIB:
791 case OPC_STP:
792 case OPC_STL:
793 case OPC_STLW:
794 case OPC_L2G:
795 case OPC_G2L:
796 return true;
797 default:
798 return false;
799 }
800 }
801
is_load(struct ir3_instruction * instr)802 static inline bool is_load(struct ir3_instruction *instr)
803 {
804 switch (instr->opc) {
805 case OPC_LDG:
806 case OPC_LDGB:
807 case OPC_LDIB:
808 case OPC_LDL:
809 case OPC_LDP:
810 case OPC_L2G:
811 case OPC_LDLW:
812 case OPC_LDC:
813 case OPC_LDLV:
814 /* probably some others too.. */
815 return true;
816 default:
817 return false;
818 }
819 }
820
is_input(struct ir3_instruction * instr)821 static inline bool is_input(struct ir3_instruction *instr)
822 {
823 /* in some cases, ldlv is used to fetch varying without
824 * interpolation.. fortunately inloc is the first src
825 * register in either case
826 */
827 switch (instr->opc) {
828 case OPC_LDLV:
829 case OPC_BARY_F:
830 return true;
831 default:
832 return false;
833 }
834 }
835
is_bool(struct ir3_instruction * instr)836 static inline bool is_bool(struct ir3_instruction *instr)
837 {
838 switch (instr->opc) {
839 case OPC_CMPS_F:
840 case OPC_CMPS_S:
841 case OPC_CMPS_U:
842 return true;
843 default:
844 return false;
845 }
846 }
847
848 static inline opc_t
cat3_half_opc(opc_t opc)849 cat3_half_opc(opc_t opc)
850 {
851 switch (opc) {
852 case OPC_MAD_F32: return OPC_MAD_F16;
853 case OPC_SEL_B32: return OPC_SEL_B16;
854 case OPC_SEL_S32: return OPC_SEL_S16;
855 case OPC_SEL_F32: return OPC_SEL_F16;
856 case OPC_SAD_S32: return OPC_SAD_S16;
857 default: return opc;
858 }
859 }
860
861 static inline opc_t
cat3_full_opc(opc_t opc)862 cat3_full_opc(opc_t opc)
863 {
864 switch (opc) {
865 case OPC_MAD_F16: return OPC_MAD_F32;
866 case OPC_SEL_B16: return OPC_SEL_B32;
867 case OPC_SEL_S16: return OPC_SEL_S32;
868 case OPC_SEL_F16: return OPC_SEL_F32;
869 case OPC_SAD_S16: return OPC_SAD_S32;
870 default: return opc;
871 }
872 }
873
874 static inline opc_t
cat4_half_opc(opc_t opc)875 cat4_half_opc(opc_t opc)
876 {
877 switch (opc) {
878 case OPC_RSQ: return OPC_HRSQ;
879 case OPC_LOG2: return OPC_HLOG2;
880 case OPC_EXP2: return OPC_HEXP2;
881 default: return opc;
882 }
883 }
884
885 static inline opc_t
cat4_full_opc(opc_t opc)886 cat4_full_opc(opc_t opc)
887 {
888 switch (opc) {
889 case OPC_HRSQ: return OPC_RSQ;
890 case OPC_HLOG2: return OPC_LOG2;
891 case OPC_HEXP2: return OPC_EXP2;
892 default: return opc;
893 }
894 }
895
is_meta(struct ir3_instruction * instr)896 static inline bool is_meta(struct ir3_instruction *instr)
897 {
898 return (opc_cat(instr->opc) == -1);
899 }
900
dest_regs(struct ir3_instruction * instr)901 static inline unsigned dest_regs(struct ir3_instruction *instr)
902 {
903 if ((instr->regs_count == 0) || is_store(instr) || is_flow(instr))
904 return 0;
905
906 return util_last_bit(instr->regs[0]->wrmask);
907 }
908
909 static inline bool
writes_gpr(struct ir3_instruction * instr)910 writes_gpr(struct ir3_instruction *instr)
911 {
912 if (dest_regs(instr) == 0)
913 return false;
914 /* is dest a normal temp register: */
915 struct ir3_register *reg = instr->regs[0];
916 debug_assert(!(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)));
917 if ((reg_num(reg) == REG_A0) ||
918 (reg->num == regid(REG_P0, 0)))
919 return false;
920 return true;
921 }
922
writes_addr0(struct ir3_instruction * instr)923 static inline bool writes_addr0(struct ir3_instruction *instr)
924 {
925 if (instr->regs_count > 0) {
926 struct ir3_register *dst = instr->regs[0];
927 return dst->num == regid(REG_A0, 0);
928 }
929 return false;
930 }
931
writes_addr1(struct ir3_instruction * instr)932 static inline bool writes_addr1(struct ir3_instruction *instr)
933 {
934 if (instr->regs_count > 0) {
935 struct ir3_register *dst = instr->regs[0];
936 return dst->num == regid(REG_A0, 1);
937 }
938 return false;
939 }
940
writes_pred(struct ir3_instruction * instr)941 static inline bool writes_pred(struct ir3_instruction *instr)
942 {
943 if (instr->regs_count > 0) {
944 struct ir3_register *dst = instr->regs[0];
945 return reg_num(dst) == REG_P0;
946 }
947 return false;
948 }
949
950 /* returns defining instruction for reg */
951 /* TODO better name */
ssa(struct ir3_register * reg)952 static inline struct ir3_instruction *ssa(struct ir3_register *reg)
953 {
954 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
955 return reg->instr;
956 }
957 return NULL;
958 }
959
conflicts(struct ir3_instruction * a,struct ir3_instruction * b)960 static inline bool conflicts(struct ir3_instruction *a,
961 struct ir3_instruction *b)
962 {
963 return (a && b) && (a != b);
964 }
965
reg_gpr(struct ir3_register * r)966 static inline bool reg_gpr(struct ir3_register *r)
967 {
968 if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED))
969 return false;
970 if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
971 return false;
972 return true;
973 }
974
half_type(type_t type)975 static inline type_t half_type(type_t type)
976 {
977 switch (type) {
978 case TYPE_F32: return TYPE_F16;
979 case TYPE_U32: return TYPE_U16;
980 case TYPE_S32: return TYPE_S16;
981 case TYPE_F16:
982 case TYPE_U16:
983 case TYPE_S16:
984 return type;
985 default:
986 assert(0);
987 return ~0;
988 }
989 }
990
full_type(type_t type)991 static inline type_t full_type(type_t type)
992 {
993 switch (type) {
994 case TYPE_F16: return TYPE_F32;
995 case TYPE_U16: return TYPE_U32;
996 case TYPE_S16: return TYPE_S32;
997 case TYPE_F32:
998 case TYPE_U32:
999 case TYPE_S32:
1000 return type;
1001 default:
1002 assert(0);
1003 return ~0;
1004 }
1005 }
1006
1007 /* some cat2 instructions (ie. those which are not float) can embed an
1008 * immediate:
1009 */
ir3_cat2_int(opc_t opc)1010 static inline bool ir3_cat2_int(opc_t opc)
1011 {
1012 switch (opc) {
1013 case OPC_ADD_U:
1014 case OPC_ADD_S:
1015 case OPC_SUB_U:
1016 case OPC_SUB_S:
1017 case OPC_CMPS_U:
1018 case OPC_CMPS_S:
1019 case OPC_MIN_U:
1020 case OPC_MIN_S:
1021 case OPC_MAX_U:
1022 case OPC_MAX_S:
1023 case OPC_CMPV_U:
1024 case OPC_CMPV_S:
1025 case OPC_MUL_U24:
1026 case OPC_MUL_S24:
1027 case OPC_MULL_U:
1028 case OPC_CLZ_S:
1029 case OPC_ABSNEG_S:
1030 case OPC_AND_B:
1031 case OPC_OR_B:
1032 case OPC_NOT_B:
1033 case OPC_XOR_B:
1034 case OPC_BFREV_B:
1035 case OPC_CLZ_B:
1036 case OPC_SHL_B:
1037 case OPC_SHR_B:
1038 case OPC_ASHR_B:
1039 case OPC_MGEN_B:
1040 case OPC_GETBIT_B:
1041 case OPC_CBITS_B:
1042 case OPC_BARY_F:
1043 return true;
1044
1045 default:
1046 return false;
1047 }
1048 }
1049
1050 /* map cat2 instruction to valid abs/neg flags: */
ir3_cat2_absneg(opc_t opc)1051 static inline unsigned ir3_cat2_absneg(opc_t opc)
1052 {
1053 switch (opc) {
1054 case OPC_ADD_F:
1055 case OPC_MIN_F:
1056 case OPC_MAX_F:
1057 case OPC_MUL_F:
1058 case OPC_SIGN_F:
1059 case OPC_CMPS_F:
1060 case OPC_ABSNEG_F:
1061 case OPC_CMPV_F:
1062 case OPC_FLOOR_F:
1063 case OPC_CEIL_F:
1064 case OPC_RNDNE_F:
1065 case OPC_RNDAZ_F:
1066 case OPC_TRUNC_F:
1067 case OPC_BARY_F:
1068 return IR3_REG_FABS | IR3_REG_FNEG;
1069
1070 case OPC_ADD_U:
1071 case OPC_ADD_S:
1072 case OPC_SUB_U:
1073 case OPC_SUB_S:
1074 case OPC_CMPS_U:
1075 case OPC_CMPS_S:
1076 case OPC_MIN_U:
1077 case OPC_MIN_S:
1078 case OPC_MAX_U:
1079 case OPC_MAX_S:
1080 case OPC_CMPV_U:
1081 case OPC_CMPV_S:
1082 case OPC_MUL_U24:
1083 case OPC_MUL_S24:
1084 case OPC_MULL_U:
1085 case OPC_CLZ_S:
1086 return 0;
1087
1088 case OPC_ABSNEG_S:
1089 return IR3_REG_SABS | IR3_REG_SNEG;
1090
1091 case OPC_AND_B:
1092 case OPC_OR_B:
1093 case OPC_NOT_B:
1094 case OPC_XOR_B:
1095 case OPC_BFREV_B:
1096 case OPC_CLZ_B:
1097 case OPC_SHL_B:
1098 case OPC_SHR_B:
1099 case OPC_ASHR_B:
1100 case OPC_MGEN_B:
1101 case OPC_GETBIT_B:
1102 case OPC_CBITS_B:
1103 return IR3_REG_BNOT;
1104
1105 default:
1106 return 0;
1107 }
1108 }
1109
1110 /* map cat3 instructions to valid abs/neg flags: */
ir3_cat3_absneg(opc_t opc)1111 static inline unsigned ir3_cat3_absneg(opc_t opc)
1112 {
1113 switch (opc) {
1114 case OPC_MAD_F16:
1115 case OPC_MAD_F32:
1116 case OPC_SEL_F16:
1117 case OPC_SEL_F32:
1118 return IR3_REG_FNEG;
1119
1120 case OPC_MAD_U16:
1121 case OPC_MADSH_U16:
1122 case OPC_MAD_S16:
1123 case OPC_MADSH_M16:
1124 case OPC_MAD_U24:
1125 case OPC_MAD_S24:
1126 case OPC_SEL_S16:
1127 case OPC_SEL_S32:
1128 case OPC_SAD_S16:
1129 case OPC_SAD_S32:
1130 /* neg *may* work on 3rd src.. */
1131
1132 case OPC_SEL_B16:
1133 case OPC_SEL_B32:
1134
1135 default:
1136 return 0;
1137 }
1138 }
1139
1140 #define MASK(n) ((1 << (n)) - 1)
1141
1142 /* iterator for an instructions's sources (reg), also returns src #: */
1143 #define foreach_src_n(__srcreg, __n, __instr) \
1144 if ((__instr)->regs_count) \
1145 for (struct ir3_register *__srcreg = (void *)~0; __srcreg; __srcreg = NULL) \
1146 for (unsigned __cnt = (__instr)->regs_count - 1, __n = 0; __n < __cnt; __n++) \
1147 if ((__srcreg = (__instr)->regs[__n + 1]))
1148
1149 /* iterator for an instructions's sources (reg): */
1150 #define foreach_src(__srcreg, __instr) \
1151 foreach_src_n(__srcreg, __i, __instr)
1152
__ssa_src_cnt(struct ir3_instruction * instr)1153 static inline unsigned __ssa_src_cnt(struct ir3_instruction *instr)
1154 {
1155 unsigned cnt = instr->regs_count + instr->deps_count;
1156 if (instr->address)
1157 cnt++;
1158 return cnt;
1159 }
1160
1161 static inline struct ir3_instruction **
__ssa_srcp_n(struct ir3_instruction * instr,unsigned n)1162 __ssa_srcp_n(struct ir3_instruction *instr, unsigned n)
1163 {
1164 if (n == (instr->regs_count + instr->deps_count))
1165 return &instr->address;
1166 if (n >= instr->regs_count)
1167 return &instr->deps[n - instr->regs_count];
1168 if (ssa(instr->regs[n]))
1169 return &instr->regs[n]->instr;
1170 return NULL;
1171 }
1172
__is_false_dep(struct ir3_instruction * instr,unsigned n)1173 static inline bool __is_false_dep(struct ir3_instruction *instr, unsigned n)
1174 {
1175 if (n == (instr->regs_count + instr->deps_count))
1176 return false;
1177 if (n >= instr->regs_count)
1178 return true;
1179 return false;
1180 }
1181
1182 #define foreach_ssa_srcp_n(__srcp, __n, __instr) \
1183 for (struct ir3_instruction **__srcp = (void *)~0; __srcp; __srcp = NULL) \
1184 for (unsigned __cnt = __ssa_src_cnt(__instr), __n = 0; __n < __cnt; __n++) \
1185 if ((__srcp = __ssa_srcp_n(__instr, __n)))
1186
1187 #define foreach_ssa_srcp(__srcp, __instr) \
1188 foreach_ssa_srcp_n(__srcp, __i, __instr)
1189
1190 /* iterator for an instruction's SSA sources (instr), also returns src #: */
1191 #define foreach_ssa_src_n(__srcinst, __n, __instr) \
1192 for (struct ir3_instruction *__srcinst = (void *)~0; __srcinst; __srcinst = NULL) \
1193 foreach_ssa_srcp_n(__srcp, __n, __instr) \
1194 if ((__srcinst = *__srcp))
1195
1196 /* iterator for an instruction's SSA sources (instr): */
1197 #define foreach_ssa_src(__srcinst, __instr) \
1198 foreach_ssa_src_n(__srcinst, __i, __instr)
1199
1200 /* iterators for shader inputs: */
1201 #define foreach_input_n(__ininstr, __cnt, __ir) \
1202 for (struct ir3_instruction *__ininstr = (void *)~0; __ininstr; __ininstr = NULL) \
1203 for (unsigned __cnt = 0; __cnt < (__ir)->inputs_count; __cnt++) \
1204 if ((__ininstr = (__ir)->inputs[__cnt]))
1205 #define foreach_input(__ininstr, __ir) \
1206 foreach_input_n(__ininstr, __i, __ir)
1207
1208 /* iterators for shader outputs: */
1209 #define foreach_output_n(__outinstr, __cnt, __ir) \
1210 for (struct ir3_instruction *__outinstr = (void *)~0; __outinstr; __outinstr = NULL) \
1211 for (unsigned __cnt = 0; __cnt < (__ir)->outputs_count; __cnt++) \
1212 if ((__outinstr = (__ir)->outputs[__cnt]))
1213 #define foreach_output(__outinstr, __ir) \
1214 foreach_output_n(__outinstr, __i, __ir)
1215
1216 /* iterators for instructions: */
1217 #define foreach_instr(__instr, __list) \
1218 list_for_each_entry(struct ir3_instruction, __instr, __list, node)
1219 #define foreach_instr_rev(__instr, __list) \
1220 list_for_each_entry_rev(struct ir3_instruction, __instr, __list, node)
1221 #define foreach_instr_safe(__instr, __list) \
1222 list_for_each_entry_safe(struct ir3_instruction, __instr, __list, node)
1223
1224 /* iterators for blocks: */
1225 #define foreach_block(__block, __list) \
1226 list_for_each_entry(struct ir3_block, __block, __list, node)
1227 #define foreach_block_safe(__block, __list) \
1228 list_for_each_entry_safe(struct ir3_block, __block, __list, node)
1229 #define foreach_block_rev(__block, __list) \
1230 list_for_each_entry_rev(struct ir3_block, __block, __list, node)
1231
1232 /* iterators for arrays: */
1233 #define foreach_array(__array, __list) \
1234 list_for_each_entry(struct ir3_array, __array, __list, node)
1235 #define foreach_array_safe(__array, __list) \
1236 list_for_each_entry_safe(struct ir3_array, __array, __list, node)
1237
1238 /* Check if condition is true for any src instruction.
1239 */
1240 static inline bool
check_src_cond(struct ir3_instruction * instr,bool (* cond)(struct ir3_instruction *))1241 check_src_cond(struct ir3_instruction *instr, bool (*cond)(struct ir3_instruction *))
1242 {
1243 /* Note that this is also used post-RA so skip the ssa iterator: */
1244 foreach_src (reg, instr) {
1245 struct ir3_instruction *src = reg->instr;
1246
1247 if (!src)
1248 continue;
1249
1250 /* meta:split/collect aren't real instructions, the thing that
1251 * we actually care about is *their* srcs
1252 */
1253 if ((src->opc == OPC_META_SPLIT) || (src->opc == OPC_META_COLLECT)) {
1254 if (check_src_cond(src, cond))
1255 return true;
1256 } else {
1257 if (cond(src))
1258 return true;
1259 }
1260 }
1261
1262 return false;
1263 }
1264
1265 #define IR3_PASS(ir, pass, ...) ({ \
1266 bool progress = pass(ir, ##__VA_ARGS__); \
1267 if (progress) { \
1268 ir3_debug_print(ir, "AFTER: " #pass); \
1269 ir3_validate(ir); \
1270 } \
1271 progress; \
1272 })
1273
1274 /* validate: */
1275 void ir3_validate(struct ir3 *ir);
1276
1277 /* dump: */
1278 void ir3_print(struct ir3 *ir);
1279 void ir3_print_instr(struct ir3_instruction *instr);
1280
1281 /* delay calculation: */
1282 int ir3_delayslots(struct ir3_instruction *assigner,
1283 struct ir3_instruction *consumer, unsigned n, bool soft);
1284 unsigned ir3_delay_calc(struct ir3_block *block, struct ir3_instruction *instr,
1285 bool soft, bool pred);
1286 void ir3_remove_nops(struct ir3 *ir);
1287
1288 /* dead code elimination: */
1289 struct ir3_shader_variant;
1290 bool ir3_dce(struct ir3 *ir, struct ir3_shader_variant *so);
1291
1292 /* fp16 conversion folding */
1293 bool ir3_cf(struct ir3 *ir);
1294
1295 /* copy-propagate: */
1296 bool ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
1297 bool ir3_cp_postsched(struct ir3 *ir);
1298
1299 /* group neighbors and insert mov's to resolve conflicts: */
1300 bool ir3_group(struct ir3 *ir);
1301
1302 /* scheduling: */
1303 bool ir3_sched_add_deps(struct ir3 *ir);
1304 int ir3_sched(struct ir3 *ir);
1305
1306 struct ir3_context;
1307 bool ir3_postsched(struct ir3 *ir, struct ir3_shader_variant *v);
1308
1309 bool ir3_a6xx_fixup_atomic_dests(struct ir3 *ir, struct ir3_shader_variant *so);
1310
1311 /* register assignment: */
1312 struct ir3_ra_reg_set * ir3_ra_alloc_reg_set(struct ir3_compiler *compiler, bool mergedregs);
1313 int ir3_ra(struct ir3_shader_variant *v, struct ir3_instruction **precolor, unsigned nprecolor);
1314
1315 /* legalize: */
1316 bool ir3_legalize(struct ir3 *ir, struct ir3_shader_variant *so, int *max_bary);
1317
1318 static inline bool
ir3_has_latency_to_hide(struct ir3 * ir)1319 ir3_has_latency_to_hide(struct ir3 *ir)
1320 {
1321 /* VS/GS/TCS/TESS co-exist with frag shader invocations, but we don't
1322 * know the nature of the fragment shader. Just assume it will have
1323 * latency to hide:
1324 */
1325 if (ir->type != MESA_SHADER_FRAGMENT)
1326 return true;
1327
1328 foreach_block (block, &ir->block_list) {
1329 foreach_instr (instr, &block->instr_list) {
1330 if (is_tex_or_prefetch(instr))
1331 return true;
1332
1333 if (is_load(instr)) {
1334 switch (instr->opc) {
1335 case OPC_LDLV:
1336 case OPC_LDL:
1337 case OPC_LDLW:
1338 break;
1339 default:
1340 return true;
1341 }
1342 }
1343 }
1344 }
1345
1346 return false;
1347 }
1348
1349 /* ************************************************************************* */
1350 /* instruction helpers */
1351
1352 /* creates SSA src of correct type (ie. half vs full precision) */
__ssa_src(struct ir3_instruction * instr,struct ir3_instruction * src,unsigned flags)1353 static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
1354 struct ir3_instruction *src, unsigned flags)
1355 {
1356 struct ir3_register *reg;
1357 if (src->regs[0]->flags & IR3_REG_HALF)
1358 flags |= IR3_REG_HALF;
1359 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1360 reg->instr = src;
1361 reg->wrmask = src->regs[0]->wrmask;
1362 return reg;
1363 }
1364
__ssa_dst(struct ir3_instruction * instr)1365 static inline struct ir3_register * __ssa_dst(struct ir3_instruction *instr)
1366 {
1367 struct ir3_register *reg = ir3_reg_create(instr, 0, 0);
1368 reg->flags |= IR3_REG_SSA;
1369 return reg;
1370 }
1371
1372 static inline struct ir3_instruction *
create_immed_typed(struct ir3_block * block,uint32_t val,type_t type)1373 create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
1374 {
1375 struct ir3_instruction *mov;
1376 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1377
1378 mov = ir3_instr_create(block, OPC_MOV);
1379 mov->cat1.src_type = type;
1380 mov->cat1.dst_type = type;
1381 __ssa_dst(mov)->flags |= flags;
1382 ir3_reg_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val;
1383
1384 return mov;
1385 }
1386
1387 static inline struct ir3_instruction *
create_immed(struct ir3_block * block,uint32_t val)1388 create_immed(struct ir3_block *block, uint32_t val)
1389 {
1390 return create_immed_typed(block, val, TYPE_U32);
1391 }
1392
1393 static inline struct ir3_instruction *
create_uniform_typed(struct ir3_block * block,unsigned n,type_t type)1394 create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
1395 {
1396 struct ir3_instruction *mov;
1397 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1398
1399 mov = ir3_instr_create(block, OPC_MOV);
1400 mov->cat1.src_type = type;
1401 mov->cat1.dst_type = type;
1402 __ssa_dst(mov)->flags |= flags;
1403 ir3_reg_create(mov, n, IR3_REG_CONST | flags);
1404
1405 return mov;
1406 }
1407
1408 static inline struct ir3_instruction *
create_uniform(struct ir3_block * block,unsigned n)1409 create_uniform(struct ir3_block *block, unsigned n)
1410 {
1411 return create_uniform_typed(block, n, TYPE_F32);
1412 }
1413
1414 static inline struct ir3_instruction *
create_uniform_indirect(struct ir3_block * block,int n,type_t type,struct ir3_instruction * address)1415 create_uniform_indirect(struct ir3_block *block, int n, type_t type,
1416 struct ir3_instruction *address)
1417 {
1418 struct ir3_instruction *mov;
1419
1420 mov = ir3_instr_create(block, OPC_MOV);
1421 mov->cat1.src_type = type;
1422 mov->cat1.dst_type = type;
1423 __ssa_dst(mov);
1424 ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
1425
1426 ir3_instr_set_address(mov, address);
1427
1428 return mov;
1429 }
1430
1431 static inline struct ir3_instruction *
ir3_MOV(struct ir3_block * block,struct ir3_instruction * src,type_t type)1432 ir3_MOV(struct ir3_block *block, struct ir3_instruction *src, type_t type)
1433 {
1434 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1435 unsigned flags = (type_size(type) < 32) ? IR3_REG_HALF : 0;
1436
1437 __ssa_dst(instr)->flags |= flags;
1438 if (src->regs[0]->flags & IR3_REG_ARRAY) {
1439 struct ir3_register *src_reg = __ssa_src(instr, src, IR3_REG_ARRAY);
1440 src_reg->array = src->regs[0]->array;
1441 } else {
1442 __ssa_src(instr, src, src->regs[0]->flags & IR3_REG_HIGH);
1443 }
1444 debug_assert(!(src->regs[0]->flags & IR3_REG_RELATIV));
1445 instr->cat1.src_type = type;
1446 instr->cat1.dst_type = type;
1447 return instr;
1448 }
1449
1450 static inline struct ir3_instruction *
ir3_COV(struct ir3_block * block,struct ir3_instruction * src,type_t src_type,type_t dst_type)1451 ir3_COV(struct ir3_block *block, struct ir3_instruction *src,
1452 type_t src_type, type_t dst_type)
1453 {
1454 struct ir3_instruction *instr = ir3_instr_create(block, OPC_MOV);
1455 unsigned dst_flags = (type_size(dst_type) < 32) ? IR3_REG_HALF : 0;
1456 unsigned src_flags = (type_size(src_type) < 32) ? IR3_REG_HALF : 0;
1457
1458 debug_assert((src->regs[0]->flags & IR3_REG_HALF) == src_flags);
1459
1460 __ssa_dst(instr)->flags |= dst_flags;
1461 __ssa_src(instr, src, 0);
1462 instr->cat1.src_type = src_type;
1463 instr->cat1.dst_type = dst_type;
1464 debug_assert(!(src->regs[0]->flags & IR3_REG_ARRAY));
1465 return instr;
1466 }
1467
1468 static inline struct ir3_instruction *
ir3_NOP(struct ir3_block * block)1469 ir3_NOP(struct ir3_block *block)
1470 {
1471 return ir3_instr_create(block, OPC_NOP);
1472 }
1473
1474 #define IR3_INSTR_0 0
1475
1476 #define __INSTR0(flag, name, opc) \
1477 static inline struct ir3_instruction * \
1478 ir3_##name(struct ir3_block *block) \
1479 { \
1480 struct ir3_instruction *instr = \
1481 ir3_instr_create(block, opc); \
1482 instr->flags |= flag; \
1483 return instr; \
1484 }
1485 #define INSTR0F(f, name) __INSTR0(IR3_INSTR_##f, name##_##f, OPC_##name)
1486 #define INSTR0(name) __INSTR0(0, name, OPC_##name)
1487
1488 #define __INSTR1(flag, name, opc) \
1489 static inline struct ir3_instruction * \
1490 ir3_##name(struct ir3_block *block, \
1491 struct ir3_instruction *a, unsigned aflags) \
1492 { \
1493 struct ir3_instruction *instr = \
1494 ir3_instr_create(block, opc); \
1495 __ssa_dst(instr); \
1496 __ssa_src(instr, a, aflags); \
1497 instr->flags |= flag; \
1498 return instr; \
1499 }
1500 #define INSTR1F(f, name) __INSTR1(IR3_INSTR_##f, name##_##f, OPC_##name)
1501 #define INSTR1(name) __INSTR1(0, name, OPC_##name)
1502
1503 #define __INSTR2(flag, name, opc) \
1504 static inline struct ir3_instruction * \
1505 ir3_##name(struct ir3_block *block, \
1506 struct ir3_instruction *a, unsigned aflags, \
1507 struct ir3_instruction *b, unsigned bflags) \
1508 { \
1509 struct ir3_instruction *instr = \
1510 ir3_instr_create(block, opc); \
1511 __ssa_dst(instr); \
1512 __ssa_src(instr, a, aflags); \
1513 __ssa_src(instr, b, bflags); \
1514 instr->flags |= flag; \
1515 return instr; \
1516 }
1517 #define INSTR2F(f, name) __INSTR2(IR3_INSTR_##f, name##_##f, OPC_##name)
1518 #define INSTR2(name) __INSTR2(0, name, OPC_##name)
1519
1520 #define __INSTR3(flag, name, opc) \
1521 static inline struct ir3_instruction * \
1522 ir3_##name(struct ir3_block *block, \
1523 struct ir3_instruction *a, unsigned aflags, \
1524 struct ir3_instruction *b, unsigned bflags, \
1525 struct ir3_instruction *c, unsigned cflags) \
1526 { \
1527 struct ir3_instruction *instr = \
1528 ir3_instr_create2(block, opc, 4); \
1529 __ssa_dst(instr); \
1530 __ssa_src(instr, a, aflags); \
1531 __ssa_src(instr, b, bflags); \
1532 __ssa_src(instr, c, cflags); \
1533 instr->flags |= flag; \
1534 return instr; \
1535 }
1536 #define INSTR3F(f, name) __INSTR3(IR3_INSTR_##f, name##_##f, OPC_##name)
1537 #define INSTR3(name) __INSTR3(0, name, OPC_##name)
1538
1539 #define __INSTR4(flag, name, opc) \
1540 static inline struct ir3_instruction * \
1541 ir3_##name(struct ir3_block *block, \
1542 struct ir3_instruction *a, unsigned aflags, \
1543 struct ir3_instruction *b, unsigned bflags, \
1544 struct ir3_instruction *c, unsigned cflags, \
1545 struct ir3_instruction *d, unsigned dflags) \
1546 { \
1547 struct ir3_instruction *instr = \
1548 ir3_instr_create2(block, opc, 5); \
1549 __ssa_dst(instr); \
1550 __ssa_src(instr, a, aflags); \
1551 __ssa_src(instr, b, bflags); \
1552 __ssa_src(instr, c, cflags); \
1553 __ssa_src(instr, d, dflags); \
1554 instr->flags |= flag; \
1555 return instr; \
1556 }
1557 #define INSTR4F(f, name) __INSTR4(IR3_INSTR_##f, name##_##f, OPC_##name)
1558 #define INSTR4(name) __INSTR4(0, name, OPC_##name)
1559
1560 /* cat0 instructions: */
1561 INSTR1(B)
INSTR0(JUMP)1562 INSTR0(JUMP)
1563 INSTR1(KILL)
1564 INSTR0(END)
1565 INSTR0(CHSH)
1566 INSTR0(CHMASK)
1567 INSTR1(PREDT)
1568 INSTR0(PREDF)
1569 INSTR0(PREDE)
1570
1571 /* cat2 instructions, most 2 src but some 1 src: */
1572 INSTR2(ADD_F)
1573 INSTR2(MIN_F)
1574 INSTR2(MAX_F)
1575 INSTR2(MUL_F)
1576 INSTR1(SIGN_F)
1577 INSTR2(CMPS_F)
1578 INSTR1(ABSNEG_F)
1579 INSTR2(CMPV_F)
1580 INSTR1(FLOOR_F)
1581 INSTR1(CEIL_F)
1582 INSTR1(RNDNE_F)
1583 INSTR1(RNDAZ_F)
1584 INSTR1(TRUNC_F)
1585 INSTR2(ADD_U)
1586 INSTR2(ADD_S)
1587 INSTR2(SUB_U)
1588 INSTR2(SUB_S)
1589 INSTR2(CMPS_U)
1590 INSTR2(CMPS_S)
1591 INSTR2(MIN_U)
1592 INSTR2(MIN_S)
1593 INSTR2(MAX_U)
1594 INSTR2(MAX_S)
1595 INSTR1(ABSNEG_S)
1596 INSTR2(AND_B)
1597 INSTR2(OR_B)
1598 INSTR1(NOT_B)
1599 INSTR2(XOR_B)
1600 INSTR2(CMPV_U)
1601 INSTR2(CMPV_S)
1602 INSTR2(MUL_U24)
1603 INSTR2(MUL_S24)
1604 INSTR2(MULL_U)
1605 INSTR1(BFREV_B)
1606 INSTR1(CLZ_S)
1607 INSTR1(CLZ_B)
1608 INSTR2(SHL_B)
1609 INSTR2(SHR_B)
1610 INSTR2(ASHR_B)
1611 INSTR2(BARY_F)
1612 INSTR2(MGEN_B)
1613 INSTR2(GETBIT_B)
1614 INSTR1(SETRM)
1615 INSTR1(CBITS_B)
1616 INSTR2(SHB)
1617 INSTR2(MSAD)
1618
1619 /* cat3 instructions: */
1620 INSTR3(MAD_U16)
1621 INSTR3(MADSH_U16)
1622 INSTR3(MAD_S16)
1623 INSTR3(MADSH_M16)
1624 INSTR3(MAD_U24)
1625 INSTR3(MAD_S24)
1626 INSTR3(MAD_F16)
1627 INSTR3(MAD_F32)
1628 /* NOTE: SEL_B32 checks for zero vs nonzero */
1629 INSTR3(SEL_B16)
1630 INSTR3(SEL_B32)
1631 INSTR3(SEL_S16)
1632 INSTR3(SEL_S32)
1633 INSTR3(SEL_F16)
1634 INSTR3(SEL_F32)
1635 INSTR3(SAD_S16)
1636 INSTR3(SAD_S32)
1637
1638 /* cat4 instructions: */
1639 INSTR1(RCP)
1640 INSTR1(RSQ)
1641 INSTR1(HRSQ)
1642 INSTR1(LOG2)
1643 INSTR1(HLOG2)
1644 INSTR1(EXP2)
1645 INSTR1(HEXP2)
1646 INSTR1(SIN)
1647 INSTR1(COS)
1648 INSTR1(SQRT)
1649
1650 /* cat5 instructions: */
1651 INSTR1(DSX)
1652 INSTR1(DSXPP_MACRO)
1653 INSTR1(DSY)
1654 INSTR1(DSYPP_MACRO)
1655 INSTR1F(3D, DSX)
1656 INSTR1F(3D, DSY)
1657 INSTR1(RGETPOS)
1658
1659 static inline struct ir3_instruction *
1660 ir3_SAM(struct ir3_block *block, opc_t opc, type_t type,
1661 unsigned wrmask, unsigned flags, struct ir3_instruction *samp_tex,
1662 struct ir3_instruction *src0, struct ir3_instruction *src1)
1663 {
1664 struct ir3_instruction *sam;
1665
1666 sam = ir3_instr_create(block, opc);
1667 sam->flags |= flags;
1668 __ssa_dst(sam)->wrmask = wrmask;
1669 if (flags & IR3_INSTR_S2EN) {
1670 __ssa_src(sam, samp_tex, (flags & IR3_INSTR_B) ? 0 : IR3_REG_HALF);
1671 }
1672 if (src0) {
1673 __ssa_src(sam, src0, 0);
1674 }
1675 if (src1) {
1676 __ssa_src(sam, src1, 0);
1677 }
1678 sam->cat5.type = type;
1679
1680 return sam;
1681 }
1682
1683 /* cat6 instructions: */
1684 INSTR2(LDLV)
1685 INSTR3(LDG)
1686 INSTR3(LDL)
1687 INSTR3(LDLW)
1688 INSTR3(STG)
1689 INSTR3(STL)
1690 INSTR3(STLW)
1691 INSTR1(RESINFO)
1692 INSTR1(RESFMT)
1693 INSTR2(ATOMIC_ADD)
1694 INSTR2(ATOMIC_SUB)
1695 INSTR2(ATOMIC_XCHG)
1696 INSTR2(ATOMIC_INC)
1697 INSTR2(ATOMIC_DEC)
1698 INSTR2(ATOMIC_CMPXCHG)
1699 INSTR2(ATOMIC_MIN)
1700 INSTR2(ATOMIC_MAX)
1701 INSTR2(ATOMIC_AND)
1702 INSTR2(ATOMIC_OR)
1703 INSTR2(ATOMIC_XOR)
1704 INSTR2(LDC)
1705 #if GPU >= 600
1706 INSTR3(STIB);
1707 INSTR2(LDIB);
1708 INSTR3F(G, ATOMIC_ADD)
1709 INSTR3F(G, ATOMIC_SUB)
1710 INSTR3F(G, ATOMIC_XCHG)
1711 INSTR3F(G, ATOMIC_INC)
1712 INSTR3F(G, ATOMIC_DEC)
1713 INSTR3F(G, ATOMIC_CMPXCHG)
1714 INSTR3F(G, ATOMIC_MIN)
1715 INSTR3F(G, ATOMIC_MAX)
1716 INSTR3F(G, ATOMIC_AND)
1717 INSTR3F(G, ATOMIC_OR)
1718 INSTR3F(G, ATOMIC_XOR)
1719 #elif GPU >= 400
1720 INSTR3(LDGB)
1721 INSTR4(STGB)
1722 INSTR4(STIB)
1723 INSTR4F(G, ATOMIC_ADD)
1724 INSTR4F(G, ATOMIC_SUB)
1725 INSTR4F(G, ATOMIC_XCHG)
1726 INSTR4F(G, ATOMIC_INC)
1727 INSTR4F(G, ATOMIC_DEC)
1728 INSTR4F(G, ATOMIC_CMPXCHG)
1729 INSTR4F(G, ATOMIC_MIN)
1730 INSTR4F(G, ATOMIC_MAX)
1731 INSTR4F(G, ATOMIC_AND)
1732 INSTR4F(G, ATOMIC_OR)
1733 INSTR4F(G, ATOMIC_XOR)
1734 #endif
1735
1736 INSTR4F(G, STG)
1737
1738 /* cat7 instructions: */
1739 INSTR0(BAR)
1740 INSTR0(FENCE)
1741
1742 /* meta instructions: */
1743 INSTR0(META_TEX_PREFETCH);
1744
1745 /* ************************************************************************* */
1746 #include "regmask.h"
1747
regmask_set(regmask_t * regmask,struct ir3_register * reg)1748 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
1749 {
1750 bool half = reg->flags & IR3_REG_HALF;
1751 if (reg->flags & IR3_REG_RELATIV) {
1752 for (unsigned i = 0; i < reg->size; i++)
1753 __regmask_set(regmask, half, reg->array.offset + i);
1754 } else {
1755 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++)
1756 if (mask & 1)
1757 __regmask_set(regmask, half, n);
1758 }
1759 }
1760
regmask_get(regmask_t * regmask,struct ir3_register * reg)1761 static inline bool regmask_get(regmask_t *regmask,
1762 struct ir3_register *reg)
1763 {
1764 bool half = reg->flags & IR3_REG_HALF;
1765 if (reg->flags & IR3_REG_RELATIV) {
1766 for (unsigned i = 0; i < reg->size; i++)
1767 if (__regmask_get(regmask, half, reg->array.offset + i))
1768 return true;
1769 } else {
1770 for (unsigned mask = reg->wrmask, n = reg->num; mask; mask >>= 1, n++)
1771 if (mask & 1)
1772 if (__regmask_get(regmask, half, n))
1773 return true;
1774 }
1775 return false;
1776 }
1777 /* ************************************************************************* */
1778
1779 #endif /* IR3_H_ */
1780