1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47 #include "util/format/u_format.h"
48
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52
53 struct gen_device_info;
54 struct brw_image_param;
55
56 #ifndef ISL_DEV_GEN
57 /**
58 * @brief Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 */
63 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
64 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #else
66 #define ISL_DEV_GEN_SANITIZE(__dev) \
67 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
68 #endif
69
70 #ifndef ISL_DEV_IS_G4X
71 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
72 #endif
73
74 #ifndef ISL_DEV_IS_HASWELL
75 /**
76 * @brief Get the hardware generation of isl_device.
77 *
78 * You can define this as a compile-time constant in the CFLAGS. For example,
79 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 */
81 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
82 #endif
83
84 #ifndef ISL_DEV_IS_BAYTRAIL
85 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
86 #endif
87
88 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 /**
90 * You can define this as a compile-time constant in the CFLAGS. For example,
91 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 */
93 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #else
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
97 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
98 #endif
99
100 /**
101 * Hardware enumeration SURFACE_FORMAT.
102 *
103 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
104 * Enumerations: SURFACE_FORMAT.
105 */
106 enum isl_format {
107 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
108 ISL_FORMAT_R32G32B32A32_SINT = 1,
109 ISL_FORMAT_R32G32B32A32_UINT = 2,
110 ISL_FORMAT_R32G32B32A32_UNORM = 3,
111 ISL_FORMAT_R32G32B32A32_SNORM = 4,
112 ISL_FORMAT_R64G64_FLOAT = 5,
113 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
114 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
115 ISL_FORMAT_R32G32B32A32_USCALED = 8,
116 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
117 ISL_FORMAT_R64G64_PASSTHRU = 33,
118 ISL_FORMAT_R32G32B32_FLOAT = 64,
119 ISL_FORMAT_R32G32B32_SINT = 65,
120 ISL_FORMAT_R32G32B32_UINT = 66,
121 ISL_FORMAT_R32G32B32_UNORM = 67,
122 ISL_FORMAT_R32G32B32_SNORM = 68,
123 ISL_FORMAT_R32G32B32_SSCALED = 69,
124 ISL_FORMAT_R32G32B32_USCALED = 70,
125 ISL_FORMAT_R32G32B32_SFIXED = 80,
126 ISL_FORMAT_R16G16B16A16_UNORM = 128,
127 ISL_FORMAT_R16G16B16A16_SNORM = 129,
128 ISL_FORMAT_R16G16B16A16_SINT = 130,
129 ISL_FORMAT_R16G16B16A16_UINT = 131,
130 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
131 ISL_FORMAT_R32G32_FLOAT = 133,
132 ISL_FORMAT_R32G32_SINT = 134,
133 ISL_FORMAT_R32G32_UINT = 135,
134 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
135 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
136 ISL_FORMAT_L32A32_FLOAT = 138,
137 ISL_FORMAT_R32G32_UNORM = 139,
138 ISL_FORMAT_R32G32_SNORM = 140,
139 ISL_FORMAT_R64_FLOAT = 141,
140 ISL_FORMAT_R16G16B16X16_UNORM = 142,
141 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
142 ISL_FORMAT_A32X32_FLOAT = 144,
143 ISL_FORMAT_L32X32_FLOAT = 145,
144 ISL_FORMAT_I32X32_FLOAT = 146,
145 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
146 ISL_FORMAT_R16G16B16A16_USCALED = 148,
147 ISL_FORMAT_R32G32_SSCALED = 149,
148 ISL_FORMAT_R32G32_USCALED = 150,
149 ISL_FORMAT_R32G32_FLOAT_LD = 151,
150 ISL_FORMAT_R32G32_SFIXED = 160,
151 ISL_FORMAT_R64_PASSTHRU = 161,
152 ISL_FORMAT_B8G8R8A8_UNORM = 192,
153 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
154 ISL_FORMAT_R10G10B10A2_UNORM = 194,
155 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
156 ISL_FORMAT_R10G10B10A2_UINT = 196,
157 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
158 ISL_FORMAT_R8G8B8A8_UNORM = 199,
159 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
160 ISL_FORMAT_R8G8B8A8_SNORM = 201,
161 ISL_FORMAT_R8G8B8A8_SINT = 202,
162 ISL_FORMAT_R8G8B8A8_UINT = 203,
163 ISL_FORMAT_R16G16_UNORM = 204,
164 ISL_FORMAT_R16G16_SNORM = 205,
165 ISL_FORMAT_R16G16_SINT = 206,
166 ISL_FORMAT_R16G16_UINT = 207,
167 ISL_FORMAT_R16G16_FLOAT = 208,
168 ISL_FORMAT_B10G10R10A2_UNORM = 209,
169 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
170 ISL_FORMAT_R11G11B10_FLOAT = 211,
171 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
172 ISL_FORMAT_R32_SINT = 214,
173 ISL_FORMAT_R32_UINT = 215,
174 ISL_FORMAT_R32_FLOAT = 216,
175 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
176 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
177 ISL_FORMAT_L32_UNORM = 221,
178 ISL_FORMAT_A32_UNORM = 222,
179 ISL_FORMAT_L16A16_UNORM = 223,
180 ISL_FORMAT_I24X8_UNORM = 224,
181 ISL_FORMAT_L24X8_UNORM = 225,
182 ISL_FORMAT_A24X8_UNORM = 226,
183 ISL_FORMAT_I32_FLOAT = 227,
184 ISL_FORMAT_L32_FLOAT = 228,
185 ISL_FORMAT_A32_FLOAT = 229,
186 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
187 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
188 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
189 ISL_FORMAT_B8G8R8X8_UNORM = 233,
190 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
191 ISL_FORMAT_R8G8B8X8_UNORM = 235,
192 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
193 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
194 ISL_FORMAT_B10G10R10X2_UNORM = 238,
195 ISL_FORMAT_L16A16_FLOAT = 240,
196 ISL_FORMAT_R32_UNORM = 241,
197 ISL_FORMAT_R32_SNORM = 242,
198 ISL_FORMAT_R10G10B10X2_USCALED = 243,
199 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
200 ISL_FORMAT_R8G8B8A8_USCALED = 245,
201 ISL_FORMAT_R16G16_SSCALED = 246,
202 ISL_FORMAT_R16G16_USCALED = 247,
203 ISL_FORMAT_R32_SSCALED = 248,
204 ISL_FORMAT_R32_USCALED = 249,
205 ISL_FORMAT_B5G6R5_UNORM = 256,
206 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
207 ISL_FORMAT_B5G5R5A1_UNORM = 258,
208 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
209 ISL_FORMAT_B4G4R4A4_UNORM = 260,
210 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
211 ISL_FORMAT_R8G8_UNORM = 262,
212 ISL_FORMAT_R8G8_SNORM = 263,
213 ISL_FORMAT_R8G8_SINT = 264,
214 ISL_FORMAT_R8G8_UINT = 265,
215 ISL_FORMAT_R16_UNORM = 266,
216 ISL_FORMAT_R16_SNORM = 267,
217 ISL_FORMAT_R16_SINT = 268,
218 ISL_FORMAT_R16_UINT = 269,
219 ISL_FORMAT_R16_FLOAT = 270,
220 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
221 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
222 ISL_FORMAT_I16_UNORM = 273,
223 ISL_FORMAT_L16_UNORM = 274,
224 ISL_FORMAT_A16_UNORM = 275,
225 ISL_FORMAT_L8A8_UNORM = 276,
226 ISL_FORMAT_I16_FLOAT = 277,
227 ISL_FORMAT_L16_FLOAT = 278,
228 ISL_FORMAT_A16_FLOAT = 279,
229 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
230 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
231 ISL_FORMAT_B5G5R5X1_UNORM = 282,
232 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
233 ISL_FORMAT_R8G8_SSCALED = 284,
234 ISL_FORMAT_R8G8_USCALED = 285,
235 ISL_FORMAT_R16_SSCALED = 286,
236 ISL_FORMAT_R16_USCALED = 287,
237 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
238 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
239 ISL_FORMAT_A1B5G5R5_UNORM = 292,
240 ISL_FORMAT_A4B4G4R4_UNORM = 293,
241 ISL_FORMAT_L8A8_UINT = 294,
242 ISL_FORMAT_L8A8_SINT = 295,
243 ISL_FORMAT_R8_UNORM = 320,
244 ISL_FORMAT_R8_SNORM = 321,
245 ISL_FORMAT_R8_SINT = 322,
246 ISL_FORMAT_R8_UINT = 323,
247 ISL_FORMAT_A8_UNORM = 324,
248 ISL_FORMAT_I8_UNORM = 325,
249 ISL_FORMAT_L8_UNORM = 326,
250 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
251 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
252 ISL_FORMAT_R8_SSCALED = 329,
253 ISL_FORMAT_R8_USCALED = 330,
254 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
255 ISL_FORMAT_L8_UNORM_SRGB = 332,
256 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
257 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
258 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
259 ISL_FORMAT_Y8_UNORM = 336,
260 ISL_FORMAT_L8_UINT = 338,
261 ISL_FORMAT_L8_SINT = 339,
262 ISL_FORMAT_I8_UINT = 340,
263 ISL_FORMAT_I8_SINT = 341,
264 ISL_FORMAT_DXT1_RGB_SRGB = 384,
265 ISL_FORMAT_R1_UNORM = 385,
266 ISL_FORMAT_YCRCB_NORMAL = 386,
267 ISL_FORMAT_YCRCB_SWAPUVY = 387,
268 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
269 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
270 ISL_FORMAT_BC1_UNORM = 390,
271 ISL_FORMAT_BC2_UNORM = 391,
272 ISL_FORMAT_BC3_UNORM = 392,
273 ISL_FORMAT_BC4_UNORM = 393,
274 ISL_FORMAT_BC5_UNORM = 394,
275 ISL_FORMAT_BC1_UNORM_SRGB = 395,
276 ISL_FORMAT_BC2_UNORM_SRGB = 396,
277 ISL_FORMAT_BC3_UNORM_SRGB = 397,
278 ISL_FORMAT_MONO8 = 398,
279 ISL_FORMAT_YCRCB_SWAPUV = 399,
280 ISL_FORMAT_YCRCB_SWAPY = 400,
281 ISL_FORMAT_DXT1_RGB = 401,
282 ISL_FORMAT_FXT1 = 402,
283 ISL_FORMAT_R8G8B8_UNORM = 403,
284 ISL_FORMAT_R8G8B8_SNORM = 404,
285 ISL_FORMAT_R8G8B8_SSCALED = 405,
286 ISL_FORMAT_R8G8B8_USCALED = 406,
287 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
288 ISL_FORMAT_R64G64B64_FLOAT = 408,
289 ISL_FORMAT_BC4_SNORM = 409,
290 ISL_FORMAT_BC5_SNORM = 410,
291 ISL_FORMAT_R16G16B16_FLOAT = 411,
292 ISL_FORMAT_R16G16B16_UNORM = 412,
293 ISL_FORMAT_R16G16B16_SNORM = 413,
294 ISL_FORMAT_R16G16B16_SSCALED = 414,
295 ISL_FORMAT_R16G16B16_USCALED = 415,
296 ISL_FORMAT_BC6H_SF16 = 417,
297 ISL_FORMAT_BC7_UNORM = 418,
298 ISL_FORMAT_BC7_UNORM_SRGB = 419,
299 ISL_FORMAT_BC6H_UF16 = 420,
300 ISL_FORMAT_PLANAR_420_8 = 421,
301 ISL_FORMAT_PLANAR_420_16 = 422,
302 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
303 ISL_FORMAT_ETC1_RGB8 = 425,
304 ISL_FORMAT_ETC2_RGB8 = 426,
305 ISL_FORMAT_EAC_R11 = 427,
306 ISL_FORMAT_EAC_RG11 = 428,
307 ISL_FORMAT_EAC_SIGNED_R11 = 429,
308 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
309 ISL_FORMAT_ETC2_SRGB8 = 431,
310 ISL_FORMAT_R16G16B16_UINT = 432,
311 ISL_FORMAT_R16G16B16_SINT = 433,
312 ISL_FORMAT_R32_SFIXED = 434,
313 ISL_FORMAT_R10G10B10A2_SNORM = 435,
314 ISL_FORMAT_R10G10B10A2_USCALED = 436,
315 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
316 ISL_FORMAT_R10G10B10A2_SINT = 438,
317 ISL_FORMAT_B10G10R10A2_SNORM = 439,
318 ISL_FORMAT_B10G10R10A2_USCALED = 440,
319 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
320 ISL_FORMAT_B10G10R10A2_UINT = 442,
321 ISL_FORMAT_B10G10R10A2_SINT = 443,
322 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
323 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
324 ISL_FORMAT_ETC2_RGB8_PTA = 448,
325 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
326 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
327 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
328 ISL_FORMAT_R8G8B8_UINT = 456,
329 ISL_FORMAT_R8G8B8_SINT = 457,
330 ISL_FORMAT_RAW = 511,
331 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
332 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
333 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
334 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
335 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
336 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
337 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
338 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
339 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
340 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
341 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
342 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
343 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
344 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
345 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
346 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
347 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
348 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
349 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
350 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
351 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
352 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
353 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
354 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
355 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
356 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
357 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
358 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
359 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
360 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
361 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
362 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
363 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
364 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
365 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
366 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
367 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
368 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
369 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
370 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
371 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
372 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
373
374 /* The formats that follow are internal to ISL and as such don't have an
375 * explicit number. We'll just let the C compiler assign it for us. Any
376 * actual hardware formats *must* come before these in the list.
377 */
378
379 /* Formats for the aux-map */
380 ISL_FORMAT_PLANAR_420_10,
381 ISL_FORMAT_PLANAR_420_12,
382
383 /* Formats for auxiliary surfaces */
384 ISL_FORMAT_HIZ,
385 ISL_FORMAT_MCS_2X,
386 ISL_FORMAT_MCS_4X,
387 ISL_FORMAT_MCS_8X,
388 ISL_FORMAT_MCS_16X,
389 ISL_FORMAT_GEN7_CCS_32BPP_X,
390 ISL_FORMAT_GEN7_CCS_64BPP_X,
391 ISL_FORMAT_GEN7_CCS_128BPP_X,
392 ISL_FORMAT_GEN7_CCS_32BPP_Y,
393 ISL_FORMAT_GEN7_CCS_64BPP_Y,
394 ISL_FORMAT_GEN7_CCS_128BPP_Y,
395 ISL_FORMAT_GEN9_CCS_32BPP,
396 ISL_FORMAT_GEN9_CCS_64BPP,
397 ISL_FORMAT_GEN9_CCS_128BPP,
398 ISL_FORMAT_GEN12_CCS_8BPP_Y0,
399 ISL_FORMAT_GEN12_CCS_16BPP_Y0,
400 ISL_FORMAT_GEN12_CCS_32BPP_Y0,
401 ISL_FORMAT_GEN12_CCS_64BPP_Y0,
402 ISL_FORMAT_GEN12_CCS_128BPP_Y0,
403
404 /* An upper bound on the supported format enumerations */
405 ISL_NUM_FORMATS,
406
407 /* Hardware doesn't understand this out-of-band value */
408 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
409 };
410
411 /**
412 * Numerical base type for channels of isl_format.
413 */
414 enum isl_base_type {
415 ISL_VOID,
416 ISL_RAW,
417 ISL_UNORM,
418 ISL_SNORM,
419 ISL_UFLOAT,
420 ISL_SFLOAT,
421 ISL_UFIXED,
422 ISL_SFIXED,
423 ISL_UINT,
424 ISL_SINT,
425 ISL_USCALED,
426 ISL_SSCALED,
427 };
428
429 /**
430 * Colorspace of isl_format.
431 */
432 enum isl_colorspace {
433 ISL_COLORSPACE_NONE = 0,
434 ISL_COLORSPACE_LINEAR,
435 ISL_COLORSPACE_SRGB,
436 ISL_COLORSPACE_YUV,
437 };
438
439 /**
440 * Texture compression mode of isl_format.
441 */
442 enum isl_txc {
443 ISL_TXC_NONE = 0,
444 ISL_TXC_DXT1,
445 ISL_TXC_DXT3,
446 ISL_TXC_DXT5,
447 ISL_TXC_FXT1,
448 ISL_TXC_RGTC1,
449 ISL_TXC_RGTC2,
450 ISL_TXC_BPTC,
451 ISL_TXC_ETC1,
452 ISL_TXC_ETC2,
453 ISL_TXC_ASTC,
454
455 /* Used for auxiliary surface formats */
456 ISL_TXC_HIZ,
457 ISL_TXC_MCS,
458 ISL_TXC_CCS,
459 };
460
461 /**
462 * @brief Hardware tile mode
463 *
464 * WARNING: These values differ from the hardware enum values, which are
465 * unstable across hardware generations.
466 *
467 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
468 * clearly distinguish it from Yf and Ys.
469 */
470 enum isl_tiling {
471 ISL_TILING_LINEAR = 0,
472 ISL_TILING_W,
473 ISL_TILING_X,
474 ISL_TILING_Y0, /**< Legacy Y tiling */
475 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
476 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
477 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
478 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
479 ISL_TILING_GEN12_CCS, /**< Tiling format for Gen12 CCS surfaces */
480 };
481
482 /**
483 * @defgroup Tiling Flags
484 * @{
485 */
486 typedef uint32_t isl_tiling_flags_t;
487 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
488 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
489 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
490 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
491 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
492 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
493 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
494 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
495 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
496 #define ISL_TILING_ANY_MASK (~0u)
497 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
498
499 /** Any Y tiling, including legacy Y tiling. */
500 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
501 ISL_TILING_Yf_BIT | \
502 ISL_TILING_Ys_BIT)
503
504 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
505 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
506 ISL_TILING_Ys_BIT)
507 /** @} */
508
509 /**
510 * @brief Logical dimension of surface.
511 *
512 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
513 * as 2D array surfaces.
514 */
515 enum isl_surf_dim {
516 ISL_SURF_DIM_1D,
517 ISL_SURF_DIM_2D,
518 ISL_SURF_DIM_3D,
519 };
520
521 /**
522 * @brief Physical layout of the surface's dimensions.
523 */
524 enum isl_dim_layout {
525 /**
526 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
527 * 6.17.3: 2D Surfaces.
528 *
529 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
530 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
531 *
532 * One-dimensional surfaces are identical to 2D surfaces with height of
533 * one.
534 *
535 * @invariant isl_surf::phys_level0_sa::depth == 1
536 */
537 ISL_DIM_LAYOUT_GEN4_2D,
538
539 /**
540 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
541 * 6.17.5: 3D Surfaces.
542 *
543 * @invariant isl_surf::phys_level0_sa::array_len == 1
544 */
545 ISL_DIM_LAYOUT_GEN4_3D,
546
547 /**
548 * Special layout used for HiZ and stencil on Sandy Bridge to work around
549 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
550 * work the same as on gen7+ except that they don't technically support
551 * mipmapping. That does not, however, stop us from doing it. As far as
552 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
553 * single miplevel 2D (possibly array) image. The dimensions of that image
554 * are NOT minified.
555 *
556 * In order to implement HiZ and stencil on Sandy Bridge, we create one
557 * full-sized 2D (possibly array) image for every LOD with every image
558 * aligned to a page boundary. When the surface is used with the stencil
559 * or HiZ hardware, we manually offset to the image for the given LOD.
560 *
561 * As a memory saving measure, we pretend that the width of each miplevel
562 * is minified and we place LOD1 and above below LOD0 but horizontally
563 * adjacent to each other. When considered as full-sized images, LOD1 and
564 * above technically overlap. However, since we only write to part of that
565 * image, the hardware will never notice the overlap.
566 *
567 * This layout looks something like this:
568 *
569 * +---------+
570 * | |
571 * | |
572 * +---------+
573 * | |
574 * | |
575 * +---------+
576 *
577 * +----+ +-+ .
578 * | | +-+
579 * +----+
580 *
581 * +----+ +-+ .
582 * | | +-+
583 * +----+
584 */
585 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
586
587 /**
588 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
589 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
590 */
591 ISL_DIM_LAYOUT_GEN9_1D,
592 };
593
594 enum isl_aux_usage {
595 /** No Auxiliary surface is used */
596 ISL_AUX_USAGE_NONE,
597
598 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
599 ISL_AUX_USAGE_HIZ,
600
601 /** The auxiliary surface is an MCS
602 *
603 * @invariant isl_surf::samples > 1
604 */
605 ISL_AUX_USAGE_MCS,
606
607 /** The auxiliary surface is a fast-clear-only compression surface
608 *
609 * @invariant isl_surf::samples == 1
610 */
611 ISL_AUX_USAGE_CCS_D,
612
613 /** The auxiliary surface provides full lossless color compression
614 *
615 * @invariant isl_surf::samples == 1
616 */
617 ISL_AUX_USAGE_CCS_E,
618
619 /** The auxiliary surface provides full lossless color compression on
620 * Gen12.
621 *
622 * @invariant isl_surf::samples == 1
623 */
624 ISL_AUX_USAGE_GEN12_CCS_E,
625
626 /** The auxiliary surface provides full lossless media color compression
627 *
628 * @invariant isl_surf::samples == 1
629 */
630 ISL_AUX_USAGE_MC,
631
632 /** The auxiliary surface is a HiZ surface operating in write-through mode
633 * and CCS is also enabled
634 *
635 * In this mode, the HiZ and CCS surfaces act as a single fused compression
636 * surface where resolves and ambiguates operate on both surfaces at the
637 * same time. In this mode, the HiZ surface operates in write-through
638 * mode where it is only used for accelerating depth testing and not for
639 * actual compression. The CCS-compressed surface contains valid data at
640 * all times.
641 *
642 * @invariant isl_surf::samples == 1
643 */
644 ISL_AUX_USAGE_HIZ_CCS_WT,
645
646 /** The auxiliary surface is a HiZ surface with and CCS is also enabled
647 *
648 * In this mode, the HiZ and CCS surfaces act as a single fused compression
649 * surface where resolves and ambiguates operate on both surfaces at the
650 * same time. In this mode, full HiZ compression is enabled and the
651 * CCS-compressed main surface may not contain valid data. The only way to
652 * read the surface outside of the depth hardware is to do a full resolve
653 * which resolves both HiZ and CCS so the surface is in the pass-through
654 * state.
655 */
656 ISL_AUX_USAGE_HIZ_CCS,
657
658 /** The auxiliary surface is an MCS and CCS is also enabled
659 *
660 * In this mode, we have fused MCS+CCS compression where the MCS is used
661 * for fast-clears and "identical samples" compression just like on Gen7-11
662 * but each plane is then CCS compressed.
663 *
664 * @invariant isl_surf::samples > 1
665 */
666 ISL_AUX_USAGE_MCS_CCS,
667
668 /** CCS auxiliary data is used to compress a stencil buffer
669 *
670 * @invariant isl_surf::samples == 1
671 */
672 ISL_AUX_USAGE_STC_CCS,
673 };
674
675 /**
676 * Enum for keeping track of the state an auxiliary compressed surface.
677 *
678 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
679 * given slice (lod + array layer) can be in one of the six states described
680 * by this enum. Draw and resolve operations may cause the slice to change
681 * from one state to another. The six valid states are:
682 *
683 * 1) Clear: In this state, each block in the auxiliary surface contains a
684 * magic value that indicates that the block is in the clear state. If
685 * a block is in the clear state, it's values in the primary surface are
686 * ignored and the color of the samples in the block is taken either the
687 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
688 * depth. Since neither the primary surface nor the auxiliary surface
689 * contains the clear value, the surface can be cleared to a different
690 * color by simply changing the clear color without modifying either
691 * surface.
692 *
693 * 2) Partial Clear: In this state, each block in the auxiliary surface
694 * contains either the magic clear or pass-through value. See Clear and
695 * Pass-through for more details.
696 *
697 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
698 * nor the primary surface has a complete representation of the data.
699 * Instead, both surfaces must be used together or else rendering
700 * corruption may occur. Depending on the auxiliary compression format
701 * and the data, any given block in the primary surface may contain all,
702 * some, or none of the data required to reconstruct the actual sample
703 * values. Blocks may also be in the clear state (see Clear) and have
704 * their value taken from outside the surface.
705 *
706 * 4) Compressed w/o Clear: This state is identical to the state above
707 * except that no blocks are in the clear state. In this state, all of
708 * the data required to reconstruct the final sample values is contained
709 * in the auxiliary and primary surface and the clear value is not
710 * considered.
711 *
712 * 5) Resolved: In this state, the primary surface contains 100% of the
713 * data. The auxiliary surface is also valid so the surface can be
714 * validly used with or without aux enabled. The auxiliary surface may,
715 * however, contain non-trivial data and any update to the primary
716 * surface with aux disabled will cause the two to get out of sync.
717 *
718 * 6) Pass-through: In this state, the primary surface contains 100% of the
719 * data and every block in the auxiliary surface contains a magic value
720 * which indicates that the auxiliary surface should be ignored and the
721 * only the primary surface should be considered. Updating the primary
722 * surface without aux works fine and can be done repeatedly in this
723 * mode. Writing to a surface in pass-through mode with aux enabled may
724 * cause the auxiliary buffer to contain non-trivial data and no longer
725 * be in the pass-through state.
726 *
727 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
728 * data and the auxiliary surface is completely bogus. Any attempt to
729 * use the auxiliary surface is liable to result in rendering
730 * corruption. The only thing that one can do to re-enable aux once
731 * this state is reached is to use an ambiguate pass to transition into
732 * the pass-through state.
733 *
734 * Drawing with or without aux enabled may implicitly cause the surface to
735 * transition between these states. There are also four types of auxiliary
736 * compression operations which cause an explicit transition which are
737 * described by the isl_aux_op enum below.
738 *
739 * Not all operations are valid or useful in all states. The diagram below
740 * contains a complete description of the states and all valid and useful
741 * transitions except clear.
742 *
743 * Draw w/ Aux
744 * +----------+
745 * | |
746 * | +-------------+ Draw w/ Aux +-------------+
747 * +------>| Compressed |<-------------------| Clear |
748 * | w/ Clear |----->----+ | |
749 * +-------------+ | +-------------+
750 * | /|\ | | |
751 * | | | | |
752 * | | +------<-----+ | Draw w/
753 * | | | | Clear Only
754 * | | Full | | +----------+
755 * Partial | | Resolve | \|/ | |
756 * Resolve | | | +-------------+ |
757 * | | | | Partial |<------+
758 * | | | | Clear |<----------+
759 * | | | +-------------+ |
760 * | | | | |
761 * | | +------>---------+ Full |
762 * | | | Resolve |
763 * Draw w/ aux | | Partial Fast Clear | |
764 * +----------+ | +--------------------------+ | |
765 * | | \|/ | \|/ |
766 * | +-------------+ Full Resolve +-------------+ |
767 * +------>| Compressed |------------------->| Resolved | |
768 * | w/o Clear |<-------------------| | |
769 * +-------------+ Draw w/ Aux +-------------+ |
770 * /|\ | | |
771 * | Draw | | Draw |
772 * | w/ Aux | | w/o Aux |
773 * | Ambiguate | | |
774 * | +--------------------------+ | |
775 * Draw w/o Aux | | | Draw w/o Aux |
776 * +----------+ | | | +----------+ |
777 * | | | \|/ \|/ | | |
778 * | +-------------+ Ambiguate +-------------+ | |
779 * +------>| Pass- |<-------------------| Aux |<------+ |
780 * +------>| through | | Invalid | |
781 * | +-------------+ +-------------+ |
782 * | | | |
783 * +----------+ +-----------------------------------------------------+
784 * Draw w/ Partial Fast Clear
785 * Clear Only
786 *
787 *
788 * While the above general theory applies to all forms of auxiliary
789 * compression on Intel hardware, not all states and operations are available
790 * on all compression types. However, each of the auxiliary states and
791 * operations can be fairly easily mapped onto the above diagram:
792 *
793 * HiZ: Hierarchical depth compression is capable of being in any of the
794 * states above. Hardware provides three HiZ operations: "Depth
795 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
796 * Clear", "Full Resolve", and "Ambiguate" respectively. The
797 * hardware provides no HiZ partial resolve operation so the only way
798 * to get into the "Compressed w/o Clear" state is to render with HiZ
799 * when the surface is in the resolved or pass-through states.
800 *
801 * MCS: Multisample compression is technically capable of being in any of
802 * the states above except that most of them aren't useful. Both the
803 * render engine and the sampler support MCS compression and, apart
804 * from clear color, MCS is format-unaware so we leave the surface
805 * compressed 100% of the time. The hardware provides no MCS
806 * operations.
807 *
808 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
809 * the simplest forms of compression since they don't do anything
810 * beyond clear color tracking. They really only support three of
811 * the six states: Clear, Partial Clear, and Pass-through. The
812 * only CCS_D operation is "Resolve" which maps to a full resolve
813 * followed by an ambiguate.
814 *
815 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
816 * is capable of being in almost all of the above states. THe only
817 * exception is that it does not have separate resolved and pass-
818 * through states. Instead, the CCS_E full resolve operation does
819 * both a resolve and an ambiguate so it goes directly into the
820 * pass-through state. CCS_E also provides fast clear and partial
821 * resolve operations which work as described above.
822 *
823 * While it is technically possible to perform a CCS_E ambiguate, it
824 * is not provided by Sky Lake hardware so we choose to avoid the aux
825 * invalid state. If the aux invalid state were determined to be
826 * useful, a CCS ambiguate could be done by carefully rendering to
827 * the CCS and filling it with zeros.
828 */
829 enum isl_aux_state {
830 #ifdef IN_UNIT_TEST
831 ISL_AUX_STATE_ASSERT,
832 #endif
833 ISL_AUX_STATE_CLEAR,
834 ISL_AUX_STATE_PARTIAL_CLEAR,
835 ISL_AUX_STATE_COMPRESSED_CLEAR,
836 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
837 ISL_AUX_STATE_RESOLVED,
838 ISL_AUX_STATE_PASS_THROUGH,
839 ISL_AUX_STATE_AUX_INVALID,
840 };
841
842 /**
843 * Enum which describes explicit aux transition operations.
844 */
845 enum isl_aux_op {
846 #ifdef IN_UNIT_TEST
847 ISL_AUX_OP_ASSERT,
848 #endif
849
850 ISL_AUX_OP_NONE,
851
852 /** Fast Clear
853 *
854 * This operation writes the magic "clear" value to the auxiliary surface.
855 * This operation will safely transition any slice of a surface from any
856 * state to the clear state so long as the entire slice is fast cleared at
857 * once. A fast clear that only covers part of a slice of a surface is
858 * called a partial fast clear.
859 */
860 ISL_AUX_OP_FAST_CLEAR,
861
862 /** Full Resolve
863 *
864 * This operation combines the auxiliary surface data with the primary
865 * surface data and writes the result to the primary. For HiZ, the docs
866 * call this a depth resolve. For CCS, the hardware full resolve operation
867 * does both a full resolve and an ambiguate so it actually takes you all
868 * the way to the pass-through state.
869 */
870 ISL_AUX_OP_FULL_RESOLVE,
871
872 /** Partial Resolve
873 *
874 * This operation considers blocks which are in the "clear" state and
875 * writes the clear value directly into the primary or auxiliary surface.
876 * Once this operation completes, the surface is still compressed but no
877 * longer references the clear color. This operation is only available
878 * for CCS_E.
879 */
880 ISL_AUX_OP_PARTIAL_RESOLVE,
881
882 /** Ambiguate
883 *
884 * This operation throws away the current auxiliary data and replaces it
885 * with the magic pass-through value. If an ambiguate operation is
886 * performed when the primary surface does not contain 100% of the data,
887 * data will be lost. This operation is only implemented in hardware for
888 * depth where it is called a HiZ resolve.
889 */
890 ISL_AUX_OP_AMBIGUATE,
891 };
892
893 /* TODO(chadv): Explain */
894 enum isl_array_pitch_span {
895 ISL_ARRAY_PITCH_SPAN_FULL,
896 ISL_ARRAY_PITCH_SPAN_COMPACT,
897 };
898
899 /**
900 * @defgroup Surface Usage
901 * @{
902 */
903 typedef uint64_t isl_surf_usage_flags_t;
904 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
905 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
906 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
907 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
908 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
909 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
910 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
911 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
912 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
913 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
914 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
915 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
916 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
917 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
918 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
919 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
920 #define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 16)
921 #define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 17)
922 #define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 18)
923 #define ISL_SURF_USAGE_STAGING_BIT (1u << 19)
924 /** @} */
925
926 /**
927 * @defgroup Channel Mask
928 *
929 * These #define values are chosen to match the values of
930 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
931 *
932 * @{
933 */
934 typedef uint8_t isl_channel_mask_t;
935 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
936 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
937 #define ISL_CHANNEL_RED_BIT (1 << 2)
938 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
939 /** @} */
940
941 /**
942 * @brief A channel select (also known as texture swizzle) value
943 */
944 enum PACKED isl_channel_select {
945 ISL_CHANNEL_SELECT_ZERO = 0,
946 ISL_CHANNEL_SELECT_ONE = 1,
947 ISL_CHANNEL_SELECT_RED = 4,
948 ISL_CHANNEL_SELECT_GREEN = 5,
949 ISL_CHANNEL_SELECT_BLUE = 6,
950 ISL_CHANNEL_SELECT_ALPHA = 7,
951 };
952
953 /**
954 * Identical to VkSampleCountFlagBits.
955 */
956 enum isl_sample_count {
957 ISL_SAMPLE_COUNT_1_BIT = 1u,
958 ISL_SAMPLE_COUNT_2_BIT = 2u,
959 ISL_SAMPLE_COUNT_4_BIT = 4u,
960 ISL_SAMPLE_COUNT_8_BIT = 8u,
961 ISL_SAMPLE_COUNT_16_BIT = 16u,
962 };
963 typedef uint32_t isl_sample_count_mask_t;
964
965 /**
966 * @brief Multisample Format
967 */
968 enum isl_msaa_layout {
969 /**
970 * @brief Suface is single-sampled.
971 */
972 ISL_MSAA_LAYOUT_NONE,
973
974 /**
975 * @brief [SNB+] Interleaved Multisample Format
976 *
977 * In this format, multiple samples are interleaved into each cacheline.
978 * In other words, the sample index is swizzled into the low 6 bits of the
979 * surface's virtual address space.
980 *
981 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
982 * and its pixel format is 32bpp. Then the first cacheline is arranged
983 * thus:
984 *
985 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
986 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
987 *
988 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
989 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
990 *
991 * The hardware docs refer to this format with multiple terms. In
992 * Sandybridge, this is the only multisample format; so no term is used.
993 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
994 * Multisample Surface). Later hardware docs additionally refer to this
995 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
996 * color surfaces).
997 *
998 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
999 * Surface Behavior".
1000 *
1001 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
1002 * Multisampled Surfaces".
1003 */
1004 ISL_MSAA_LAYOUT_INTERLEAVED,
1005
1006 /**
1007 * @brief [IVB+] Array Multisample Format
1008 *
1009 * In this format, the surface's physical layout resembles that of a
1010 * 2D array surface.
1011 *
1012 * Suppose the multisample surface's logical extent is (w, h) and its
1013 * sample count is N. Then surface's physical extent is the same as
1014 * a singlesample 2D surface whose logical extent is (w, h) and array
1015 * length is N. Array slice `i` contains the pixel values for sample
1016 * index `i`.
1017 *
1018 * The Ivybridge docs refer to surfaces in this format as UMS
1019 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1020 * Surface). The Broadwell docs additionally refer to this format as
1021 * MSFMT_MSS (MSS=Multisample Surface Storage).
1022 *
1023 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1024 * Multisample Surfaces".
1025 *
1026 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1027 * Multisample Surfaces".
1028 */
1029 ISL_MSAA_LAYOUT_ARRAY,
1030 };
1031
1032 typedef enum {
1033 ISL_MEMCPY = 0,
1034 ISL_MEMCPY_BGRA8,
1035 ISL_MEMCPY_STREAMING_LOAD,
1036 ISL_MEMCPY_INVALID,
1037 } isl_memcpy_type;
1038
1039 struct isl_device {
1040 const struct gen_device_info *info;
1041 bool use_separate_stencil;
1042 bool has_bit6_swizzling;
1043
1044 /**
1045 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1046 * current gen.
1047 */
1048 struct {
1049 uint8_t size;
1050 uint8_t align;
1051 uint8_t addr_offset;
1052 uint8_t aux_addr_offset;
1053
1054 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1055
1056 /* size of the state buffer used to store the clear color + extra
1057 * additional space used by the hardware */
1058 uint8_t clear_color_state_size;
1059 uint8_t clear_color_state_offset;
1060 /* size of the clear color itself - used to copy it to/from a BO */
1061 uint8_t clear_value_size;
1062 uint8_t clear_value_offset;
1063 } ss;
1064
1065 /**
1066 * Describes the layout of the depth/stencil/hiz commands as emitted by
1067 * isl_emit_depth_stencil_hiz.
1068 */
1069 struct {
1070 uint8_t size;
1071 uint8_t depth_offset;
1072 uint8_t stencil_offset;
1073 uint8_t hiz_offset;
1074 } ds;
1075
1076 struct {
1077 uint32_t internal;
1078 uint32_t external;
1079 uint32_t l1_hdc_l3_llc;
1080 } mocs;
1081 };
1082
1083 struct isl_extent2d {
1084 union { uint32_t w, width; };
1085 union { uint32_t h, height; };
1086 };
1087
1088 struct isl_extent3d {
1089 union { uint32_t w, width; };
1090 union { uint32_t h, height; };
1091 union { uint32_t d, depth; };
1092 };
1093
1094 struct isl_extent4d {
1095 union { uint32_t w, width; };
1096 union { uint32_t h, height; };
1097 union { uint32_t d, depth; };
1098 union { uint32_t a, array_len; };
1099 };
1100
1101 struct isl_channel_layout {
1102 enum isl_base_type type;
1103 uint8_t start_bit; /**< Bit at which this channel starts */
1104 uint8_t bits; /**< Size in bits */
1105 };
1106
1107 /**
1108 * Each format has 3D block extent (width, height, depth). The block extent of
1109 * compressed formats is that of the format's compression block. For example,
1110 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1111 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1112 * is (w=1, h=1, d=1).
1113 */
1114 struct isl_format_layout {
1115 enum isl_format format;
1116 const char *name;
1117
1118 uint16_t bpb; /**< Bits per block */
1119 uint8_t bw; /**< Block width, in pixels */
1120 uint8_t bh; /**< Block height, in pixels */
1121 uint8_t bd; /**< Block depth, in pixels */
1122
1123 union {
1124 struct {
1125 struct isl_channel_layout r; /**< Red channel */
1126 struct isl_channel_layout g; /**< Green channel */
1127 struct isl_channel_layout b; /**< Blue channel */
1128 struct isl_channel_layout a; /**< Alpha channel */
1129 struct isl_channel_layout l; /**< Luminance channel */
1130 struct isl_channel_layout i; /**< Intensity channel */
1131 struct isl_channel_layout p; /**< Palette channel */
1132 } channels;
1133 struct isl_channel_layout channels_array[7];
1134 };
1135
1136 enum isl_colorspace colorspace;
1137 enum isl_txc txc;
1138 };
1139
1140 struct isl_tile_info {
1141 enum isl_tiling tiling;
1142
1143 /* The size (in bits per block) of a single surface element
1144 *
1145 * For surfaces with power-of-two formats, this is the same as
1146 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1147 * The logical_extent_el field is in terms of elements of this size.
1148 *
1149 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1150 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1151 * of the tiling formats can actually hold an integer number of 96-bit
1152 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1153 * 32-bit element size. It is the responsibility of the caller to
1154 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1155 * the width of a surface in tiles, you would do:
1156 *
1157 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1158 * tile_info.logical_extent_el.width);
1159 */
1160 uint32_t format_bpb;
1161
1162 /** The logical size of the tile in units of format_bpb size elements
1163 *
1164 * This field determines how a given surface is cut up into tiles. It is
1165 * used to compute the size of a surface in tiles and can be used to
1166 * determine the location of the tile containing any given surface element.
1167 * The exact value of this field depends heavily on the bits-per-block of
1168 * the format being used.
1169 */
1170 struct isl_extent2d logical_extent_el;
1171
1172 /** The physical size of the tile in bytes and rows of bytes
1173 *
1174 * This field determines how the tiles of a surface are physically layed
1175 * out in memory. The logical and physical tile extent are frequently the
1176 * same but this is not always the case. For instance, a W-tile (which is
1177 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1178 * its physical size is 128B x 32rows, the same as a Y-tile.
1179 *
1180 * @see isl_surf::row_pitch_B
1181 */
1182 struct isl_extent2d phys_extent_B;
1183 };
1184
1185 /**
1186 * Metadata about a DRM format modifier.
1187 */
1188 struct isl_drm_modifier_info {
1189 uint64_t modifier;
1190
1191 /** Text name of the modifier */
1192 const char *name;
1193
1194 /** ISL tiling implied by this modifier */
1195 enum isl_tiling tiling;
1196
1197 /** ISL aux usage implied by this modifier */
1198 enum isl_aux_usage aux_usage;
1199
1200 /** Whether or not this modifier supports clear color */
1201 bool supports_clear_color;
1202 };
1203
1204 /**
1205 * @brief Input to surface initialization
1206 *
1207 * @invariant width >= 1
1208 * @invariant height >= 1
1209 * @invariant depth >= 1
1210 * @invariant levels >= 1
1211 * @invariant samples >= 1
1212 * @invariant array_len >= 1
1213 *
1214 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1215 * @invariant if 2D then depth == 1
1216 * @invariant if 3D then array_len == 1 and samples == 1
1217 */
1218 struct isl_surf_init_info {
1219 enum isl_surf_dim dim;
1220 enum isl_format format;
1221
1222 uint32_t width;
1223 uint32_t height;
1224 uint32_t depth;
1225 uint32_t levels;
1226 uint32_t array_len;
1227 uint32_t samples;
1228
1229 /** Lower bound for isl_surf::alignment, in bytes. */
1230 uint32_t min_alignment_B;
1231
1232 /**
1233 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1234 * will fail if this is misaligned or out of bounds.
1235 */
1236 uint32_t row_pitch_B;
1237
1238 isl_surf_usage_flags_t usage;
1239
1240 /** Flags that alter how ISL selects isl_surf::tiling. */
1241 isl_tiling_flags_t tiling_flags;
1242 };
1243
1244 struct isl_surf {
1245 enum isl_surf_dim dim;
1246 enum isl_dim_layout dim_layout;
1247 enum isl_msaa_layout msaa_layout;
1248 enum isl_tiling tiling;
1249 enum isl_format format;
1250
1251 /**
1252 * Alignment of the upper-left sample of each subimage, in units of surface
1253 * elements.
1254 */
1255 struct isl_extent3d image_alignment_el;
1256
1257 /**
1258 * Logical extent of the surface's base level, in units of pixels. This is
1259 * identical to the extent defined in isl_surf_init_info.
1260 */
1261 struct isl_extent4d logical_level0_px;
1262
1263 /**
1264 * Physical extent of the surface's base level, in units of physical
1265 * surface samples.
1266 *
1267 * Consider isl_dim_layout as an operator that transforms a logical surface
1268 * layout to a physical surface layout. Then
1269 *
1270 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1271 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1272 */
1273 struct isl_extent4d phys_level0_sa;
1274
1275 uint32_t levels;
1276 uint32_t samples;
1277
1278 /** Total size of the surface, in bytes. */
1279 uint64_t size_B;
1280
1281 /** Required alignment for the surface's base address. */
1282 uint32_t alignment_B;
1283
1284 /**
1285 * The interpretation of this field depends on the value of
1286 * isl_tile_info::physical_extent_B. In particular, the width of the
1287 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1288 * and the distance in bytes between vertically adjacent tiles in the image
1289 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1290 *
1291 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1292 * this cleanly reduces to being the distance, in bytes, between vertically
1293 * adjacent surface elements.
1294 *
1295 * @see isl_tile_info::phys_extent_B;
1296 */
1297 uint32_t row_pitch_B;
1298
1299 /**
1300 * Pitch between physical array slices, in rows of surface elements.
1301 */
1302 uint32_t array_pitch_el_rows;
1303
1304 enum isl_array_pitch_span array_pitch_span;
1305
1306 /** Copy of isl_surf_init_info::usage. */
1307 isl_surf_usage_flags_t usage;
1308 };
1309
1310 struct isl_swizzle {
1311 enum isl_channel_select r:4;
1312 enum isl_channel_select g:4;
1313 enum isl_channel_select b:4;
1314 enum isl_channel_select a:4;
1315 };
1316
1317 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1318 .r = ISL_CHANNEL_SELECT_##R, \
1319 .g = ISL_CHANNEL_SELECT_##G, \
1320 .b = ISL_CHANNEL_SELECT_##B, \
1321 .a = ISL_CHANNEL_SELECT_##A, \
1322 })
1323
1324 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1325
1326 struct isl_view {
1327 /**
1328 * Indicates the usage of the particular view
1329 *
1330 * Normally, this is one bit. However, for a cube map texture, it
1331 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1332 */
1333 isl_surf_usage_flags_t usage;
1334
1335 /**
1336 * The format to use in the view
1337 *
1338 * This may differ from the format of the actual isl_surf but must have
1339 * the same block size.
1340 */
1341 enum isl_format format;
1342
1343 uint32_t base_level;
1344 uint32_t levels;
1345
1346 /**
1347 * Base array layer
1348 *
1349 * For cube maps, both base_array_layer and array_len should be
1350 * specified in terms of 2-D layers and must be a multiple of 6.
1351 *
1352 * 3-D textures are effectively treated as 2-D arrays when used as a
1353 * storage image or render target. If `usage` contains
1354 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1355 * base_array_layer and array_len are applied. If the surface is only used
1356 * for texturing, they are ignored.
1357 */
1358 uint32_t base_array_layer;
1359
1360 /**
1361 * Array Length
1362 *
1363 * Indicates the number of array elements starting at Base Array Layer.
1364 */
1365 uint32_t array_len;
1366
1367 struct isl_swizzle swizzle;
1368 };
1369
1370 union isl_color_value {
1371 float f32[4];
1372 uint32_t u32[4];
1373 int32_t i32[4];
1374 };
1375
1376 struct isl_surf_fill_state_info {
1377 const struct isl_surf *surf;
1378 const struct isl_view *view;
1379
1380 /**
1381 * The address of the surface in GPU memory.
1382 */
1383 uint64_t address;
1384
1385 /**
1386 * The Memory Object Control state for the filled surface state.
1387 *
1388 * The exact format of this value depends on hardware generation.
1389 */
1390 uint32_t mocs;
1391
1392 /**
1393 * The auxilary surface or NULL if no auxilary surface is to be used.
1394 */
1395 const struct isl_surf *aux_surf;
1396 enum isl_aux_usage aux_usage;
1397 uint64_t aux_address;
1398
1399 /**
1400 * The clear color for this surface
1401 *
1402 * Valid values depend on hardware generation.
1403 */
1404 union isl_color_value clear_color;
1405
1406 /**
1407 * Send only the clear value address
1408 *
1409 * If set, we only pass the clear address to the GPU and it will fetch it
1410 * from wherever it is.
1411 */
1412 bool use_clear_address;
1413 uint64_t clear_address;
1414
1415 /**
1416 * Surface write disables for gen4-5
1417 */
1418 isl_channel_mask_t write_disables;
1419
1420 /* Intra-tile offset */
1421 uint16_t x_offset_sa, y_offset_sa;
1422 };
1423
1424 struct isl_buffer_fill_state_info {
1425 /**
1426 * The address of the surface in GPU memory.
1427 */
1428 uint64_t address;
1429
1430 /**
1431 * The size of the buffer
1432 */
1433 uint64_t size_B;
1434
1435 /**
1436 * The Memory Object Control state for the filled surface state.
1437 *
1438 * The exact format of this value depends on hardware generation.
1439 */
1440 uint32_t mocs;
1441
1442 /**
1443 * The format to use in the surface state
1444 *
1445 * This may differ from the format of the actual isl_surf but have the
1446 * same block size.
1447 */
1448 enum isl_format format;
1449
1450 /**
1451 * The swizzle to use in the surface state
1452 */
1453 struct isl_swizzle swizzle;
1454
1455 uint32_t stride_B;
1456 };
1457
1458 struct isl_depth_stencil_hiz_emit_info {
1459 /**
1460 * The depth surface
1461 */
1462 const struct isl_surf *depth_surf;
1463
1464 /**
1465 * The stencil surface
1466 *
1467 * If separate stencil is not available, this must point to the same
1468 * isl_surf as depth_surf.
1469 */
1470 const struct isl_surf *stencil_surf;
1471
1472 /**
1473 * The view into the depth and stencil surfaces.
1474 *
1475 * This view applies to both surfaces simultaneously.
1476 */
1477 const struct isl_view *view;
1478
1479 /**
1480 * The address of the depth surface in GPU memory
1481 */
1482 uint64_t depth_address;
1483
1484 /**
1485 * The address of the stencil surface in GPU memory
1486 *
1487 * If separate stencil is not available, this must have the same value as
1488 * depth_address.
1489 */
1490 uint64_t stencil_address;
1491
1492 /**
1493 * The Memory Object Control state for depth and stencil buffers
1494 *
1495 * Both depth and stencil will get the same MOCS value. The exact format
1496 * of this value depends on hardware generation.
1497 */
1498 uint32_t mocs;
1499
1500 /**
1501 * The HiZ surface or NULL if HiZ is disabled.
1502 */
1503 const struct isl_surf *hiz_surf;
1504 enum isl_aux_usage hiz_usage;
1505 uint64_t hiz_address;
1506
1507 /**
1508 * The depth clear value
1509 */
1510 float depth_clear_value;
1511
1512 /**
1513 * Track stencil aux usage for Gen >= 12
1514 */
1515 enum isl_aux_usage stencil_aux_usage;
1516 };
1517
1518 extern const struct isl_format_layout isl_format_layouts[];
1519
1520 void
1521 isl_device_init(struct isl_device *dev,
1522 const struct gen_device_info *info,
1523 bool has_bit6_swizzling);
1524
1525 isl_sample_count_mask_t ATTRIBUTE_CONST
1526 isl_device_get_sample_counts(struct isl_device *dev);
1527
1528 static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)1529 isl_format_get_layout(enum isl_format fmt)
1530 {
1531 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1532 assert(fmt < ISL_NUM_FORMATS);
1533 return &isl_format_layouts[fmt];
1534 }
1535
1536 bool isl_format_is_valid(enum isl_format);
1537
1538 static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)1539 isl_format_get_name(enum isl_format fmt)
1540 {
1541 return isl_format_get_layout(fmt)->name;
1542 }
1543
1544 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
1545
1546 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1547 enum isl_format format);
1548 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1549 enum isl_format format);
1550 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1551 enum isl_format format);
1552 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1553 enum isl_format format);
1554 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1555 enum isl_format format);
1556 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1557 enum isl_format format);
1558 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1559 enum isl_format format);
1560 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1561 enum isl_format format);
1562 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1563 enum isl_format format);
1564 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1565 enum isl_format format);
1566
1567 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1568 enum isl_format format1,
1569 enum isl_format format2);
1570 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
1571
1572 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1573 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1574 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1575 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1576 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1577 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1578
1579 static inline bool
isl_format_has_normalized_channel(enum isl_format fmt)1580 isl_format_has_normalized_channel(enum isl_format fmt)
1581 {
1582 return isl_format_has_unorm_channel(fmt) ||
1583 isl_format_has_snorm_channel(fmt);
1584 }
1585
1586 static inline bool
isl_format_has_float_channel(enum isl_format fmt)1587 isl_format_has_float_channel(enum isl_format fmt)
1588 {
1589 return isl_format_has_ufloat_channel(fmt) ||
1590 isl_format_has_sfloat_channel(fmt);
1591 }
1592
1593 static inline bool
isl_format_has_int_channel(enum isl_format fmt)1594 isl_format_has_int_channel(enum isl_format fmt)
1595 {
1596 return isl_format_has_uint_channel(fmt) ||
1597 isl_format_has_sint_channel(fmt);
1598 }
1599
1600 bool isl_format_has_color_component(enum isl_format fmt,
1601 int component) ATTRIBUTE_CONST;
1602
1603 unsigned isl_format_get_num_channels(enum isl_format fmt);
1604
1605 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1606
1607 static inline bool
isl_format_is_compressed(enum isl_format fmt)1608 isl_format_is_compressed(enum isl_format fmt)
1609 {
1610 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1611
1612 return fmtl->txc != ISL_TXC_NONE;
1613 }
1614
1615 static inline bool
isl_format_has_bc_compression(enum isl_format fmt)1616 isl_format_has_bc_compression(enum isl_format fmt)
1617 {
1618 switch (isl_format_get_layout(fmt)->txc) {
1619 case ISL_TXC_DXT1:
1620 case ISL_TXC_DXT3:
1621 case ISL_TXC_DXT5:
1622 return true;
1623 case ISL_TXC_NONE:
1624 case ISL_TXC_FXT1:
1625 case ISL_TXC_RGTC1:
1626 case ISL_TXC_RGTC2:
1627 case ISL_TXC_BPTC:
1628 case ISL_TXC_ETC1:
1629 case ISL_TXC_ETC2:
1630 case ISL_TXC_ASTC:
1631 return false;
1632
1633 case ISL_TXC_HIZ:
1634 case ISL_TXC_MCS:
1635 case ISL_TXC_CCS:
1636 unreachable("Should not be called on an aux surface");
1637 }
1638
1639 unreachable("bad texture compression mode");
1640 return false;
1641 }
1642
1643 static inline bool
isl_format_is_planar(enum isl_format fmt)1644 isl_format_is_planar(enum isl_format fmt)
1645 {
1646 return fmt == ISL_FORMAT_PLANAR_420_8 ||
1647 fmt == ISL_FORMAT_PLANAR_420_10 ||
1648 fmt == ISL_FORMAT_PLANAR_420_12 ||
1649 fmt == ISL_FORMAT_PLANAR_420_16;
1650 }
1651
1652 static inline bool
isl_format_is_yuv(enum isl_format fmt)1653 isl_format_is_yuv(enum isl_format fmt)
1654 {
1655 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1656
1657 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1658 }
1659
1660 static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)1661 isl_format_block_is_1x1x1(enum isl_format fmt)
1662 {
1663 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1664
1665 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1666 }
1667
1668 static inline bool
isl_format_is_srgb(enum isl_format fmt)1669 isl_format_is_srgb(enum isl_format fmt)
1670 {
1671 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1672 }
1673
1674 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1675
1676 static inline bool
isl_format_is_rgb(enum isl_format fmt)1677 isl_format_is_rgb(enum isl_format fmt)
1678 {
1679 if (isl_format_is_yuv(fmt))
1680 return false;
1681
1682 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1683
1684 return fmtl->channels.r.bits > 0 &&
1685 fmtl->channels.g.bits > 0 &&
1686 fmtl->channels.b.bits > 0 &&
1687 fmtl->channels.a.bits == 0;
1688 }
1689
1690 static inline bool
isl_format_is_rgbx(enum isl_format fmt)1691 isl_format_is_rgbx(enum isl_format fmt)
1692 {
1693 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1694
1695 return fmtl->channels.r.bits > 0 &&
1696 fmtl->channels.g.bits > 0 &&
1697 fmtl->channels.b.bits > 0 &&
1698 fmtl->channels.a.bits > 0 &&
1699 fmtl->channels.a.type == ISL_VOID;
1700 }
1701
1702 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1703 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1704 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1705
1706 union isl_color_value
1707 isl_color_value_swizzle_inv(union isl_color_value src,
1708 struct isl_swizzle swizzle);
1709
1710 void isl_color_value_pack(const union isl_color_value *value,
1711 enum isl_format format,
1712 uint32_t *data_out);
1713 void isl_color_value_unpack(union isl_color_value *value,
1714 enum isl_format format,
1715 const uint32_t *data_in);
1716
1717 bool isl_is_storage_image_format(enum isl_format fmt);
1718
1719 enum isl_format
1720 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1721 enum isl_format fmt);
1722
1723 /* Returns true if this hardware supports typed load/store on a format with
1724 * the same size as the given format.
1725 */
1726 bool
1727 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1728 enum isl_format fmt);
1729
1730 static inline enum isl_tiling
isl_tiling_flag_to_enum(isl_tiling_flags_t flag)1731 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
1732 {
1733 assert(__builtin_popcount(flag) == 1);
1734 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
1735 }
1736
1737 static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)1738 isl_tiling_is_any_y(enum isl_tiling tiling)
1739 {
1740 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1741 }
1742
1743 static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)1744 isl_tiling_is_std_y(enum isl_tiling tiling)
1745 {
1746 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1747 }
1748
1749 uint32_t
1750 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1751
1752 enum isl_tiling
1753 isl_tiling_from_i915_tiling(uint32_t tiling);
1754
1755 /**
1756 * Return an isl_aux_op needed to enable an access to occur in an
1757 * isl_aux_state suitable for the isl_aux_usage.
1758 *
1759 * NOTE: If the access will invalidate the main surface, this function should
1760 * not be called and the isl_aux_op of NONE should be used instead.
1761 * Otherwise, an extra (but still lossless) ambiguate may occur.
1762 *
1763 * @invariant initial_state is possible with an isl_aux_usage compatible with
1764 * the given usage. Two usages are compatible if it's possible to
1765 * switch between them (e.g. CCS_E <-> CCS_D).
1766 * @invariant fast_clear is false if the aux doesn't support fast clears.
1767 */
1768 enum isl_aux_op
1769 isl_aux_prepare_access(enum isl_aux_state initial_state,
1770 enum isl_aux_usage usage,
1771 bool fast_clear_supported);
1772
1773 /**
1774 * Return the isl_aux_state entered after performing an isl_aux_op.
1775 *
1776 * @invariant initial_state is possible with the given usage.
1777 * @invariant op is possible with the given usage.
1778 * @invariant op must not cause HW to read from an invalid aux.
1779 */
1780 enum isl_aux_state
1781 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
1782 enum isl_aux_usage usage,
1783 enum isl_aux_op op);
1784
1785 /**
1786 * Return the isl_aux_state entered after performing a write.
1787 *
1788 * NOTE: full_surface should be true if the write covers the entire
1789 * slice. Setting it to false in this case will still result in a
1790 * correct (but imprecise) aux state.
1791 *
1792 * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
1793 * possible with the given usage.
1794 * @invariant usage can be ISL_AUX_USAGE_NONE iff:
1795 * * the main surface is valid, or
1796 * * the main surface is being invalidated/replaced.
1797 */
1798 enum isl_aux_state
1799 isl_aux_state_transition_write(enum isl_aux_state initial_state,
1800 enum isl_aux_usage usage,
1801 bool full_surface);
1802
1803 bool
1804 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
1805
1806 static inline bool
isl_aux_usage_has_hiz(enum isl_aux_usage usage)1807 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
1808 {
1809 return usage == ISL_AUX_USAGE_HIZ ||
1810 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
1811 usage == ISL_AUX_USAGE_HIZ_CCS;
1812 }
1813
1814 static inline bool
isl_aux_usage_has_mcs(enum isl_aux_usage usage)1815 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
1816 {
1817 return usage == ISL_AUX_USAGE_MCS ||
1818 usage == ISL_AUX_USAGE_MCS_CCS;
1819 }
1820
1821 static inline bool
isl_aux_usage_has_ccs(enum isl_aux_usage usage)1822 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
1823 {
1824 return usage == ISL_AUX_USAGE_CCS_D ||
1825 usage == ISL_AUX_USAGE_CCS_E ||
1826 usage == ISL_AUX_USAGE_GEN12_CCS_E ||
1827 usage == ISL_AUX_USAGE_MC ||
1828 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
1829 usage == ISL_AUX_USAGE_HIZ_CCS ||
1830 usage == ISL_AUX_USAGE_MCS_CCS ||
1831 usage == ISL_AUX_USAGE_STC_CCS;
1832 }
1833
1834 static inline bool
isl_aux_state_has_valid_primary(enum isl_aux_state state)1835 isl_aux_state_has_valid_primary(enum isl_aux_state state)
1836 {
1837 return state == ISL_AUX_STATE_RESOLVED ||
1838 state == ISL_AUX_STATE_PASS_THROUGH ||
1839 state == ISL_AUX_STATE_AUX_INVALID;
1840 }
1841
1842 static inline bool
isl_aux_state_has_valid_aux(enum isl_aux_state state)1843 isl_aux_state_has_valid_aux(enum isl_aux_state state)
1844 {
1845 return state != ISL_AUX_STATE_AUX_INVALID;
1846 }
1847
1848 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1849 isl_drm_modifier_get_info(uint64_t modifier);
1850
1851 static inline bool
isl_drm_modifier_has_aux(uint64_t modifier)1852 isl_drm_modifier_has_aux(uint64_t modifier)
1853 {
1854 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1855 }
1856
1857 /** Returns the default isl_aux_state for the given modifier.
1858 *
1859 * If we have a modifier which supports compression, then the auxiliary data
1860 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1861 * can be in any of the following:
1862 *
1863 * - ISL_AUX_STATE_CLEAR
1864 * - ISL_AUX_STATE_PARTIAL_CLEAR
1865 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1866 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1867 * - ISL_AUX_STATE_RESOLVED
1868 * - ISL_AUX_STATE_PASS_THROUGH
1869 *
1870 * If the modifier does not support fast-clears, then we are guaranteed
1871 * that the surface is at least partially resolved and the first three not
1872 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1873 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1874 * because they are the least common denominator of the set of possible aux
1875 * states and will yield a valid interpretation of the aux data.
1876 *
1877 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1878 */
1879 static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)1880 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1881 {
1882 const struct isl_drm_modifier_info *mod_info =
1883 isl_drm_modifier_get_info(modifier);
1884
1885 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1886 return ISL_AUX_STATE_AUX_INVALID;
1887
1888 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
1889 mod_info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E ||
1890 mod_info->aux_usage == ISL_AUX_USAGE_MC);
1891 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1892 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1893 }
1894
1895 struct isl_extent2d ATTRIBUTE_CONST
1896 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1897
1898 static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)1899 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1900 {
1901 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1902 }
1903
1904 static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)1905 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1906 {
1907 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1908 }
1909
1910 static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)1911 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1912 {
1913 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1914 }
1915
1916 static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)1917 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1918 {
1919 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1920 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1921 }
1922
1923 static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)1924 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1925 {
1926 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1927 }
1928
1929 static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info * info)1930 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1931 {
1932 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1933 (info->format == ISL_FORMAT_R16_UNORM);
1934 }
1935
1936 static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info * info)1937 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1938 {
1939 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1940 (info->format == ISL_FORMAT_R32_FLOAT);
1941 }
1942
1943 static inline struct isl_extent2d
isl_extent2d(uint32_t width,uint32_t height)1944 isl_extent2d(uint32_t width, uint32_t height)
1945 {
1946 struct isl_extent2d e = { { 0 } };
1947
1948 e.width = width;
1949 e.height = height;
1950
1951 return e;
1952 }
1953
1954 static inline struct isl_extent3d
isl_extent3d(uint32_t width,uint32_t height,uint32_t depth)1955 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1956 {
1957 struct isl_extent3d e = { { 0 } };
1958
1959 e.width = width;
1960 e.height = height;
1961 e.depth = depth;
1962
1963 return e;
1964 }
1965
1966 static inline struct isl_extent4d
isl_extent4d(uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)1967 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1968 uint32_t array_len)
1969 {
1970 struct isl_extent4d e = { { 0 } };
1971
1972 e.width = width;
1973 e.height = height;
1974 e.depth = depth;
1975 e.array_len = array_len;
1976
1977 return e;
1978 }
1979
1980 bool isl_color_value_is_zero(union isl_color_value value,
1981 enum isl_format format);
1982
1983 bool isl_color_value_is_zero_one(union isl_color_value value,
1984 enum isl_format format);
1985
1986 static inline bool
isl_swizzle_is_identity(struct isl_swizzle swizzle)1987 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1988 {
1989 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1990 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1991 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1992 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1993 }
1994
1995 bool
1996 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1997 struct isl_swizzle swizzle);
1998
1999 struct isl_swizzle
2000 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
2001 struct isl_swizzle
2002 isl_swizzle_invert(struct isl_swizzle swizzle);
2003
2004 uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage);
2005
2006 #define isl_surf_init(dev, surf, ...) \
2007 isl_surf_init_s((dev), (surf), \
2008 &(struct isl_surf_init_info) { __VA_ARGS__ });
2009
2010 bool
2011 isl_surf_init_s(const struct isl_device *dev,
2012 struct isl_surf *surf,
2013 const struct isl_surf_init_info *restrict info);
2014
2015 void
2016 isl_surf_get_tile_info(const struct isl_surf *surf,
2017 struct isl_tile_info *tile_info);
2018
2019 bool
2020 isl_surf_supports_ccs(const struct isl_device *dev,
2021 const struct isl_surf *surf);
2022
2023 bool
2024 isl_surf_get_hiz_surf(const struct isl_device *dev,
2025 const struct isl_surf *surf,
2026 struct isl_surf *hiz_surf);
2027
2028 bool
2029 isl_surf_get_mcs_surf(const struct isl_device *dev,
2030 const struct isl_surf *surf,
2031 struct isl_surf *mcs_surf);
2032
2033 bool
2034 isl_surf_get_ccs_surf(const struct isl_device *dev,
2035 const struct isl_surf *surf,
2036 struct isl_surf *aux_surf,
2037 struct isl_surf *extra_aux_surf,
2038 uint32_t row_pitch_B /**< Ignored if 0 */);
2039
2040 #define isl_surf_fill_state(dev, state, ...) \
2041 isl_surf_fill_state_s((dev), (state), \
2042 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2043
2044 void
2045 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
2046 const struct isl_surf_fill_state_info *restrict info);
2047
2048 #define isl_buffer_fill_state(dev, state, ...) \
2049 isl_buffer_fill_state_s((dev), (state), \
2050 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2051
2052 void
2053 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
2054 const struct isl_buffer_fill_state_info *restrict info);
2055
2056 void
2057 isl_null_fill_state(const struct isl_device *dev, void *state,
2058 struct isl_extent3d size);
2059
2060 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2061 isl_emit_depth_stencil_hiz_s((dev), (batch), \
2062 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2063
2064 void
2065 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
2066 const struct isl_depth_stencil_hiz_emit_info *restrict info);
2067
2068 void
2069 isl_surf_fill_image_param(const struct isl_device *dev,
2070 struct brw_image_param *param,
2071 const struct isl_surf *surf,
2072 const struct isl_view *view);
2073
2074 void
2075 isl_buffer_fill_image_param(const struct isl_device *dev,
2076 struct brw_image_param *param,
2077 enum isl_format format,
2078 uint64_t size);
2079
2080 /**
2081 * Alignment of the upper-left sample of each subimage, in units of surface
2082 * elements.
2083 */
2084 static inline struct isl_extent3d
isl_surf_get_image_alignment_el(const struct isl_surf * surf)2085 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2086 {
2087 return surf->image_alignment_el;
2088 }
2089
2090 /**
2091 * Alignment of the upper-left sample of each subimage, in units of surface
2092 * samples.
2093 */
2094 static inline struct isl_extent3d
isl_surf_get_image_alignment_sa(const struct isl_surf * surf)2095 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2096 {
2097 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2098
2099 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2100 fmtl->bh * surf->image_alignment_el.h,
2101 fmtl->bd * surf->image_alignment_el.d);
2102 }
2103
2104 /**
2105 * Logical extent of level 0 in units of surface elements.
2106 */
2107 static inline struct isl_extent4d
isl_surf_get_logical_level0_el(const struct isl_surf * surf)2108 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2109 {
2110 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2111
2112 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2113 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2114 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2115 surf->logical_level0_px.a);
2116 }
2117
2118 /**
2119 * Physical extent of level 0 in units of surface elements.
2120 */
2121 static inline struct isl_extent4d
isl_surf_get_phys_level0_el(const struct isl_surf * surf)2122 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2123 {
2124 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2125
2126 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2127 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2128 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2129 surf->phys_level0_sa.a);
2130 }
2131
2132 /**
2133 * Pitch between vertically adjacent surface elements, in bytes.
2134 */
2135 static inline uint32_t
isl_surf_get_row_pitch_B(const struct isl_surf * surf)2136 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2137 {
2138 return surf->row_pitch_B;
2139 }
2140
2141 /**
2142 * Pitch between vertically adjacent surface elements, in units of surface elements.
2143 */
2144 static inline uint32_t
isl_surf_get_row_pitch_el(const struct isl_surf * surf)2145 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2146 {
2147 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2148
2149 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2150 return surf->row_pitch_B / (fmtl->bpb / 8);
2151 }
2152
2153 /**
2154 * Pitch between physical array slices, in rows of surface elements.
2155 */
2156 static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf * surf)2157 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2158 {
2159 return surf->array_pitch_el_rows;
2160 }
2161
2162 /**
2163 * Pitch between physical array slices, in units of surface elements.
2164 */
2165 static inline uint32_t
isl_surf_get_array_pitch_el(const struct isl_surf * surf)2166 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2167 {
2168 return isl_surf_get_array_pitch_el_rows(surf) *
2169 isl_surf_get_row_pitch_el(surf);
2170 }
2171
2172 /**
2173 * Pitch between physical array slices, in rows of surface samples.
2174 */
2175 static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf * surf)2176 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2177 {
2178 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2179 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2180 }
2181
2182 /**
2183 * Pitch between physical array slices, in bytes.
2184 */
2185 static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf * surf)2186 isl_surf_get_array_pitch(const struct isl_surf *surf)
2187 {
2188 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2189 }
2190
2191 /**
2192 * Calculate the offset, in units of surface samples, to a subimage in the
2193 * surface.
2194 *
2195 * @invariant level < surface levels
2196 * @invariant logical_array_layer < logical array length of surface
2197 * @invariant logical_z_offset_px < logical depth of surface at level
2198 */
2199 void
2200 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2201 uint32_t level,
2202 uint32_t logical_array_layer,
2203 uint32_t logical_z_offset_px,
2204 uint32_t *x_offset_sa,
2205 uint32_t *y_offset_sa);
2206
2207 /**
2208 * Calculate the offset, in units of surface elements, to a subimage in the
2209 * surface.
2210 *
2211 * @invariant level < surface levels
2212 * @invariant logical_array_layer < logical array length of surface
2213 * @invariant logical_z_offset_px < logical depth of surface at level
2214 */
2215 void
2216 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2217 uint32_t level,
2218 uint32_t logical_array_layer,
2219 uint32_t logical_z_offset_px,
2220 uint32_t *x_offset_el,
2221 uint32_t *y_offset_el);
2222
2223 /**
2224 * Calculate the offset, in bytes and intratile surface samples, to a
2225 * subimage in the surface.
2226 *
2227 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2228 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2229 * offsets to samples.
2230 *
2231 * @invariant level < surface levels
2232 * @invariant logical_array_layer < logical array length of surface
2233 * @invariant logical_z_offset_px < logical depth of surface at level
2234 */
2235 void
2236 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2237 uint32_t level,
2238 uint32_t logical_array_layer,
2239 uint32_t logical_z_offset_px,
2240 uint32_t *offset_B,
2241 uint32_t *x_offset_sa,
2242 uint32_t *y_offset_sa);
2243
2244 /**
2245 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2246 *
2247 * The range returned will be the smallest memory range in which the give
2248 * subimage fits, rounded to even tiles. Intel images do not usually have a
2249 * direct subimage -> range mapping so the range returned may contain data
2250 * from other sub-images. The returned range is a half-open interval where
2251 * all of the addresses within the subimage are < end_tile_B.
2252 *
2253 * @invariant level < surface levels
2254 * @invariant logical_array_layer < logical array length of surface
2255 * @invariant logical_z_offset_px < logical depth of surface at level
2256 */
2257 void
2258 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2259 uint32_t level,
2260 uint32_t logical_array_layer,
2261 uint32_t logical_z_offset_px,
2262 uint32_t *start_tile_B,
2263 uint32_t *end_tile_B);
2264
2265 /**
2266 * Create an isl_surf that represents a particular subimage in the surface.
2267 *
2268 * The newly created surface will have a single miplevel and array slice. The
2269 * surface lives at the returned byte and intratile offsets, in samples.
2270 *
2271 * It is safe to call this function with surf == image_surf.
2272 *
2273 * @invariant level < surface levels
2274 * @invariant logical_array_layer < logical array length of surface
2275 * @invariant logical_z_offset_px < logical depth of surface at level
2276 */
2277 void
2278 isl_surf_get_image_surf(const struct isl_device *dev,
2279 const struct isl_surf *surf,
2280 uint32_t level,
2281 uint32_t logical_array_layer,
2282 uint32_t logical_z_offset_px,
2283 struct isl_surf *image_surf,
2284 uint32_t *offset_B,
2285 uint32_t *x_offset_sa,
2286 uint32_t *y_offset_sa);
2287
2288 /**
2289 * @brief Calculate the intratile offsets to a surface.
2290 *
2291 * In @a base_address_offset return the offset from the base of the surface to
2292 * the base address of the first tile of the subimage. In @a x_offset_B and
2293 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2294 * tile's base to the subimage's first surface element. The x and y offsets
2295 * are intratile offsets; that is, they do not exceed the boundary of the
2296 * surface's tiling format.
2297 */
2298 void
2299 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2300 uint32_t bpb,
2301 uint32_t row_pitch_B,
2302 uint32_t total_x_offset_el,
2303 uint32_t total_y_offset_el,
2304 uint32_t *base_address_offset,
2305 uint32_t *x_offset_el,
2306 uint32_t *y_offset_el);
2307
2308 static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,enum isl_format format,uint32_t row_pitch_B,uint32_t total_x_offset_sa,uint32_t total_y_offset_sa,uint32_t * base_address_offset,uint32_t * x_offset_sa,uint32_t * y_offset_sa)2309 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2310 enum isl_format format,
2311 uint32_t row_pitch_B,
2312 uint32_t total_x_offset_sa,
2313 uint32_t total_y_offset_sa,
2314 uint32_t *base_address_offset,
2315 uint32_t *x_offset_sa,
2316 uint32_t *y_offset_sa)
2317 {
2318 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2319
2320 /* For computing the intratile offsets, we actually want a strange unit
2321 * which is samples for multisampled surfaces but elements for compressed
2322 * surfaces.
2323 */
2324 assert(total_x_offset_sa % fmtl->bw == 0);
2325 assert(total_y_offset_sa % fmtl->bh == 0);
2326 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2327 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2328
2329 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2330 total_x_offset, total_y_offset,
2331 base_address_offset,
2332 x_offset_sa, y_offset_sa);
2333 *x_offset_sa *= fmtl->bw;
2334 *y_offset_sa *= fmtl->bh;
2335 }
2336
2337 /**
2338 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2339 *
2340 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2341 * @pre surf->format must be a valid format for depth surfaces
2342 */
2343 uint32_t
2344 isl_surf_get_depth_format(const struct isl_device *dev,
2345 const struct isl_surf *surf);
2346
2347 /**
2348 * @brief performs a copy from linear to tiled surface
2349 *
2350 */
2351 void
2352 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2353 uint32_t yt1, uint32_t yt2,
2354 char *dst, const char *src,
2355 uint32_t dst_pitch, int32_t src_pitch,
2356 bool has_swizzling,
2357 enum isl_tiling tiling,
2358 isl_memcpy_type copy_type);
2359
2360 /**
2361 * @brief performs a copy from tiled to linear surface
2362 *
2363 */
2364 void
2365 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2366 uint32_t yt1, uint32_t yt2,
2367 char *dst, const char *src,
2368 int32_t dst_pitch, uint32_t src_pitch,
2369 bool has_swizzling,
2370 enum isl_tiling tiling,
2371 isl_memcpy_type copy_type);
2372
2373 #ifdef __cplusplus
2374 }
2375 #endif
2376
2377 #endif /* ISL_H */
2378