1 /*
2  * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef STPMIC1_H
8 #define STPMIC1_H
9 
10 #include <drivers/st/stm32_i2c.h>
11 #include <lib/utils_def.h>
12 
13 #define TURN_ON_REG			0x1U
14 #define TURN_OFF_REG			0x2U
15 #define ICC_LDO_TURN_OFF_REG		0x3U
16 #define ICC_BUCK_TURN_OFF_REG		0x4U
17 #define RESET_STATUS_REG		0x5U
18 #define VERSION_STATUS_REG		0x6U
19 #define MAIN_CONTROL_REG		0x10U
20 #define PADS_PULL_REG			0x11U
21 #define BUCK_PULL_DOWN_REG		0x12U
22 #define LDO14_PULL_DOWN_REG		0x13U
23 #define LDO56_PULL_DOWN_REG		0x14U
24 #define VIN_CONTROL_REG			0x15U
25 #define PONKEY_TIMER_REG		0x16U
26 #define MASK_RANK_BUCK_REG		0x17U
27 #define MASK_RESET_BUCK_REG		0x18U
28 #define MASK_RANK_LDO_REG		0x19U
29 #define MASK_RESET_LDO_REG		0x1AU
30 #define WATCHDOG_CONTROL_REG		0x1BU
31 #define WATCHDOG_TIMER_REG		0x1CU
32 #define BUCK_ICC_TURNOFF_REG		0x1DU
33 #define LDO_ICC_TURNOFF_REG		0x1EU
34 #define BUCK_APM_CONTROL_REG		0x1FU
35 #define BUCK1_CONTROL_REG		0x20U
36 #define BUCK2_CONTROL_REG		0x21U
37 #define BUCK3_CONTROL_REG		0x22U
38 #define BUCK4_CONTROL_REG		0x23U
39 #define VREF_DDR_CONTROL_REG		0x24U
40 #define LDO1_CONTROL_REG		0x25U
41 #define LDO2_CONTROL_REG		0x26U
42 #define LDO3_CONTROL_REG		0x27U
43 #define LDO4_CONTROL_REG		0x28U
44 #define LDO5_CONTROL_REG		0x29U
45 #define LDO6_CONTROL_REG		0x2AU
46 #define BUCK1_PWRCTRL_REG		0x30U
47 #define BUCK2_PWRCTRL_REG		0x31U
48 #define BUCK3_PWRCTRL_REG		0x32U
49 #define BUCK4_PWRCTRL_REG		0x33U
50 #define VREF_DDR_PWRCTRL_REG		0x34U
51 #define LDO1_PWRCTRL_REG		0x35U
52 #define LDO2_PWRCTRL_REG		0x36U
53 #define LDO3_PWRCTRL_REG		0x37U
54 #define LDO4_PWRCTRL_REG		0x38U
55 #define LDO5_PWRCTRL_REG		0x39U
56 #define LDO6_PWRCTRL_REG		0x3AU
57 #define FREQUENCY_SPREADING_REG		0x3BU
58 #define USB_CONTROL_REG			0x40U
59 #define ITLATCH1_REG			0x50U
60 #define ITLATCH2_REG			0x51U
61 #define ITLATCH3_REG			0x52U
62 #define ITLATCH4_REG			0x53U
63 #define ITSETLATCH1_REG			0x60U
64 #define ITSETLATCH2_REG			0x61U
65 #define ITSETLATCH3_REG			0x62U
66 #define ITSETLATCH4_REG			0x63U
67 #define ITCLEARLATCH1_REG		0x70U
68 #define ITCLEARLATCH2_REG		0x71U
69 #define ITCLEARLATCH3_REG		0x72U
70 #define ITCLEARLATCH4_REG		0x73U
71 #define ITMASK1_REG			0x80U
72 #define ITMASK2_REG			0x81U
73 #define ITMASK3_REG			0x82U
74 #define ITMASK4_REG			0x83U
75 #define ITSETMASK1_REG			0x90U
76 #define ITSETMASK2_REG			0x91U
77 #define ITSETMASK3_REG			0x92U
78 #define ITSETMASK4_REG			0x93U
79 #define ITCLEARMASK1_REG		0xA0U
80 #define ITCLEARMASK2_REG		0xA1U
81 #define ITCLEARMASK3_REG		0xA2U
82 #define ITCLEARMASK4_REG		0xA3U
83 #define ITSOURCE1_REG			0xB0U
84 #define ITSOURCE2_REG			0xB1U
85 #define ITSOURCE3_REG			0xB2U
86 #define ITSOURCE4_REG			0xB3U
87 
88 /* Registers masks */
89 #define LDO_VOLTAGE_MASK		0x7CU
90 #define BUCK_VOLTAGE_MASK		0xFCU
91 #define LDO_BUCK_VOLTAGE_SHIFT		2
92 #define LDO_BUCK_ENABLE_MASK		0x01U
93 #define LDO_BUCK_HPLP_ENABLE_MASK	0x02U
94 #define LDO_BUCK_HPLP_SHIFT		1
95 #define LDO_BUCK_RANK_MASK		0x01U
96 #define LDO_BUCK_RESET_MASK		0x01U
97 #define LDO_BUCK_PULL_DOWN_MASK		0x03U
98 
99 /* Pull down register */
100 #define BUCK1_PULL_DOWN_SHIFT		0
101 #define BUCK2_PULL_DOWN_SHIFT		2
102 #define BUCK3_PULL_DOWN_SHIFT		4
103 #define BUCK4_PULL_DOWN_SHIFT		6
104 #define VREF_DDR_PULL_DOWN_SHIFT	4
105 
106 /* Buck Mask reset register */
107 #define BUCK1_MASK_RESET		0
108 #define BUCK2_MASK_RESET		1
109 #define BUCK3_MASK_RESET		2
110 #define BUCK4_MASK_RESET		3
111 
112 /* LDO Mask reset register */
113 #define LDO1_MASK_RESET			0
114 #define LDO2_MASK_RESET			1
115 #define LDO3_MASK_RESET			2
116 #define LDO4_MASK_RESET			3
117 #define LDO5_MASK_RESET			4
118 #define LDO6_MASK_RESET			5
119 #define VREF_DDR_MASK_RESET		6
120 
121 /* Main PMIC Control Register (MAIN_CONTROL_REG) */
122 #define ICC_EVENT_ENABLED		BIT(4)
123 #define PWRCTRL_POLARITY_HIGH		BIT(3)
124 #define PWRCTRL_PIN_VALID		BIT(2)
125 #define RESTART_REQUEST_ENABLED		BIT(1)
126 #define SOFTWARE_SWITCH_OFF_ENABLED	BIT(0)
127 
128 /* Main PMIC PADS Control Register (PADS_PULL_REG) */
129 #define WAKEUP_DETECTOR_DISABLED	BIT(4)
130 #define PWRCTRL_PD_ACTIVE		BIT(3)
131 #define PWRCTRL_PU_ACTIVE		BIT(2)
132 #define WAKEUP_PD_ACTIVE		BIT(1)
133 #define PONKEY_PU_ACTIVE		BIT(0)
134 
135 /* Main PMIC VINLOW Control Register (VIN_CONTROL_REGC DMSC) */
136 #define SWIN_DETECTOR_ENABLED		BIT(7)
137 #define SWOUT_DETECTOR_ENABLED          BIT(6)
138 #define VINLOW_HYST_MASK		0x3
139 #define VINLOW_HYST_SHIFT		4
140 #define VINLOW_THRESHOLD_MASK		0x7
141 #define VINLOW_THRESHOLD_SHIFT		1
142 #define VINLOW_ENABLED			0x01
143 #define VINLOW_CTRL_REG_MASK		0xFF
144 
145 /* USB Control Register */
146 #define BOOST_OVP_DISABLED		BIT(7)
147 #define VBUS_OTG_DETECTION_DISABLED	BIT(6)
148 #define OCP_LIMIT_HIGH			BIT(3)
149 #define SWIN_SWOUT_ENABLED		BIT(2)
150 #define USBSW_OTG_SWITCH_ENABLED	BIT(1)
151 
152 int stpmic1_powerctrl_on(void);
153 int stpmic1_switch_off(void);
154 int stpmic1_register_read(uint8_t register_id, uint8_t *value);
155 int stpmic1_register_write(uint8_t register_id, uint8_t value);
156 int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
157 int stpmic1_regulator_enable(const char *name);
158 int stpmic1_regulator_disable(const char *name);
159 uint8_t stpmic1_is_regulator_enabled(const char *name);
160 int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts);
161 int stpmic1_regulator_voltage_get(const char *name);
162 int stpmic1_regulator_pull_down_set(const char *name);
163 int stpmic1_regulator_mask_reset_set(const char *name);
164 void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
165 
166 int stpmic1_get_version(unsigned long *version);
167 void stpmic1_dump_regulators(void);
168 
169 #endif /* STPMIC1_H */
170