1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef A8K_PLAT_DEF_H 9 #define A8K_PLAT_DEF_H 10 11 #include <marvell_def.h> 12 13 #define MVEBU_PRIMARY_CPU 0x0 14 #define MVEBU_AP0 0x0 15 16 /* APN806 revision ID */ 17 #define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC) 18 #define GWD_IIDR2_REV_ID_OFFSET 12 19 #define GWD_IIDR2_REV_ID_MASK 0xF 20 #define GWD_IIDR2_CHIP_ID_OFFSET 20 21 #define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET) 22 23 #define CHIP_ID_AP806 0x806 24 #define CHIP_ID_AP807 0x807 25 26 #define COUNTER_FREQUENCY 25000000 27 28 #define MVEBU_REGS_BASE 0xF0000000 29 #define MVEBU_REGS_BASE_MASK 0xF0000000 30 #define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE 31 #define MVEBU_AP_IO_BASE(ap) 0xF2000000 32 #define MVEBU_CP_OFFSET 0x2000000 33 #define MVEBU_CP_REGS_BASE(cp_index) (MVEBU_AP_IO_BASE(0) + \ 34 (cp_index) * MVEBU_CP_OFFSET) 35 #define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000) 36 #define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE) 37 #define MVEBU_IO_WIN_GCR_OFFSET (0x70) 38 #define MVEBU_IO_WIN_MAX_WINS (7) 39 40 /* Misc SoC configurations Base */ 41 #define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300) 42 43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000) 44 #define MVEBU_CCU_MAX_WINS (8) 45 46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000) 47 #define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000) 48 #define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000) 49 #define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000) 50 #define MVEBU_CP_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 51 0x440000 + ((n) << 2)) 52 #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 53 0x440000 + ((n / 8) << 2)) 54 #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ 55 (MVEBU_CP_REGS_BASE(cp_index) + \ 56 0x440100 + ((n > 31) ? 0x40 : 0x00)) 57 #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ 58 (MVEBU_CP_REGS_BASE(cp_index) + \ 59 0x440104 + ((n > 31) ? 0x40 : 0x00)) 60 #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 61 0x440110 + ((n > 31) ? 0x40 : 0x00)) 62 #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2)) 63 #define MVEBU_AP_GPIO_REGS (MVEBU_RFU_BASE + 0x5040) 64 #define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10) 65 #define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000) 66 #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) 67 #define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) 68 69 #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 70 0x20080 + ((win) * 0x8)) 71 #define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 72 0x20084 + ((win) * 0x8)) 73 74 /* MCI indirect access definitions */ 75 #define MCI_MAX_UNIT_ID 2 76 /* SoC RFU / IHBx4 Control */ 77 #define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \ 78 0x4218 + (unit_id * 0x20)) 79 #define MCI_REMAP_OFF_SHIFT 8 80 81 #define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \ 82 ((index) * 0x1000000)) 83 84 #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000) 85 #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000) 86 #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000) 87 #define MVEBU_CP_DFX_OFFSET (0x400200) 88 89 /***************************************************************************** 90 * MVEBU memory map related constants 91 ***************************************************************************** 92 */ 93 /* Aggregate of all devices in the first GB */ 94 #define DEVICE0_BASE MVEBU_REGS_BASE 95 #define DEVICE0_SIZE 0x10000000 96 97 /***************************************************************************** 98 * GIC-400 & interrupt handling related constants 99 ***************************************************************************** 100 */ 101 /* Base MVEBU compatible GIC memory map */ 102 #define MVEBU_GICD_BASE 0x210000 103 #define MVEBU_GICC_BASE 0x220000 104 105 106 /***************************************************************************** 107 * AXI Configuration 108 ***************************************************************************** 109 */ 110 #define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4 111 #define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \ 112 MVEBU_AXI_ATTR_ARCACHE_OFFSET) 113 #define MVEBU_AXI_ATTR_ARDOMAIN_OFFSET 12 114 #define MVEBU_AXI_ATTR_ARDOMAIN_MASK (0x3 << \ 115 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET) 116 #define MVEBU_AXI_ATTR_AWCACHE_OFFSET 20 117 #define MVEBU_AXI_ATTR_AWCACHE_MASK (0xF << \ 118 MVEBU_AXI_ATTR_AWCACHE_OFFSET) 119 #define MVEBU_AXI_ATTR_AWDOMAIN_OFFSET 28 120 #define MVEBU_AXI_ATTR_AWDOMAIN_MASK (0x3 << \ 121 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET) 122 123 /* SATA MBUS to AXI configuration */ 124 #define MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET 1 125 #define MVEBU_SATA_M2A_AXI_ARCACHE_MASK (0xF << \ 126 MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET) 127 #define MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET 5 128 #define MVEBU_SATA_M2A_AXI_AWCACHE_MASK (0xF << \ 129 MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET) 130 131 /* ARM cache attributes */ 132 #define CACHE_ATTR_BUFFERABLE 0x1 133 #define CACHE_ATTR_CACHEABLE 0x2 134 #define CACHE_ATTR_READ_ALLOC 0x4 135 #define CACHE_ATTR_WRITE_ALLOC 0x8 136 /* Domain */ 137 #define DOMAIN_NON_SHAREABLE 0x0 138 #define DOMAIN_INNER_SHAREABLE 0x1 139 #define DOMAIN_OUTER_SHAREABLE 0x2 140 #define DOMAIN_SYSTEM_SHAREABLE 0x3 141 142 /************************************************************************ 143 * Required platform porting definitions common to all 144 * Management Compute SubSystems (MSS) 145 ************************************************************************ 146 */ 147 /* 148 * Load address of SCP_BL2 149 * SCP_BL2 is loaded to the same place as BL31. 150 * Once SCP_BL2 is transferred to the SCP, 151 * it is discarded and BL31 is loaded over the top. 152 */ 153 #ifdef SCP_IMAGE 154 #define SCP_BL2_BASE BL31_BASE 155 #define SCP_BL2_SIZE BL31_LIMIT 156 #endif 157 158 #ifndef __ASSEMBLER__ 159 enum ap806_sar_target_dev { 160 SAR_PIDI_MCIX2 = 0x0, 161 SAR_MCIX4 = 0x1, 162 SAR_SPI = 0x2, 163 SAR_SD = 0x3, 164 SAR_PIDI_MCIX2_BD = 0x4, /* BootRom disabled */ 165 SAR_MCIX4_DB = 0x5, /* BootRom disabled */ 166 SAR_SPI_DB = 0x6, /* BootRom disabled */ 167 SAR_EMMC = 0x7 168 }; 169 170 enum io_win_target_ids { 171 MCI_0_TID = 0x0, 172 MCI_1_TID = 0x1, 173 MCI_2_TID = 0x2, 174 PIDI_TID = 0x3, 175 SPI_TID = 0x4, 176 STM_TID = 0x5, 177 BOOTROM_TID = 0x6, 178 IO_WIN_MAX_TID 179 }; 180 181 enum ccu_target_ids { 182 IO_0_TID = 0x00, 183 DRAM_0_TID = 0x03, 184 IO_1_TID = 0x0F, 185 CFG_REG_TID = 0x10, 186 RAR_TID = 0x20, 187 SRAM_TID = 0x40, 188 DRAM_1_TID = 0xC0, 189 CCU_MAX_TID, 190 INVALID_TID = 0xFF 191 }; 192 #endif /* __ASSEMBLER__ */ 193 194 #endif /* A8K_PLAT_DEF_H */ 195