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26 
27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_
28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_
29 
30 #include "../globals-vixl.h"
31 
32 namespace vixl {
33 namespace aarch64 {
34 
35 const unsigned kNumberOfRegisters = 32;
36 const unsigned kNumberOfVRegisters = 32;
37 const unsigned kNumberOfZRegisters = kNumberOfVRegisters;
38 const unsigned kNumberOfPRegisters = 16;
39 // Callee saved registers are x21-x30(lr).
40 const int kNumberOfCalleeSavedRegisters = 10;
41 const int kFirstCalleeSavedRegisterIndex = 21;
42 // Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are
43 // still caller-saved.
44 const int kNumberOfCalleeSavedFPRegisters = 8;
45 const int kFirstCalleeSavedFPRegisterIndex = 8;
46 // All predicated instructions accept at least p0-p7 as the governing predicate.
47 const unsigned kNumberOfGoverningPRegisters = 8;
48 
49 // clang-format off
50 #define AARCH64_P_REGISTER_CODE_LIST(R)                                        \
51   R(0)  R(1)  R(2)  R(3)  R(4)  R(5)  R(6)  R(7)                               \
52   R(8)  R(9)  R(10) R(11) R(12) R(13) R(14) R(15)
53 
54 #define AARCH64_REGISTER_CODE_LIST(R)                                          \
55   R(0)  R(1)  R(2)  R(3)  R(4)  R(5)  R(6)  R(7)                               \
56   R(8)  R(9)  R(10) R(11) R(12) R(13) R(14) R(15)                              \
57   R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23)                              \
58   R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
59 
60 // SVE loads and stores use "w" instead of "s" for word-sized accesses, so the
61 // mapping from the load/store variant to constants like k*RegSize is irregular.
62 #define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \
63   V(b, B)                            \
64   V(h, H)                            \
65   V(w, S)                            \
66   V(d, D)
67 
68 // Sign-extending loads don't have double-word variants.
69 #define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \
70   V(b, B)                            \
71   V(h, H)                            \
72   V(w, S)
73 
74 #define INSTRUCTION_FIELDS_LIST(V_)                                          \
75 /* Register fields */                                                        \
76 V_(Rd, 4, 0, ExtractBits)         /* Destination register.                */ \
77 V_(Rn, 9, 5, ExtractBits)         /* First source register.               */ \
78 V_(Rm, 20, 16, ExtractBits)       /* Second source register.              */ \
79 V_(RmLow16, 19, 16, ExtractBits)  /* Second source register (code 0-15).  */ \
80 V_(Ra, 14, 10, ExtractBits)       /* Third source register.               */ \
81 V_(Rt, 4, 0, ExtractBits)         /* Load/store register.                 */ \
82 V_(Rt2, 14, 10, ExtractBits)      /* Load/store second register.          */ \
83 V_(Rs, 20, 16, ExtractBits)       /* Exclusive access status.             */ \
84 V_(Pt, 3, 0, ExtractBits)         /* Load/store register (p0-p7).         */ \
85 V_(Pd, 3, 0, ExtractBits)         /* SVE destination predicate register.  */ \
86 V_(Pn, 8, 5, ExtractBits)         /* SVE first source predicate register. */ \
87 V_(Pm, 19, 16, ExtractBits)       /* SVE second source predicate register.*/ \
88 V_(PgLow8, 12, 10, ExtractBits)   /* Governing predicate (p0-p7).         */ \
89                                                                              \
90 /* Common bits */                                                            \
91 V_(SixtyFourBits, 31, 31, ExtractBits)                                       \
92 V_(FlagsUpdate, 29, 29, ExtractBits)                                         \
93                                                                              \
94 /* PC relative addressing */                                                 \
95 V_(ImmPCRelHi, 23, 5, ExtractSignedBits)                                     \
96 V_(ImmPCRelLo, 30, 29, ExtractBits)                                          \
97                                                                              \
98 /* Add/subtract/logical shift register */                                    \
99 V_(ShiftDP, 23, 22, ExtractBits)                                             \
100 V_(ImmDPShift, 15, 10, ExtractBits)                                          \
101                                                                              \
102 /* Add/subtract immediate */                                                 \
103 V_(ImmAddSub, 21, 10, ExtractBits)                                           \
104 V_(ImmAddSubShift, 22, 22, ExtractBits)                                      \
105                                                                              \
106 /* Add/substract extend */                                                   \
107 V_(ImmExtendShift, 12, 10, ExtractBits)                                      \
108 V_(ExtendMode, 15, 13, ExtractBits)                                          \
109                                                                              \
110 /* Move wide */                                                              \
111 V_(ImmMoveWide, 20, 5, ExtractBits)                                          \
112 V_(ShiftMoveWide, 22, 21, ExtractBits)                                       \
113                                                                              \
114 /* Logical immediate, bitfield and extract */                                \
115 V_(BitN, 22, 22, ExtractBits)                                                \
116 V_(ImmRotate, 21, 16, ExtractBits)                                           \
117 V_(ImmSetBits, 15, 10, ExtractBits)                                          \
118 V_(ImmR, 21, 16, ExtractBits)                                                \
119 V_(ImmS, 15, 10, ExtractBits)                                                \
120                                                                              \
121 /* Test and branch immediate */                                              \
122 V_(ImmTestBranch, 18, 5, ExtractSignedBits)                                  \
123 V_(ImmTestBranchBit40, 23, 19, ExtractBits)                                  \
124 V_(ImmTestBranchBit5, 31, 31, ExtractBits)                                   \
125                                                                              \
126 /* Conditionals */                                                           \
127 V_(Condition, 15, 12, ExtractBits)                                           \
128 V_(ConditionBranch, 3, 0, ExtractBits)                                       \
129 V_(Nzcv, 3, 0, ExtractBits)                                                  \
130 V_(ImmCondCmp, 20, 16, ExtractBits)                                          \
131 V_(ImmCondBranch, 23, 5, ExtractSignedBits)                                  \
132                                                                              \
133 /* Floating point */                                                         \
134 V_(FPType, 23, 22, ExtractBits)                                              \
135 V_(ImmFP, 20, 13, ExtractBits)                                               \
136 V_(FPScale, 15, 10, ExtractBits)                                             \
137                                                                              \
138 /* Load Store */                                                             \
139 V_(ImmLS, 20, 12, ExtractSignedBits)                                         \
140 V_(ImmLSUnsigned, 21, 10, ExtractBits)                                       \
141 V_(ImmLSPair, 21, 15, ExtractSignedBits)                                     \
142 V_(ImmShiftLS, 12, 12, ExtractBits)                                          \
143 V_(LSOpc, 23, 22, ExtractBits)                                               \
144 V_(LSVector, 26, 26, ExtractBits)                                            \
145 V_(LSSize, 31, 30, ExtractBits)                                              \
146 V_(ImmPrefetchOperation, 4, 0, ExtractBits)                                  \
147 V_(PrefetchHint, 4, 3, ExtractBits)                                          \
148 V_(PrefetchTarget, 2, 1, ExtractBits)                                        \
149 V_(PrefetchStream, 0, 0, ExtractBits)                                        \
150 V_(ImmLSPACHi, 22, 22, ExtractSignedBits)                                    \
151 V_(ImmLSPACLo, 20, 12, ExtractBits)                                          \
152                                                                              \
153 /* Other immediates */                                                       \
154 V_(ImmUncondBranch, 25, 0, ExtractSignedBits)                                \
155 V_(ImmCmpBranch, 23, 5, ExtractSignedBits)                                   \
156 V_(ImmLLiteral, 23, 5, ExtractSignedBits)                                    \
157 V_(ImmException, 20, 5, ExtractBits)                                         \
158 V_(ImmHint, 11, 5, ExtractBits)                                              \
159 V_(ImmBarrierDomain, 11, 10, ExtractBits)                                    \
160 V_(ImmBarrierType, 9, 8, ExtractBits)                                        \
161 V_(ImmUdf, 15, 0, ExtractBits)                                               \
162                                                                              \
163 /* System (MRS, MSR, SYS) */                                                 \
164 V_(ImmSystemRegister, 20, 5, ExtractBits)                                    \
165 V_(SysO0, 19, 19, ExtractBits)                                               \
166 V_(SysOp, 18, 5, ExtractBits)                                                \
167 V_(SysOp0, 20, 19, ExtractBits)                                              \
168 V_(SysOp1, 18, 16, ExtractBits)                                              \
169 V_(SysOp2, 7, 5, ExtractBits)                                                \
170 V_(CRn, 15, 12, ExtractBits)                                                 \
171 V_(CRm, 11, 8, ExtractBits)                                                  \
172 V_(ImmRMIFRotation, 20, 15, ExtractBits)                                     \
173                                                                              \
174 /* Load-/store-exclusive */                                                  \
175 V_(LdStXLoad, 22, 22, ExtractBits)                                           \
176 V_(LdStXNotExclusive, 23, 23, ExtractBits)                                   \
177 V_(LdStXAcquireRelease, 15, 15, ExtractBits)                                 \
178 V_(LdStXSizeLog2, 31, 30, ExtractBits)                                       \
179 V_(LdStXPair, 21, 21, ExtractBits)                                           \
180                                                                              \
181 /* NEON generic fields */                                                    \
182 V_(NEONQ, 30, 30, ExtractBits)                                               \
183 V_(NEONSize, 23, 22, ExtractBits)                                            \
184 V_(NEONLSSize, 11, 10, ExtractBits)                                          \
185 V_(NEONS, 12, 12, ExtractBits)                                               \
186 V_(NEONL, 21, 21, ExtractBits)                                               \
187 V_(NEONM, 20, 20, ExtractBits)                                               \
188 V_(NEONH, 11, 11, ExtractBits)                                               \
189 V_(ImmNEONExt, 14, 11, ExtractBits)                                          \
190 V_(ImmNEON5, 20, 16, ExtractBits)                                            \
191 V_(ImmNEON4, 14, 11, ExtractBits)                                            \
192                                                                              \
193 /* NEON extra fields */                                                      \
194 V_(ImmRotFcadd, 12, 12, ExtractBits)                                         \
195 V_(ImmRotFcmlaVec, 12, 11, ExtractBits)                                      \
196 V_(ImmRotFcmlaSca, 14, 13, ExtractBits)                                      \
197                                                                              \
198 /* NEON Modified Immediate fields */                                         \
199 V_(ImmNEONabc, 18, 16, ExtractBits)                                          \
200 V_(ImmNEONdefgh, 9, 5, ExtractBits)                                          \
201 V_(NEONModImmOp, 29, 29, ExtractBits)                                        \
202 V_(NEONCmode, 15, 12, ExtractBits)                                           \
203                                                                              \
204 /* NEON Shift Immediate fields */                                            \
205 V_(ImmNEONImmhImmb, 22, 16, ExtractBits)                                     \
206 V_(ImmNEONImmh, 22, 19, ExtractBits)                                         \
207 V_(ImmNEONImmb, 18, 16, ExtractBits)                                         \
208                                                                              \
209 /* SVE generic fields */                                                     \
210 V_(SVESize, 23, 22, ExtractBits)                                             \
211 V_(ImmSVEVLScale, 10, 5, ExtractSignedBits)                                  \
212 V_(ImmSVEIntWideSigned, 12, 5, ExtractSignedBits)                            \
213 V_(ImmSVEIntWideUnsigned, 12, 5, ExtractBits)                                \
214 V_(ImmSVEPredicateConstraint, 9, 5, ExtractBits)                             \
215                                                                              \
216 /* SVE Bitwise Immediate bitfield */                                         \
217 V_(SVEBitN, 17, 17, ExtractBits)                                             \
218 V_(SVEImmRotate, 16, 11, ExtractBits)                                        \
219 V_(SVEImmSetBits, 10, 5, ExtractBits)                                        \
220                                                                              \
221 V_(SVEImmPrefetchOperation, 3, 0, ExtractBits)                               \
222 V_(SVEPrefetchHint, 3, 3, ExtractBits)
223 
224 // clang-format on
225 
226 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
227   /* NZCV */                                \
228   V_(Flags, 31, 28, ExtractBits)            \
229   V_(N, 31, 31, ExtractBits)                \
230   V_(Z, 30, 30, ExtractBits)                \
231   V_(C, 29, 29, ExtractBits)                \
232   V_(V, 28, 28, ExtractBits)                \
233   M_(NZCV, Flags_mask)                      \
234   /* FPCR */                                \
235   V_(AHP, 26, 26, ExtractBits)              \
236   V_(DN, 25, 25, ExtractBits)               \
237   V_(FZ, 24, 24, ExtractBits)               \
238   V_(RMode, 23, 22, ExtractBits)            \
239   M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
240 
241 // Fields offsets.
242 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
243   const int Name##_offset = LowBit;                      \
244   const int Name##_width = HighBit - LowBit + 1;         \
245   const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
246 #define NOTHING(A, B)
247 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
248 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
249 #undef NOTHING
250 #undef DECLARE_FIELDS_BITS
251 
252 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
253 // from ImmPCRelLo and ImmPCRelHi.
254 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
255 
256 // Disable `clang-format` for the `enum`s below. We care about the manual
257 // formatting that `clang-format` would destroy.
258 // clang-format off
259 
260 // Condition codes.
261 enum Condition {
262   eq = 0,   // Z set            Equal.
263   ne = 1,   // Z clear          Not equal.
264   cs = 2,   // C set            Carry set.
265   cc = 3,   // C clear          Carry clear.
266   mi = 4,   // N set            Negative.
267   pl = 5,   // N clear          Positive or zero.
268   vs = 6,   // V set            Overflow.
269   vc = 7,   // V clear          No overflow.
270   hi = 8,   // C set, Z clear   Unsigned higher.
271   ls = 9,   // C clear or Z set Unsigned lower or same.
272   ge = 10,  // N == V           Greater or equal.
273   lt = 11,  // N != V           Less than.
274   gt = 12,  // Z clear, N == V  Greater than.
275   le = 13,  // Z set or N != V  Less then or equal
276   al = 14,  //                  Always.
277   nv = 15,  // Behaves as always/al.
278 
279   // Aliases.
280   hs = cs,  // C set            Unsigned higher or same.
281   lo = cc,  // C clear          Unsigned lower.
282 
283   // Floating-point additional condition code.
284   uo,       // Unordered comparison.
285 
286   // SVE predicate condition aliases.
287   sve_none  = eq,  // No active elements were true.
288   sve_any   = ne,  // An active element was true.
289   sve_nlast = cs,  // The last element was not true.
290   sve_last  = cc,  // The last element was true.
291   sve_first = mi,  // The first element was true.
292   sve_nfrst = pl,  // The first element was not true.
293   sve_pmore = hi,  // An active element was true but not the last element.
294   sve_plast = ls,  // The last active element was true or no active elements were true.
295   sve_tcont = ge,  // CTERM termination condition not deleted.
296   sve_tstop = lt   // CTERM termination condition deleted.
297 };
298 
InvertCondition(Condition cond)299 inline Condition InvertCondition(Condition cond) {
300   // Conditions al and nv behave identically, as "always true". They can't be
301   // inverted, because there is no "always false" condition.
302   VIXL_ASSERT((cond != al) && (cond != nv));
303   return static_cast<Condition>(cond ^ 1);
304 }
305 
306 enum FPTrapFlags {
307   EnableTrap   = 1,
308   DisableTrap = 0
309 };
310 
311 enum FlagsUpdate {
312   SetFlags   = 1,
313   LeaveFlags = 0
314 };
315 
316 enum StatusFlags {
317   NoFlag    = 0,
318 
319   // Derive the flag combinations from the system register bit descriptions.
320   NFlag     = N_mask,
321   ZFlag     = Z_mask,
322   CFlag     = C_mask,
323   VFlag     = V_mask,
324   NZFlag    = NFlag | ZFlag,
325   NCFlag    = NFlag | CFlag,
326   NVFlag    = NFlag | VFlag,
327   ZCFlag    = ZFlag | CFlag,
328   ZVFlag    = ZFlag | VFlag,
329   CVFlag    = CFlag | VFlag,
330   NZCFlag   = NFlag | ZFlag | CFlag,
331   NZVFlag   = NFlag | ZFlag | VFlag,
332   NCVFlag   = NFlag | CFlag | VFlag,
333   ZCVFlag   = ZFlag | CFlag | VFlag,
334   NZCVFlag  = NFlag | ZFlag | CFlag | VFlag,
335 
336   // Floating-point comparison results.
337   FPEqualFlag       = ZCFlag,
338   FPLessThanFlag    = NFlag,
339   FPGreaterThanFlag = CFlag,
340   FPUnorderedFlag   = CVFlag,
341 
342   // SVE condition flags.
343   SVEFirstFlag   = NFlag,
344   SVENoneFlag    = ZFlag,
345   SVENotLastFlag = CFlag
346 };
347 
348 enum Shift {
349   NO_SHIFT = -1,
350   LSL = 0x0,
351   LSR = 0x1,
352   ASR = 0x2,
353   ROR = 0x3,
354   MSL = 0x4
355 };
356 
357 enum Extend {
358   NO_EXTEND = -1,
359   UXTB      = 0,
360   UXTH      = 1,
361   UXTW      = 2,
362   UXTX      = 3,
363   SXTB      = 4,
364   SXTH      = 5,
365   SXTW      = 6,
366   SXTX      = 7
367 };
368 
369 enum SVEOffsetModifier {
370   NO_SVE_OFFSET_MODIFIER,
371   // Multiply (each element of) the offset by either the vector or predicate
372   // length, according to the context.
373   SVE_MUL_VL,
374   // Shift or extend modifiers (as in `Shift` or `Extend`).
375   SVE_LSL,
376   SVE_UXTW,
377   SVE_SXTW
378 };
379 
380 enum SystemHint {
381   NOP    = 0,
382   YIELD  = 1,
383   WFE    = 2,
384   WFI    = 3,
385   SEV    = 4,
386   SEVL   = 5,
387   ESB    = 16,
388   CSDB   = 20,
389   BTI    = 32,
390   BTI_c  = 34,
391   BTI_j  = 36,
392   BTI_jc = 38
393 };
394 
395 enum BranchTargetIdentifier {
396   EmitBTI_none = NOP,
397   EmitBTI = BTI,
398   EmitBTI_c = BTI_c,
399   EmitBTI_j = BTI_j,
400   EmitBTI_jc = BTI_jc,
401 
402   // These correspond to the values of the CRm:op2 fields in the equivalent HINT
403   // instruction.
404   EmitPACIASP = 25,
405   EmitPACIBSP = 27
406 };
407 
408 enum BarrierDomain {
409   OuterShareable = 0,
410   NonShareable   = 1,
411   InnerShareable = 2,
412   FullSystem     = 3
413 };
414 
415 enum BarrierType {
416   BarrierOther  = 0,
417   BarrierReads  = 1,
418   BarrierWrites = 2,
419   BarrierAll    = 3
420 };
421 
422 enum PrefetchOperation {
423   PLDL1KEEP = 0x00,
424   PLDL1STRM = 0x01,
425   PLDL2KEEP = 0x02,
426   PLDL2STRM = 0x03,
427   PLDL3KEEP = 0x04,
428   PLDL3STRM = 0x05,
429 
430   PrfUnallocated06 = 0x06,
431   PrfUnallocated07 = 0x07,
432 
433   PLIL1KEEP = 0x08,
434   PLIL1STRM = 0x09,
435   PLIL2KEEP = 0x0a,
436   PLIL2STRM = 0x0b,
437   PLIL3KEEP = 0x0c,
438   PLIL3STRM = 0x0d,
439 
440   PrfUnallocated0e = 0x0e,
441   PrfUnallocated0f = 0x0f,
442 
443   PSTL1KEEP = 0x10,
444   PSTL1STRM = 0x11,
445   PSTL2KEEP = 0x12,
446   PSTL2STRM = 0x13,
447   PSTL3KEEP = 0x14,
448   PSTL3STRM = 0x15,
449 
450   PrfUnallocated16 = 0x16,
451   PrfUnallocated17 = 0x17,
452   PrfUnallocated18 = 0x18,
453   PrfUnallocated19 = 0x19,
454   PrfUnallocated1a = 0x1a,
455   PrfUnallocated1b = 0x1b,
456   PrfUnallocated1c = 0x1c,
457   PrfUnallocated1d = 0x1d,
458   PrfUnallocated1e = 0x1e,
459   PrfUnallocated1f = 0x1f,
460 };
461 
IsNamedPrefetchOperation(int op)462 constexpr bool IsNamedPrefetchOperation(int op) {
463   return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) ||
464       ((op >= PLIL1KEEP) && (op <= PLIL3STRM)) ||
465       ((op >= PSTL1KEEP) && (op <= PSTL3STRM));
466 }
467 
468 enum BType {
469   // Set when executing any instruction on a guarded page, except those cases
470   // listed below.
471   DefaultBType = 0,
472 
473   // Set when an indirect branch is taken from an unguarded page to a guarded
474   // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0".
475   BranchFromUnguardedOrToIP = 1,
476 
477   // Set when an indirect branch and link (call) is taken, eg. "blr x0".
478   BranchAndLink = 2,
479 
480   // Set when an indirect branch is taken from a guarded page to a register
481   // that is not ip0 or ip1 (x16 or x17), eg, "br x0".
482   BranchFromGuardedNotToIP = 3
483 };
484 
485 template<int op0, int op1, int crn, int crm, int op2>
486 class SystemRegisterEncoder {
487  public:
488   static const uint32_t value =
489       ((op0 << SysO0_offset) |
490        (op1 << SysOp1_offset) |
491        (crn << CRn_offset) |
492        (crm << CRm_offset) |
493        (op2 << SysOp2_offset)) >> ImmSystemRegister_offset;
494 };
495 
496 // System/special register names.
497 // This information is not encoded as one field but as the concatenation of
498 // multiple fields (Op0, Op1, Crn, Crm, Op2).
499 enum SystemRegister {
500   NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
501   FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value,
502   RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value,    // Random number.
503   RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value   // Reseeded random number.
504 };
505 
506 template<int op1, int crn, int crm, int op2>
507 class CacheOpEncoder {
508  public:
509   static const uint32_t value =
510       ((op1 << SysOp1_offset) |
511        (crn << CRn_offset) |
512        (crm << CRm_offset) |
513        (op2 << SysOp2_offset)) >> SysOp_offset;
514 };
515 
516 enum InstructionCacheOp {
517   IVAU = CacheOpEncoder<3, 7, 5, 1>::value
518 };
519 
520 enum DataCacheOp {
521   CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
522   CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
523   CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
524   CVADP = CacheOpEncoder<3, 7, 13, 1>::value,
525   CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
526   ZVA = CacheOpEncoder<3, 7, 4, 1>::value
527 };
528 
529 // Some SVE instructions support a predicate constraint pattern. This is
530 // interpreted as a VL-dependent value, and is typically used to initialise
531 // predicates, or to otherwise limit the number of processed elements.
532 enum SVEPredicateConstraint {
533   // Select 2^N elements, for the largest possible N.
534   SVE_POW2 = 0x0,
535   // Each VL<N> selects exactly N elements if possible, or zero if N is greater
536   // than the number of elements. Note that the encoding values for VL<N> are
537   // not linearly related to N.
538   SVE_VL1 = 0x1,
539   SVE_VL2 = 0x2,
540   SVE_VL3 = 0x3,
541   SVE_VL4 = 0x4,
542   SVE_VL5 = 0x5,
543   SVE_VL6 = 0x6,
544   SVE_VL7 = 0x7,
545   SVE_VL8 = 0x8,
546   SVE_VL16 = 0x9,
547   SVE_VL32 = 0xa,
548   SVE_VL64 = 0xb,
549   SVE_VL128 = 0xc,
550   SVE_VL256 = 0xd,
551   // Each MUL<N> selects the largest multiple of N elements that the vector
552   // length supports. Note that for D-sized lanes, this can be zero.
553   SVE_MUL4 = 0x1d,
554   SVE_MUL3 = 0x1e,
555   // Select all elements.
556   SVE_ALL = 0x1f
557 };
558 
559 // Instruction enumerations.
560 //
561 // These are the masks that define a class of instructions, and the list of
562 // instructions within each class. Each enumeration has a Fixed, FMask and
563 // Mask value.
564 //
565 // Fixed: The fixed bits in this instruction class.
566 // FMask: The mask used to extract the fixed bits in the class.
567 // Mask:  The mask used to identify the instructions within a class.
568 //
569 // The enumerations can be used like this:
570 //
571 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
572 // switch(instr->Mask(PCRelAddressingMask)) {
573 //   case ADR:  Format("adr 'Xd, 'AddrPCRelByte"); break;
574 //   case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
575 //   default:   printf("Unknown instruction\n");
576 // }
577 
578 
579 // Generic fields.
580 enum GenericInstrField {
581   SixtyFourBits        = 0x80000000,
582   ThirtyTwoBits        = 0x00000000,
583 
584   FPTypeMask           = 0x00C00000,
585   FP16                 = 0x00C00000,
586   FP32                 = 0x00000000,
587   FP64                 = 0x00400000
588 };
589 
590 enum NEONFormatField {
591   NEONFormatFieldMask   = 0x40C00000,
592   NEON_Q                = 0x40000000,
593   NEON_8B               = 0x00000000,
594   NEON_16B              = NEON_8B | NEON_Q,
595   NEON_4H               = 0x00400000,
596   NEON_8H               = NEON_4H | NEON_Q,
597   NEON_2S               = 0x00800000,
598   NEON_4S               = NEON_2S | NEON_Q,
599   NEON_1D               = 0x00C00000,
600   NEON_2D               = 0x00C00000 | NEON_Q
601 };
602 
603 enum NEONFPFormatField {
604   NEONFPFormatFieldMask = 0x40400000,
605   NEON_FP_4H            = FP16,
606   NEON_FP_2S            = FP32,
607   NEON_FP_8H            = FP16 | NEON_Q,
608   NEON_FP_4S            = FP32 | NEON_Q,
609   NEON_FP_2D            = FP64 | NEON_Q
610 };
611 
612 enum NEONLSFormatField {
613   NEONLSFormatFieldMask = 0x40000C00,
614   LS_NEON_8B            = 0x00000000,
615   LS_NEON_16B           = LS_NEON_8B | NEON_Q,
616   LS_NEON_4H            = 0x00000400,
617   LS_NEON_8H            = LS_NEON_4H | NEON_Q,
618   LS_NEON_2S            = 0x00000800,
619   LS_NEON_4S            = LS_NEON_2S | NEON_Q,
620   LS_NEON_1D            = 0x00000C00,
621   LS_NEON_2D            = LS_NEON_1D | NEON_Q
622 };
623 
624 enum NEONScalarFormatField {
625   NEONScalarFormatFieldMask = 0x00C00000,
626   NEONScalar                = 0x10000000,
627   NEON_B                    = 0x00000000,
628   NEON_H                    = 0x00400000,
629   NEON_S                    = 0x00800000,
630   NEON_D                    = 0x00C00000
631 };
632 
633 enum SVESizeField {
634   SVESizeFieldMask = 0x00C00000,
635   SVE_B            = 0x00000000,
636   SVE_H            = 0x00400000,
637   SVE_S            = 0x00800000,
638   SVE_D            = 0x00C00000
639 };
640 
641 // PC relative addressing.
642 enum PCRelAddressingOp {
643   PCRelAddressingFixed = 0x10000000,
644   PCRelAddressingFMask = 0x1F000000,
645   PCRelAddressingMask  = 0x9F000000,
646   ADR                  = PCRelAddressingFixed | 0x00000000,
647   ADRP                 = PCRelAddressingFixed | 0x80000000
648 };
649 
650 // Add/sub (immediate, shifted and extended.)
651 const int kSFOffset = 31;
652 enum AddSubOp {
653   AddSubOpMask      = 0x60000000,
654   AddSubSetFlagsBit = 0x20000000,
655   ADD               = 0x00000000,
656   ADDS              = ADD | AddSubSetFlagsBit,
657   SUB               = 0x40000000,
658   SUBS              = SUB | AddSubSetFlagsBit
659 };
660 
661 #define ADD_SUB_OP_LIST(V)  \
662   V(ADD),                   \
663   V(ADDS),                  \
664   V(SUB),                   \
665   V(SUBS)
666 
667 enum AddSubImmediateOp {
668   AddSubImmediateFixed = 0x11000000,
669   AddSubImmediateFMask = 0x1F800000,
670   AddSubImmediateMask  = 0xFF800000,
671   #define ADD_SUB_IMMEDIATE(A)           \
672   A##_w_imm = AddSubImmediateFixed | A,  \
673   A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
674   ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
675   #undef ADD_SUB_IMMEDIATE
676 };
677 
678 enum AddSubShiftedOp {
679   AddSubShiftedFixed   = 0x0B000000,
680   AddSubShiftedFMask   = 0x1F200000,
681   AddSubShiftedMask    = 0xFF200000,
682   #define ADD_SUB_SHIFTED(A)             \
683   A##_w_shift = AddSubShiftedFixed | A,  \
684   A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
685   ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
686   #undef ADD_SUB_SHIFTED
687 };
688 
689 enum AddSubExtendedOp {
690   AddSubExtendedFixed  = 0x0B200000,
691   AddSubExtendedFMask  = 0x1F200000,
692   AddSubExtendedMask   = 0xFFE00000,
693   #define ADD_SUB_EXTENDED(A)           \
694   A##_w_ext = AddSubExtendedFixed | A,  \
695   A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
696   ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
697   #undef ADD_SUB_EXTENDED
698 };
699 
700 // Add/sub with carry.
701 enum AddSubWithCarryOp {
702   AddSubWithCarryFixed = 0x1A000000,
703   AddSubWithCarryFMask = 0x1FE00000,
704   AddSubWithCarryMask  = 0xFFE0FC00,
705   ADC_w                = AddSubWithCarryFixed | ADD,
706   ADC_x                = AddSubWithCarryFixed | ADD | SixtyFourBits,
707   ADC                  = ADC_w,
708   ADCS_w               = AddSubWithCarryFixed | ADDS,
709   ADCS_x               = AddSubWithCarryFixed | ADDS | SixtyFourBits,
710   SBC_w                = AddSubWithCarryFixed | SUB,
711   SBC_x                = AddSubWithCarryFixed | SUB | SixtyFourBits,
712   SBC                  = SBC_w,
713   SBCS_w               = AddSubWithCarryFixed | SUBS,
714   SBCS_x               = AddSubWithCarryFixed | SUBS | SixtyFourBits
715 };
716 
717 // Rotate right into flags.
718 enum RotateRightIntoFlagsOp {
719   RotateRightIntoFlagsFixed = 0x1A000400,
720   RotateRightIntoFlagsFMask = 0x1FE07C00,
721   RotateRightIntoFlagsMask  = 0xFFE07C10,
722   RMIF                      = RotateRightIntoFlagsFixed | 0xA0000000
723 };
724 
725 // Evaluate into flags.
726 enum EvaluateIntoFlagsOp {
727   EvaluateIntoFlagsFixed = 0x1A000800,
728   EvaluateIntoFlagsFMask = 0x1FE03C00,
729   EvaluateIntoFlagsMask  = 0xFFE07C1F,
730   SETF8                  = EvaluateIntoFlagsFixed | 0x2000000D,
731   SETF16                 = EvaluateIntoFlagsFixed | 0x2000400D
732 };
733 
734 
735 // Logical (immediate and shifted register).
736 enum LogicalOp {
737   LogicalOpMask = 0x60200000,
738   NOT   = 0x00200000,
739   AND   = 0x00000000,
740   BIC   = AND | NOT,
741   ORR   = 0x20000000,
742   ORN   = ORR | NOT,
743   EOR   = 0x40000000,
744   EON   = EOR | NOT,
745   ANDS  = 0x60000000,
746   BICS  = ANDS | NOT
747 };
748 
749 // Logical immediate.
750 enum LogicalImmediateOp {
751   LogicalImmediateFixed = 0x12000000,
752   LogicalImmediateFMask = 0x1F800000,
753   LogicalImmediateMask  = 0xFF800000,
754   AND_w_imm   = LogicalImmediateFixed | AND,
755   AND_x_imm   = LogicalImmediateFixed | AND | SixtyFourBits,
756   ORR_w_imm   = LogicalImmediateFixed | ORR,
757   ORR_x_imm   = LogicalImmediateFixed | ORR | SixtyFourBits,
758   EOR_w_imm   = LogicalImmediateFixed | EOR,
759   EOR_x_imm   = LogicalImmediateFixed | EOR | SixtyFourBits,
760   ANDS_w_imm  = LogicalImmediateFixed | ANDS,
761   ANDS_x_imm  = LogicalImmediateFixed | ANDS | SixtyFourBits
762 };
763 
764 // Logical shifted register.
765 enum LogicalShiftedOp {
766   LogicalShiftedFixed = 0x0A000000,
767   LogicalShiftedFMask = 0x1F000000,
768   LogicalShiftedMask  = 0xFF200000,
769   AND_w               = LogicalShiftedFixed | AND,
770   AND_x               = LogicalShiftedFixed | AND | SixtyFourBits,
771   AND_shift           = AND_w,
772   BIC_w               = LogicalShiftedFixed | BIC,
773   BIC_x               = LogicalShiftedFixed | BIC | SixtyFourBits,
774   BIC_shift           = BIC_w,
775   ORR_w               = LogicalShiftedFixed | ORR,
776   ORR_x               = LogicalShiftedFixed | ORR | SixtyFourBits,
777   ORR_shift           = ORR_w,
778   ORN_w               = LogicalShiftedFixed | ORN,
779   ORN_x               = LogicalShiftedFixed | ORN | SixtyFourBits,
780   ORN_shift           = ORN_w,
781   EOR_w               = LogicalShiftedFixed | EOR,
782   EOR_x               = LogicalShiftedFixed | EOR | SixtyFourBits,
783   EOR_shift           = EOR_w,
784   EON_w               = LogicalShiftedFixed | EON,
785   EON_x               = LogicalShiftedFixed | EON | SixtyFourBits,
786   EON_shift           = EON_w,
787   ANDS_w              = LogicalShiftedFixed | ANDS,
788   ANDS_x              = LogicalShiftedFixed | ANDS | SixtyFourBits,
789   ANDS_shift          = ANDS_w,
790   BICS_w              = LogicalShiftedFixed | BICS,
791   BICS_x              = LogicalShiftedFixed | BICS | SixtyFourBits,
792   BICS_shift          = BICS_w
793 };
794 
795 // Move wide immediate.
796 enum MoveWideImmediateOp {
797   MoveWideImmediateFixed = 0x12800000,
798   MoveWideImmediateFMask = 0x1F800000,
799   MoveWideImmediateMask  = 0xFF800000,
800   MOVN                   = 0x00000000,
801   MOVZ                   = 0x40000000,
802   MOVK                   = 0x60000000,
803   MOVN_w                 = MoveWideImmediateFixed | MOVN,
804   MOVN_x                 = MoveWideImmediateFixed | MOVN | SixtyFourBits,
805   MOVZ_w                 = MoveWideImmediateFixed | MOVZ,
806   MOVZ_x                 = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
807   MOVK_w                 = MoveWideImmediateFixed | MOVK,
808   MOVK_x                 = MoveWideImmediateFixed | MOVK | SixtyFourBits
809 };
810 
811 // Bitfield.
812 const int kBitfieldNOffset = 22;
813 enum BitfieldOp {
814   BitfieldFixed = 0x13000000,
815   BitfieldFMask = 0x1F800000,
816   BitfieldMask  = 0xFF800000,
817   SBFM_w        = BitfieldFixed | 0x00000000,
818   SBFM_x        = BitfieldFixed | 0x80000000,
819   SBFM          = SBFM_w,
820   BFM_w         = BitfieldFixed | 0x20000000,
821   BFM_x         = BitfieldFixed | 0xA0000000,
822   BFM           = BFM_w,
823   UBFM_w        = BitfieldFixed | 0x40000000,
824   UBFM_x        = BitfieldFixed | 0xC0000000,
825   UBFM          = UBFM_w
826   // Bitfield N field.
827 };
828 
829 // Extract.
830 enum ExtractOp {
831   ExtractFixed = 0x13800000,
832   ExtractFMask = 0x1F800000,
833   ExtractMask  = 0xFFA00000,
834   EXTR_w       = ExtractFixed | 0x00000000,
835   EXTR_x       = ExtractFixed | 0x80000000,
836   EXTR         = EXTR_w
837 };
838 
839 // Unconditional branch.
840 enum UnconditionalBranchOp {
841   UnconditionalBranchFixed = 0x14000000,
842   UnconditionalBranchFMask = 0x7C000000,
843   UnconditionalBranchMask  = 0xFC000000,
844   B                        = UnconditionalBranchFixed | 0x00000000,
845   BL                       = UnconditionalBranchFixed | 0x80000000
846 };
847 
848 // Unconditional branch to register.
849 enum UnconditionalBranchToRegisterOp {
850   UnconditionalBranchToRegisterFixed = 0xD6000000,
851   UnconditionalBranchToRegisterFMask = 0xFE000000,
852   UnconditionalBranchToRegisterMask  = 0xFFFFFC00,
853   BR      = UnconditionalBranchToRegisterFixed | 0x001F0000,
854   BLR     = UnconditionalBranchToRegisterFixed | 0x003F0000,
855   RET     = UnconditionalBranchToRegisterFixed | 0x005F0000,
856 
857   BRAAZ  = UnconditionalBranchToRegisterFixed | 0x001F0800,
858   BRABZ  = UnconditionalBranchToRegisterFixed | 0x001F0C00,
859   BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800,
860   BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00,
861   RETAA  = UnconditionalBranchToRegisterFixed | 0x005F0800,
862   RETAB  = UnconditionalBranchToRegisterFixed | 0x005F0C00,
863   BRAA   = UnconditionalBranchToRegisterFixed | 0x011F0800,
864   BRAB   = UnconditionalBranchToRegisterFixed | 0x011F0C00,
865   BLRAA  = UnconditionalBranchToRegisterFixed | 0x013F0800,
866   BLRAB  = UnconditionalBranchToRegisterFixed | 0x013F0C00
867 };
868 
869 // Compare and branch.
870 enum CompareBranchOp {
871   CompareBranchFixed = 0x34000000,
872   CompareBranchFMask = 0x7E000000,
873   CompareBranchMask  = 0xFF000000,
874   CBZ_w              = CompareBranchFixed | 0x00000000,
875   CBZ_x              = CompareBranchFixed | 0x80000000,
876   CBZ                = CBZ_w,
877   CBNZ_w             = CompareBranchFixed | 0x01000000,
878   CBNZ_x             = CompareBranchFixed | 0x81000000,
879   CBNZ               = CBNZ_w
880 };
881 
882 // Test and branch.
883 enum TestBranchOp {
884   TestBranchFixed = 0x36000000,
885   TestBranchFMask = 0x7E000000,
886   TestBranchMask  = 0x7F000000,
887   TBZ             = TestBranchFixed | 0x00000000,
888   TBNZ            = TestBranchFixed | 0x01000000
889 };
890 
891 // Conditional branch.
892 enum ConditionalBranchOp {
893   ConditionalBranchFixed = 0x54000000,
894   ConditionalBranchFMask = 0xFE000000,
895   ConditionalBranchMask  = 0xFF000010,
896   B_cond                 = ConditionalBranchFixed | 0x00000000
897 };
898 
899 // System.
900 // System instruction encoding is complicated because some instructions use op
901 // and CR fields to encode parameters. To handle this cleanly, the system
902 // instructions are split into more than one enum.
903 
904 enum SystemOp {
905   SystemFixed = 0xD5000000,
906   SystemFMask = 0xFFC00000
907 };
908 
909 enum SystemSysRegOp {
910   SystemSysRegFixed = 0xD5100000,
911   SystemSysRegFMask = 0xFFD00000,
912   SystemSysRegMask  = 0xFFF00000,
913   MRS               = SystemSysRegFixed | 0x00200000,
914   MSR               = SystemSysRegFixed | 0x00000000
915 };
916 
917 enum SystemPStateOp {
918   SystemPStateFixed = 0xD5004000,
919   SystemPStateFMask = 0xFFF8F000,
920   SystemPStateMask  = 0xFFFFF0FF,
921   CFINV             = SystemPStateFixed | 0x0000001F,
922   XAFLAG            = SystemPStateFixed | 0x0000003F,
923   AXFLAG            = SystemPStateFixed | 0x0000005F
924 };
925 
926 enum SystemHintOp {
927   SystemHintFixed = 0xD503201F,
928   SystemHintFMask = 0xFFFFF01F,
929   SystemHintMask  = 0xFFFFF01F,
930   HINT            = SystemHintFixed | 0x00000000
931 };
932 
933 enum SystemSysOp {
934   SystemSysFixed  = 0xD5080000,
935   SystemSysFMask  = 0xFFF80000,
936   SystemSysMask   = 0xFFF80000,
937   SYS             = SystemSysFixed | 0x00000000
938 };
939 
940 // Exception.
941 enum ExceptionOp {
942   ExceptionFixed = 0xD4000000,
943   ExceptionFMask = 0xFF000000,
944   ExceptionMask  = 0xFFE0001F,
945   HLT            = ExceptionFixed | 0x00400000,
946   BRK            = ExceptionFixed | 0x00200000,
947   SVC            = ExceptionFixed | 0x00000001,
948   HVC            = ExceptionFixed | 0x00000002,
949   SMC            = ExceptionFixed | 0x00000003,
950   DCPS1          = ExceptionFixed | 0x00A00001,
951   DCPS2          = ExceptionFixed | 0x00A00002,
952   DCPS3          = ExceptionFixed | 0x00A00003
953 };
954 
955 enum MemBarrierOp {
956   MemBarrierFixed = 0xD503309F,
957   MemBarrierFMask = 0xFFFFF09F,
958   MemBarrierMask  = 0xFFFFF0FF,
959   DSB             = MemBarrierFixed | 0x00000000,
960   DMB             = MemBarrierFixed | 0x00000020,
961   ISB             = MemBarrierFixed | 0x00000040
962 };
963 
964 enum SystemExclusiveMonitorOp {
965   SystemExclusiveMonitorFixed = 0xD503305F,
966   SystemExclusiveMonitorFMask = 0xFFFFF0FF,
967   SystemExclusiveMonitorMask  = 0xFFFFF0FF,
968   CLREX                       = SystemExclusiveMonitorFixed
969 };
970 
971 enum SystemPAuthOp {
972   SystemPAuthFixed = 0xD503211F,
973   SystemPAuthFMask = 0xFFFFFD1F,
974   SystemPAuthMask  = 0xFFFFFFFF,
975   PACIA1716 = SystemPAuthFixed | 0x00000100,
976   PACIB1716 = SystemPAuthFixed | 0x00000140,
977   AUTIA1716 = SystemPAuthFixed | 0x00000180,
978   AUTIB1716 = SystemPAuthFixed | 0x000001C0,
979   PACIAZ    = SystemPAuthFixed | 0x00000300,
980   PACIASP   = SystemPAuthFixed | 0x00000320,
981   PACIBZ    = SystemPAuthFixed | 0x00000340,
982   PACIBSP   = SystemPAuthFixed | 0x00000360,
983   AUTIAZ    = SystemPAuthFixed | 0x00000380,
984   AUTIASP   = SystemPAuthFixed | 0x000003A0,
985   AUTIBZ    = SystemPAuthFixed | 0x000003C0,
986   AUTIBSP   = SystemPAuthFixed | 0x000003E0,
987 
988   // XPACLRI has the same fixed mask as System Hints and needs to be handled
989   // differently.
990   XPACLRI   = 0xD50320FF
991 };
992 
993 // Any load or store.
994 enum LoadStoreAnyOp {
995   LoadStoreAnyFMask = 0x0a000000,
996   LoadStoreAnyFixed = 0x08000000
997 };
998 
999 // Any load pair or store pair.
1000 enum LoadStorePairAnyOp {
1001   LoadStorePairAnyFMask = 0x3a000000,
1002   LoadStorePairAnyFixed = 0x28000000
1003 };
1004 
1005 #define LOAD_STORE_PAIR_OP_LIST(V)  \
1006   V(STP, w,   0x00000000),          \
1007   V(LDP, w,   0x00400000),          \
1008   V(LDPSW, x, 0x40400000),          \
1009   V(STP, x,   0x80000000),          \
1010   V(LDP, x,   0x80400000),          \
1011   V(STP, s,   0x04000000),          \
1012   V(LDP, s,   0x04400000),          \
1013   V(STP, d,   0x44000000),          \
1014   V(LDP, d,   0x44400000),          \
1015   V(STP, q,   0x84000000),          \
1016   V(LDP, q,   0x84400000)
1017 
1018 // Load/store pair (post, pre and offset.)
1019 enum LoadStorePairOp {
1020   LoadStorePairMask = 0xC4400000,
1021   LoadStorePairLBit = 1 << 22,
1022   #define LOAD_STORE_PAIR(A, B, C) \
1023   A##_##B = C
1024   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
1025   #undef LOAD_STORE_PAIR
1026 };
1027 
1028 enum LoadStorePairPostIndexOp {
1029   LoadStorePairPostIndexFixed = 0x28800000,
1030   LoadStorePairPostIndexFMask = 0x3B800000,
1031   LoadStorePairPostIndexMask  = 0xFFC00000,
1032   #define LOAD_STORE_PAIR_POST_INDEX(A, B, C)  \
1033   A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
1034   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
1035   #undef LOAD_STORE_PAIR_POST_INDEX
1036 };
1037 
1038 enum LoadStorePairPreIndexOp {
1039   LoadStorePairPreIndexFixed = 0x29800000,
1040   LoadStorePairPreIndexFMask = 0x3B800000,
1041   LoadStorePairPreIndexMask  = 0xFFC00000,
1042   #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C)  \
1043   A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
1044   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
1045   #undef LOAD_STORE_PAIR_PRE_INDEX
1046 };
1047 
1048 enum LoadStorePairOffsetOp {
1049   LoadStorePairOffsetFixed = 0x29000000,
1050   LoadStorePairOffsetFMask = 0x3B800000,
1051   LoadStorePairOffsetMask  = 0xFFC00000,
1052   #define LOAD_STORE_PAIR_OFFSET(A, B, C)  \
1053   A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
1054   LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
1055   #undef LOAD_STORE_PAIR_OFFSET
1056 };
1057 
1058 enum LoadStorePairNonTemporalOp {
1059   LoadStorePairNonTemporalFixed = 0x28000000,
1060   LoadStorePairNonTemporalFMask = 0x3B800000,
1061   LoadStorePairNonTemporalMask  = 0xFFC00000,
1062   LoadStorePairNonTemporalLBit = 1 << 22,
1063   STNP_w = LoadStorePairNonTemporalFixed | STP_w,
1064   LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
1065   STNP_x = LoadStorePairNonTemporalFixed | STP_x,
1066   LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
1067   STNP_s = LoadStorePairNonTemporalFixed | STP_s,
1068   LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
1069   STNP_d = LoadStorePairNonTemporalFixed | STP_d,
1070   LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
1071   STNP_q = LoadStorePairNonTemporalFixed | STP_q,
1072   LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
1073 };
1074 
1075 // Load with pointer authentication.
1076 enum LoadStorePACOp {
1077   LoadStorePACFixed  = 0xF8200400,
1078   LoadStorePACFMask  = 0xFF200400,
1079   LoadStorePACMask   = 0xFFA00C00,
1080   LoadStorePACPreBit = 0x00000800,
1081   LDRAA     = LoadStorePACFixed | 0x00000000,
1082   LDRAA_pre = LoadStorePACPreBit | LDRAA,
1083   LDRAB     = LoadStorePACFixed | 0x00800000,
1084   LDRAB_pre = LoadStorePACPreBit | LDRAB
1085 };
1086 
1087 // Load literal.
1088 enum LoadLiteralOp {
1089   LoadLiteralFixed = 0x18000000,
1090   LoadLiteralFMask = 0x3B000000,
1091   LoadLiteralMask  = 0xFF000000,
1092   LDR_w_lit        = LoadLiteralFixed | 0x00000000,
1093   LDR_x_lit        = LoadLiteralFixed | 0x40000000,
1094   LDRSW_x_lit      = LoadLiteralFixed | 0x80000000,
1095   PRFM_lit         = LoadLiteralFixed | 0xC0000000,
1096   LDR_s_lit        = LoadLiteralFixed | 0x04000000,
1097   LDR_d_lit        = LoadLiteralFixed | 0x44000000,
1098   LDR_q_lit        = LoadLiteralFixed | 0x84000000
1099 };
1100 
1101 #define LOAD_STORE_OP_LIST(V)     \
1102   V(ST, RB, w,  0x00000000),  \
1103   V(ST, RH, w,  0x40000000),  \
1104   V(ST, R, w,   0x80000000),  \
1105   V(ST, R, x,   0xC0000000),  \
1106   V(LD, RB, w,  0x00400000),  \
1107   V(LD, RH, w,  0x40400000),  \
1108   V(LD, R, w,   0x80400000),  \
1109   V(LD, R, x,   0xC0400000),  \
1110   V(LD, RSB, x, 0x00800000),  \
1111   V(LD, RSH, x, 0x40800000),  \
1112   V(LD, RSW, x, 0x80800000),  \
1113   V(LD, RSB, w, 0x00C00000),  \
1114   V(LD, RSH, w, 0x40C00000),  \
1115   V(ST, R, b,   0x04000000),  \
1116   V(ST, R, h,   0x44000000),  \
1117   V(ST, R, s,   0x84000000),  \
1118   V(ST, R, d,   0xC4000000),  \
1119   V(ST, R, q,   0x04800000),  \
1120   V(LD, R, b,   0x04400000),  \
1121   V(LD, R, h,   0x44400000),  \
1122   V(LD, R, s,   0x84400000),  \
1123   V(LD, R, d,   0xC4400000),  \
1124   V(LD, R, q,   0x04C00000)
1125 
1126 // Load/store (post, pre, offset and unsigned.)
1127 enum LoadStoreOp {
1128   LoadStoreMask = 0xC4C00000,
1129   LoadStoreVMask = 0x04000000,
1130   #define LOAD_STORE(A, B, C, D)  \
1131   A##B##_##C = D
1132   LOAD_STORE_OP_LIST(LOAD_STORE),
1133   #undef LOAD_STORE
1134   PRFM = 0xC0800000
1135 };
1136 
1137 // Load/store unscaled offset.
1138 enum LoadStoreUnscaledOffsetOp {
1139   LoadStoreUnscaledOffsetFixed = 0x38000000,
1140   LoadStoreUnscaledOffsetFMask = 0x3B200C00,
1141   LoadStoreUnscaledOffsetMask  = 0xFFE00C00,
1142   PRFUM                        = LoadStoreUnscaledOffsetFixed | PRFM,
1143   #define LOAD_STORE_UNSCALED(A, B, C, D)  \
1144   A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
1145   LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
1146   #undef LOAD_STORE_UNSCALED
1147 };
1148 
1149 // Load/store post index.
1150 enum LoadStorePostIndex {
1151   LoadStorePostIndexFixed = 0x38000400,
1152   LoadStorePostIndexFMask = 0x3B200C00,
1153   LoadStorePostIndexMask  = 0xFFE00C00,
1154   #define LOAD_STORE_POST_INDEX(A, B, C, D)  \
1155   A##B##_##C##_post = LoadStorePostIndexFixed | D
1156   LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
1157   #undef LOAD_STORE_POST_INDEX
1158 };
1159 
1160 // Load/store pre index.
1161 enum LoadStorePreIndex {
1162   LoadStorePreIndexFixed = 0x38000C00,
1163   LoadStorePreIndexFMask = 0x3B200C00,
1164   LoadStorePreIndexMask  = 0xFFE00C00,
1165   #define LOAD_STORE_PRE_INDEX(A, B, C, D)  \
1166   A##B##_##C##_pre = LoadStorePreIndexFixed | D
1167   LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
1168   #undef LOAD_STORE_PRE_INDEX
1169 };
1170 
1171 // Load/store unsigned offset.
1172 enum LoadStoreUnsignedOffset {
1173   LoadStoreUnsignedOffsetFixed = 0x39000000,
1174   LoadStoreUnsignedOffsetFMask = 0x3B000000,
1175   LoadStoreUnsignedOffsetMask  = 0xFFC00000,
1176   PRFM_unsigned                = LoadStoreUnsignedOffsetFixed | PRFM,
1177   #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
1178   A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
1179   LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
1180   #undef LOAD_STORE_UNSIGNED_OFFSET
1181 };
1182 
1183 // Load/store register offset.
1184 enum LoadStoreRegisterOffset {
1185   LoadStoreRegisterOffsetFixed = 0x38200800,
1186   LoadStoreRegisterOffsetFMask = 0x3B200C00,
1187   LoadStoreRegisterOffsetMask  = 0xFFE00C00,
1188   PRFM_reg                     = LoadStoreRegisterOffsetFixed | PRFM,
1189   #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
1190   A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
1191   LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
1192   #undef LOAD_STORE_REGISTER_OFFSET
1193 };
1194 
1195 enum LoadStoreExclusive {
1196   LoadStoreExclusiveFixed = 0x08000000,
1197   LoadStoreExclusiveFMask = 0x3F000000,
1198   LoadStoreExclusiveMask  = 0xFFE08000,
1199   STXRB_w  = LoadStoreExclusiveFixed | 0x00000000,
1200   STXRH_w  = LoadStoreExclusiveFixed | 0x40000000,
1201   STXR_w   = LoadStoreExclusiveFixed | 0x80000000,
1202   STXR_x   = LoadStoreExclusiveFixed | 0xC0000000,
1203   LDXRB_w  = LoadStoreExclusiveFixed | 0x00400000,
1204   LDXRH_w  = LoadStoreExclusiveFixed | 0x40400000,
1205   LDXR_w   = LoadStoreExclusiveFixed | 0x80400000,
1206   LDXR_x   = LoadStoreExclusiveFixed | 0xC0400000,
1207   STXP_w   = LoadStoreExclusiveFixed | 0x80200000,
1208   STXP_x   = LoadStoreExclusiveFixed | 0xC0200000,
1209   LDXP_w   = LoadStoreExclusiveFixed | 0x80600000,
1210   LDXP_x   = LoadStoreExclusiveFixed | 0xC0600000,
1211   STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
1212   STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
1213   STLXR_w  = LoadStoreExclusiveFixed | 0x80008000,
1214   STLXR_x  = LoadStoreExclusiveFixed | 0xC0008000,
1215   LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
1216   LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
1217   LDAXR_w  = LoadStoreExclusiveFixed | 0x80408000,
1218   LDAXR_x  = LoadStoreExclusiveFixed | 0xC0408000,
1219   STLXP_w  = LoadStoreExclusiveFixed | 0x80208000,
1220   STLXP_x  = LoadStoreExclusiveFixed | 0xC0208000,
1221   LDAXP_w  = LoadStoreExclusiveFixed | 0x80608000,
1222   LDAXP_x  = LoadStoreExclusiveFixed | 0xC0608000,
1223   STLRB_w  = LoadStoreExclusiveFixed | 0x00808000,
1224   STLRH_w  = LoadStoreExclusiveFixed | 0x40808000,
1225   STLR_w   = LoadStoreExclusiveFixed | 0x80808000,
1226   STLR_x   = LoadStoreExclusiveFixed | 0xC0808000,
1227   LDARB_w  = LoadStoreExclusiveFixed | 0x00C08000,
1228   LDARH_w  = LoadStoreExclusiveFixed | 0x40C08000,
1229   LDAR_w   = LoadStoreExclusiveFixed | 0x80C08000,
1230   LDAR_x   = LoadStoreExclusiveFixed | 0xC0C08000,
1231 
1232   // v8.1 Load/store LORegion ops
1233   STLLRB   = LoadStoreExclusiveFixed | 0x00800000,
1234   LDLARB   = LoadStoreExclusiveFixed | 0x00C00000,
1235   STLLRH   = LoadStoreExclusiveFixed | 0x40800000,
1236   LDLARH   = LoadStoreExclusiveFixed | 0x40C00000,
1237   STLLR_w  = LoadStoreExclusiveFixed | 0x80800000,
1238   LDLAR_w  = LoadStoreExclusiveFixed | 0x80C00000,
1239   STLLR_x  = LoadStoreExclusiveFixed | 0xC0800000,
1240   LDLAR_x  = LoadStoreExclusiveFixed | 0xC0C00000,
1241 
1242   // v8.1 Load/store exclusive ops
1243   LSEBit_l  = 0x00400000,
1244   LSEBit_o0 = 0x00008000,
1245   LSEBit_sz = 0x40000000,
1246   CASFixed  = LoadStoreExclusiveFixed | 0x80A00000,
1247   CASBFixed = LoadStoreExclusiveFixed | 0x00A00000,
1248   CASHFixed = LoadStoreExclusiveFixed | 0x40A00000,
1249   CASPFixed = LoadStoreExclusiveFixed | 0x00200000,
1250   CAS_w    = CASFixed,
1251   CAS_x    = CASFixed | LSEBit_sz,
1252   CASA_w   = CASFixed | LSEBit_l,
1253   CASA_x   = CASFixed | LSEBit_l | LSEBit_sz,
1254   CASL_w   = CASFixed | LSEBit_o0,
1255   CASL_x   = CASFixed | LSEBit_o0 | LSEBit_sz,
1256   CASAL_w  = CASFixed | LSEBit_l | LSEBit_o0,
1257   CASAL_x  = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz,
1258   CASB     = CASBFixed,
1259   CASAB    = CASBFixed | LSEBit_l,
1260   CASLB    = CASBFixed | LSEBit_o0,
1261   CASALB   = CASBFixed | LSEBit_l | LSEBit_o0,
1262   CASH     = CASHFixed,
1263   CASAH    = CASHFixed | LSEBit_l,
1264   CASLH    = CASHFixed | LSEBit_o0,
1265   CASALH   = CASHFixed | LSEBit_l | LSEBit_o0,
1266   CASP_w   = CASPFixed,
1267   CASP_x   = CASPFixed | LSEBit_sz,
1268   CASPA_w  = CASPFixed | LSEBit_l,
1269   CASPA_x  = CASPFixed | LSEBit_l | LSEBit_sz,
1270   CASPL_w  = CASPFixed | LSEBit_o0,
1271   CASPL_x  = CASPFixed | LSEBit_o0 | LSEBit_sz,
1272   CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0,
1273   CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz
1274 };
1275 
1276 // Load/store RCpc unscaled offset.
1277 enum LoadStoreRCpcUnscaledOffsetOp {
1278   LoadStoreRCpcUnscaledOffsetFixed = 0x19000000,
1279   LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00,
1280   LoadStoreRCpcUnscaledOffsetMask  = 0xFFE00C00,
1281   STLURB     = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000,
1282   LDAPURB    = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000,
1283   LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000,
1284   LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000,
1285   STLURH     = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000,
1286   LDAPURH    = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000,
1287   LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000,
1288   LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000,
1289   STLUR_w    = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000,
1290   LDAPUR_w   = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000,
1291   LDAPURSW   = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000,
1292   STLUR_x    = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000,
1293   LDAPUR_x   = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000
1294 };
1295 
1296 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \
1297   V(LDADD, 0x00000000),                  \
1298   V(LDCLR, 0x00001000),                  \
1299   V(LDEOR, 0x00002000),                  \
1300   V(LDSET, 0x00003000),                  \
1301   V(LDSMAX, 0x00004000),                 \
1302   V(LDSMIN, 0x00005000),                 \
1303   V(LDUMAX, 0x00006000),                 \
1304   V(LDUMIN, 0x00007000)
1305 
1306 // Atomic memory.
1307 enum AtomicMemoryOp {
1308   AtomicMemoryFixed = 0x38200000,
1309   AtomicMemoryFMask = 0x3B200C00,
1310   AtomicMemoryMask = 0xFFE0FC00,
1311   SWPB = AtomicMemoryFixed | 0x00008000,
1312   SWPAB = AtomicMemoryFixed | 0x00808000,
1313   SWPLB = AtomicMemoryFixed | 0x00408000,
1314   SWPALB = AtomicMemoryFixed | 0x00C08000,
1315   SWPH = AtomicMemoryFixed | 0x40008000,
1316   SWPAH = AtomicMemoryFixed | 0x40808000,
1317   SWPLH = AtomicMemoryFixed | 0x40408000,
1318   SWPALH = AtomicMemoryFixed | 0x40C08000,
1319   SWP_w = AtomicMemoryFixed | 0x80008000,
1320   SWPA_w = AtomicMemoryFixed | 0x80808000,
1321   SWPL_w = AtomicMemoryFixed | 0x80408000,
1322   SWPAL_w = AtomicMemoryFixed | 0x80C08000,
1323   SWP_x = AtomicMemoryFixed | 0xC0008000,
1324   SWPA_x = AtomicMemoryFixed | 0xC0808000,
1325   SWPL_x = AtomicMemoryFixed | 0xC0408000,
1326   SWPAL_x = AtomicMemoryFixed | 0xC0C08000,
1327   LDAPRB = AtomicMemoryFixed | 0x0080C000,
1328   LDAPRH = AtomicMemoryFixed | 0x4080C000,
1329   LDAPR_w = AtomicMemoryFixed | 0x8080C000,
1330   LDAPR_x = AtomicMemoryFixed | 0xC080C000,
1331 
1332   AtomicMemorySimpleFMask = 0x3B208C00,
1333   AtomicMemorySimpleOpMask = 0x00007000,
1334 #define ATOMIC_MEMORY_SIMPLE(N, OP)              \
1335   N##Op = OP,                                    \
1336   N##B = AtomicMemoryFixed | OP,                 \
1337   N##AB = AtomicMemoryFixed | OP | 0x00800000,   \
1338   N##LB = AtomicMemoryFixed | OP | 0x00400000,   \
1339   N##ALB = AtomicMemoryFixed | OP | 0x00C00000,  \
1340   N##H = AtomicMemoryFixed | OP | 0x40000000,    \
1341   N##AH = AtomicMemoryFixed | OP | 0x40800000,   \
1342   N##LH = AtomicMemoryFixed | OP | 0x40400000,   \
1343   N##ALH = AtomicMemoryFixed | OP | 0x40C00000,  \
1344   N##_w = AtomicMemoryFixed | OP | 0x80000000,   \
1345   N##A_w = AtomicMemoryFixed | OP | 0x80800000,  \
1346   N##L_w = AtomicMemoryFixed | OP | 0x80400000,  \
1347   N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \
1348   N##_x = AtomicMemoryFixed | OP | 0xC0000000,   \
1349   N##A_x = AtomicMemoryFixed | OP | 0xC0800000,  \
1350   N##L_x = AtomicMemoryFixed | OP | 0xC0400000,  \
1351   N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000
1352 
1353   ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE)
1354 #undef ATOMIC_MEMORY_SIMPLE
1355 };
1356 
1357 // Conditional compare.
1358 enum ConditionalCompareOp {
1359   ConditionalCompareMask = 0x60000000,
1360   CCMN                   = 0x20000000,
1361   CCMP                   = 0x60000000
1362 };
1363 
1364 // Conditional compare register.
1365 enum ConditionalCompareRegisterOp {
1366   ConditionalCompareRegisterFixed = 0x1A400000,
1367   ConditionalCompareRegisterFMask = 0x1FE00800,
1368   ConditionalCompareRegisterMask  = 0xFFE00C10,
1369   CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1370   CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1371   CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1372   CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1373 };
1374 
1375 // Conditional compare immediate.
1376 enum ConditionalCompareImmediateOp {
1377   ConditionalCompareImmediateFixed = 0x1A400800,
1378   ConditionalCompareImmediateFMask = 0x1FE00800,
1379   ConditionalCompareImmediateMask  = 0xFFE00C10,
1380   CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1381   CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1382   CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1383   CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1384 };
1385 
1386 // Conditional select.
1387 enum ConditionalSelectOp {
1388   ConditionalSelectFixed = 0x1A800000,
1389   ConditionalSelectFMask = 0x1FE00000,
1390   ConditionalSelectMask  = 0xFFE00C00,
1391   CSEL_w                 = ConditionalSelectFixed | 0x00000000,
1392   CSEL_x                 = ConditionalSelectFixed | 0x80000000,
1393   CSEL                   = CSEL_w,
1394   CSINC_w                = ConditionalSelectFixed | 0x00000400,
1395   CSINC_x                = ConditionalSelectFixed | 0x80000400,
1396   CSINC                  = CSINC_w,
1397   CSINV_w                = ConditionalSelectFixed | 0x40000000,
1398   CSINV_x                = ConditionalSelectFixed | 0xC0000000,
1399   CSINV                  = CSINV_w,
1400   CSNEG_w                = ConditionalSelectFixed | 0x40000400,
1401   CSNEG_x                = ConditionalSelectFixed | 0xC0000400,
1402   CSNEG                  = CSNEG_w
1403 };
1404 
1405 // Data processing 1 source.
1406 enum DataProcessing1SourceOp {
1407   DataProcessing1SourceFixed = 0x5AC00000,
1408   DataProcessing1SourceFMask = 0x5FE00000,
1409   DataProcessing1SourceMask  = 0xFFFFFC00,
1410   RBIT    = DataProcessing1SourceFixed | 0x00000000,
1411   RBIT_w  = RBIT,
1412   RBIT_x  = RBIT | SixtyFourBits,
1413   REV16   = DataProcessing1SourceFixed | 0x00000400,
1414   REV16_w = REV16,
1415   REV16_x = REV16 | SixtyFourBits,
1416   REV     = DataProcessing1SourceFixed | 0x00000800,
1417   REV_w   = REV,
1418   REV32_x = REV | SixtyFourBits,
1419   REV_x   = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1420   CLZ     = DataProcessing1SourceFixed | 0x00001000,
1421   CLZ_w   = CLZ,
1422   CLZ_x   = CLZ | SixtyFourBits,
1423   CLS     = DataProcessing1SourceFixed | 0x00001400,
1424   CLS_w   = CLS,
1425   CLS_x   = CLS | SixtyFourBits,
1426 
1427   // Pointer authentication instructions in Armv8.3.
1428   PACIA  = DataProcessing1SourceFixed | 0x80010000,
1429   PACIB  = DataProcessing1SourceFixed | 0x80010400,
1430   PACDA  = DataProcessing1SourceFixed | 0x80010800,
1431   PACDB  = DataProcessing1SourceFixed | 0x80010C00,
1432   AUTIA  = DataProcessing1SourceFixed | 0x80011000,
1433   AUTIB  = DataProcessing1SourceFixed | 0x80011400,
1434   AUTDA  = DataProcessing1SourceFixed | 0x80011800,
1435   AUTDB  = DataProcessing1SourceFixed | 0x80011C00,
1436   PACIZA = DataProcessing1SourceFixed | 0x80012000,
1437   PACIZB = DataProcessing1SourceFixed | 0x80012400,
1438   PACDZA = DataProcessing1SourceFixed | 0x80012800,
1439   PACDZB = DataProcessing1SourceFixed | 0x80012C00,
1440   AUTIZA = DataProcessing1SourceFixed | 0x80013000,
1441   AUTIZB = DataProcessing1SourceFixed | 0x80013400,
1442   AUTDZA = DataProcessing1SourceFixed | 0x80013800,
1443   AUTDZB = DataProcessing1SourceFixed | 0x80013C00,
1444   XPACI  = DataProcessing1SourceFixed | 0x80014000,
1445   XPACD  = DataProcessing1SourceFixed | 0x80014400
1446 };
1447 
1448 // Data processing 2 source.
1449 enum DataProcessing2SourceOp {
1450   DataProcessing2SourceFixed = 0x1AC00000,
1451   DataProcessing2SourceFMask = 0x5FE00000,
1452   DataProcessing2SourceMask  = 0xFFE0FC00,
1453   UDIV_w  = DataProcessing2SourceFixed | 0x00000800,
1454   UDIV_x  = DataProcessing2SourceFixed | 0x80000800,
1455   UDIV    = UDIV_w,
1456   SDIV_w  = DataProcessing2SourceFixed | 0x00000C00,
1457   SDIV_x  = DataProcessing2SourceFixed | 0x80000C00,
1458   SDIV    = SDIV_w,
1459   LSLV_w  = DataProcessing2SourceFixed | 0x00002000,
1460   LSLV_x  = DataProcessing2SourceFixed | 0x80002000,
1461   LSLV    = LSLV_w,
1462   LSRV_w  = DataProcessing2SourceFixed | 0x00002400,
1463   LSRV_x  = DataProcessing2SourceFixed | 0x80002400,
1464   LSRV    = LSRV_w,
1465   ASRV_w  = DataProcessing2SourceFixed | 0x00002800,
1466   ASRV_x  = DataProcessing2SourceFixed | 0x80002800,
1467   ASRV    = ASRV_w,
1468   RORV_w  = DataProcessing2SourceFixed | 0x00002C00,
1469   RORV_x  = DataProcessing2SourceFixed | 0x80002C00,
1470   RORV    = RORV_w,
1471   PACGA   = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000,
1472   CRC32B  = DataProcessing2SourceFixed | 0x00004000,
1473   CRC32H  = DataProcessing2SourceFixed | 0x00004400,
1474   CRC32W  = DataProcessing2SourceFixed | 0x00004800,
1475   CRC32X  = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1476   CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1477   CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1478   CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1479   CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1480 };
1481 
1482 // Data processing 3 source.
1483 enum DataProcessing3SourceOp {
1484   DataProcessing3SourceFixed = 0x1B000000,
1485   DataProcessing3SourceFMask = 0x1F000000,
1486   DataProcessing3SourceMask  = 0xFFE08000,
1487   MADD_w                     = DataProcessing3SourceFixed | 0x00000000,
1488   MADD_x                     = DataProcessing3SourceFixed | 0x80000000,
1489   MADD                       = MADD_w,
1490   MSUB_w                     = DataProcessing3SourceFixed | 0x00008000,
1491   MSUB_x                     = DataProcessing3SourceFixed | 0x80008000,
1492   MSUB                       = MSUB_w,
1493   SMADDL_x                   = DataProcessing3SourceFixed | 0x80200000,
1494   SMSUBL_x                   = DataProcessing3SourceFixed | 0x80208000,
1495   SMULH_x                    = DataProcessing3SourceFixed | 0x80400000,
1496   UMADDL_x                   = DataProcessing3SourceFixed | 0x80A00000,
1497   UMSUBL_x                   = DataProcessing3SourceFixed | 0x80A08000,
1498   UMULH_x                    = DataProcessing3SourceFixed | 0x80C00000
1499 };
1500 
1501 // Floating point compare.
1502 enum FPCompareOp {
1503   FPCompareFixed = 0x1E202000,
1504   FPCompareFMask = 0x5F203C00,
1505   FPCompareMask  = 0xFFE0FC1F,
1506   FCMP_h         = FPCompareFixed | FP16 | 0x00000000,
1507   FCMP_s         = FPCompareFixed | 0x00000000,
1508   FCMP_d         = FPCompareFixed | FP64 | 0x00000000,
1509   FCMP           = FCMP_s,
1510   FCMP_h_zero    = FPCompareFixed | FP16 | 0x00000008,
1511   FCMP_s_zero    = FPCompareFixed | 0x00000008,
1512   FCMP_d_zero    = FPCompareFixed | FP64 | 0x00000008,
1513   FCMP_zero      = FCMP_s_zero,
1514   FCMPE_h        = FPCompareFixed | FP16 | 0x00000010,
1515   FCMPE_s        = FPCompareFixed | 0x00000010,
1516   FCMPE_d        = FPCompareFixed | FP64 | 0x00000010,
1517   FCMPE          = FCMPE_s,
1518   FCMPE_h_zero   = FPCompareFixed | FP16 | 0x00000018,
1519   FCMPE_s_zero   = FPCompareFixed | 0x00000018,
1520   FCMPE_d_zero   = FPCompareFixed | FP64 | 0x00000018,
1521   FCMPE_zero     = FCMPE_s_zero
1522 };
1523 
1524 // Floating point conditional compare.
1525 enum FPConditionalCompareOp {
1526   FPConditionalCompareFixed = 0x1E200400,
1527   FPConditionalCompareFMask = 0x5F200C00,
1528   FPConditionalCompareMask  = 0xFFE00C10,
1529   FCCMP_h                   = FPConditionalCompareFixed | FP16 | 0x00000000,
1530   FCCMP_s                   = FPConditionalCompareFixed | 0x00000000,
1531   FCCMP_d                   = FPConditionalCompareFixed | FP64 | 0x00000000,
1532   FCCMP                     = FCCMP_s,
1533   FCCMPE_h                  = FPConditionalCompareFixed | FP16 | 0x00000010,
1534   FCCMPE_s                  = FPConditionalCompareFixed | 0x00000010,
1535   FCCMPE_d                  = FPConditionalCompareFixed | FP64 | 0x00000010,
1536   FCCMPE                    = FCCMPE_s
1537 };
1538 
1539 // Floating point conditional select.
1540 enum FPConditionalSelectOp {
1541   FPConditionalSelectFixed = 0x1E200C00,
1542   FPConditionalSelectFMask = 0x5F200C00,
1543   FPConditionalSelectMask  = 0xFFE00C00,
1544   FCSEL_h                  = FPConditionalSelectFixed | FP16 | 0x00000000,
1545   FCSEL_s                  = FPConditionalSelectFixed | 0x00000000,
1546   FCSEL_d                  = FPConditionalSelectFixed | FP64 | 0x00000000,
1547   FCSEL                    = FCSEL_s
1548 };
1549 
1550 // Floating point immediate.
1551 enum FPImmediateOp {
1552   FPImmediateFixed = 0x1E201000,
1553   FPImmediateFMask = 0x5F201C00,
1554   FPImmediateMask  = 0xFFE01C00,
1555   FMOV_h_imm       = FPImmediateFixed | FP16 | 0x00000000,
1556   FMOV_s_imm       = FPImmediateFixed | 0x00000000,
1557   FMOV_d_imm       = FPImmediateFixed | FP64 | 0x00000000
1558 };
1559 
1560 // Floating point data processing 1 source.
1561 enum FPDataProcessing1SourceOp {
1562   FPDataProcessing1SourceFixed = 0x1E204000,
1563   FPDataProcessing1SourceFMask = 0x5F207C00,
1564   FPDataProcessing1SourceMask  = 0xFFFFFC00,
1565   FMOV_h   = FPDataProcessing1SourceFixed | FP16 | 0x00000000,
1566   FMOV_s   = FPDataProcessing1SourceFixed | 0x00000000,
1567   FMOV_d   = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1568   FMOV     = FMOV_s,
1569   FABS_h   = FPDataProcessing1SourceFixed | FP16 | 0x00008000,
1570   FABS_s   = FPDataProcessing1SourceFixed | 0x00008000,
1571   FABS_d   = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1572   FABS     = FABS_s,
1573   FNEG_h   = FPDataProcessing1SourceFixed | FP16 | 0x00010000,
1574   FNEG_s   = FPDataProcessing1SourceFixed | 0x00010000,
1575   FNEG_d   = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1576   FNEG     = FNEG_s,
1577   FSQRT_h  = FPDataProcessing1SourceFixed | FP16 | 0x00018000,
1578   FSQRT_s  = FPDataProcessing1SourceFixed | 0x00018000,
1579   FSQRT_d  = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1580   FSQRT    = FSQRT_s,
1581   FCVT_ds  = FPDataProcessing1SourceFixed | 0x00028000,
1582   FCVT_sd  = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1583   FCVT_hs  = FPDataProcessing1SourceFixed | 0x00038000,
1584   FCVT_hd  = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1585   FCVT_sh  = FPDataProcessing1SourceFixed | 0x00C20000,
1586   FCVT_dh  = FPDataProcessing1SourceFixed | 0x00C28000,
1587   FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000,
1588   FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000,
1589   FRINT32X = FRINT32X_s,
1590   FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000,
1591   FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000,
1592   FRINT32Z = FRINT32Z_s,
1593   FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000,
1594   FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000,
1595   FRINT64X = FRINT64X_s,
1596   FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000,
1597   FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000,
1598   FRINT64Z = FRINT64Z_s,
1599   FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000,
1600   FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1601   FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1602   FRINTN   = FRINTN_s,
1603   FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000,
1604   FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1605   FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1606   FRINTP   = FRINTP_s,
1607   FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000,
1608   FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1609   FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1610   FRINTM   = FRINTM_s,
1611   FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000,
1612   FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1613   FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1614   FRINTZ   = FRINTZ_s,
1615   FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000,
1616   FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1617   FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1618   FRINTA   = FRINTA_s,
1619   FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000,
1620   FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1621   FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1622   FRINTX   = FRINTX_s,
1623   FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000,
1624   FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1625   FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1626   FRINTI   = FRINTI_s
1627 };
1628 
1629 // Floating point data processing 2 source.
1630 enum FPDataProcessing2SourceOp {
1631   FPDataProcessing2SourceFixed = 0x1E200800,
1632   FPDataProcessing2SourceFMask = 0x5F200C00,
1633   FPDataProcessing2SourceMask  = 0xFFE0FC00,
1634   FMUL     = FPDataProcessing2SourceFixed | 0x00000000,
1635   FMUL_h   = FMUL | FP16,
1636   FMUL_s   = FMUL,
1637   FMUL_d   = FMUL | FP64,
1638   FDIV     = FPDataProcessing2SourceFixed | 0x00001000,
1639   FDIV_h   = FDIV | FP16,
1640   FDIV_s   = FDIV,
1641   FDIV_d   = FDIV | FP64,
1642   FADD     = FPDataProcessing2SourceFixed | 0x00002000,
1643   FADD_h   = FADD | FP16,
1644   FADD_s   = FADD,
1645   FADD_d   = FADD | FP64,
1646   FSUB     = FPDataProcessing2SourceFixed | 0x00003000,
1647   FSUB_h   = FSUB | FP16,
1648   FSUB_s   = FSUB,
1649   FSUB_d   = FSUB | FP64,
1650   FMAX     = FPDataProcessing2SourceFixed | 0x00004000,
1651   FMAX_h   = FMAX | FP16,
1652   FMAX_s   = FMAX,
1653   FMAX_d   = FMAX | FP64,
1654   FMIN     = FPDataProcessing2SourceFixed | 0x00005000,
1655   FMIN_h   = FMIN | FP16,
1656   FMIN_s   = FMIN,
1657   FMIN_d   = FMIN | FP64,
1658   FMAXNM   = FPDataProcessing2SourceFixed | 0x00006000,
1659   FMAXNM_h = FMAXNM | FP16,
1660   FMAXNM_s = FMAXNM,
1661   FMAXNM_d = FMAXNM | FP64,
1662   FMINNM   = FPDataProcessing2SourceFixed | 0x00007000,
1663   FMINNM_h = FMINNM | FP16,
1664   FMINNM_s = FMINNM,
1665   FMINNM_d = FMINNM | FP64,
1666   FNMUL    = FPDataProcessing2SourceFixed | 0x00008000,
1667   FNMUL_h  = FNMUL | FP16,
1668   FNMUL_s  = FNMUL,
1669   FNMUL_d  = FNMUL | FP64
1670 };
1671 
1672 // Floating point data processing 3 source.
1673 enum FPDataProcessing3SourceOp {
1674   FPDataProcessing3SourceFixed = 0x1F000000,
1675   FPDataProcessing3SourceFMask = 0x5F000000,
1676   FPDataProcessing3SourceMask  = 0xFFE08000,
1677   FMADD_h                      = FPDataProcessing3SourceFixed | 0x00C00000,
1678   FMSUB_h                      = FPDataProcessing3SourceFixed | 0x00C08000,
1679   FNMADD_h                     = FPDataProcessing3SourceFixed | 0x00E00000,
1680   FNMSUB_h                     = FPDataProcessing3SourceFixed | 0x00E08000,
1681   FMADD_s                      = FPDataProcessing3SourceFixed | 0x00000000,
1682   FMSUB_s                      = FPDataProcessing3SourceFixed | 0x00008000,
1683   FNMADD_s                     = FPDataProcessing3SourceFixed | 0x00200000,
1684   FNMSUB_s                     = FPDataProcessing3SourceFixed | 0x00208000,
1685   FMADD_d                      = FPDataProcessing3SourceFixed | 0x00400000,
1686   FMSUB_d                      = FPDataProcessing3SourceFixed | 0x00408000,
1687   FNMADD_d                     = FPDataProcessing3SourceFixed | 0x00600000,
1688   FNMSUB_d                     = FPDataProcessing3SourceFixed | 0x00608000
1689 };
1690 
1691 // Conversion between floating point and integer.
1692 enum FPIntegerConvertOp {
1693   FPIntegerConvertFixed = 0x1E200000,
1694   FPIntegerConvertFMask = 0x5F20FC00,
1695   FPIntegerConvertMask  = 0xFFFFFC00,
1696   FCVTNS    = FPIntegerConvertFixed | 0x00000000,
1697   FCVTNS_wh = FCVTNS | FP16,
1698   FCVTNS_xh = FCVTNS | SixtyFourBits | FP16,
1699   FCVTNS_ws = FCVTNS,
1700   FCVTNS_xs = FCVTNS | SixtyFourBits,
1701   FCVTNS_wd = FCVTNS | FP64,
1702   FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1703   FCVTNU    = FPIntegerConvertFixed | 0x00010000,
1704   FCVTNU_wh = FCVTNU | FP16,
1705   FCVTNU_xh = FCVTNU | SixtyFourBits | FP16,
1706   FCVTNU_ws = FCVTNU,
1707   FCVTNU_xs = FCVTNU | SixtyFourBits,
1708   FCVTNU_wd = FCVTNU | FP64,
1709   FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1710   FCVTPS    = FPIntegerConvertFixed | 0x00080000,
1711   FCVTPS_wh = FCVTPS | FP16,
1712   FCVTPS_xh = FCVTPS | SixtyFourBits | FP16,
1713   FCVTPS_ws = FCVTPS,
1714   FCVTPS_xs = FCVTPS | SixtyFourBits,
1715   FCVTPS_wd = FCVTPS | FP64,
1716   FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1717   FCVTPU    = FPIntegerConvertFixed | 0x00090000,
1718   FCVTPU_wh = FCVTPU | FP16,
1719   FCVTPU_xh = FCVTPU | SixtyFourBits | FP16,
1720   FCVTPU_ws = FCVTPU,
1721   FCVTPU_xs = FCVTPU | SixtyFourBits,
1722   FCVTPU_wd = FCVTPU | FP64,
1723   FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1724   FCVTMS    = FPIntegerConvertFixed | 0x00100000,
1725   FCVTMS_wh = FCVTMS | FP16,
1726   FCVTMS_xh = FCVTMS | SixtyFourBits | FP16,
1727   FCVTMS_ws = FCVTMS,
1728   FCVTMS_xs = FCVTMS | SixtyFourBits,
1729   FCVTMS_wd = FCVTMS | FP64,
1730   FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1731   FCVTMU    = FPIntegerConvertFixed | 0x00110000,
1732   FCVTMU_wh = FCVTMU | FP16,
1733   FCVTMU_xh = FCVTMU | SixtyFourBits | FP16,
1734   FCVTMU_ws = FCVTMU,
1735   FCVTMU_xs = FCVTMU | SixtyFourBits,
1736   FCVTMU_wd = FCVTMU | FP64,
1737   FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1738   FCVTZS    = FPIntegerConvertFixed | 0x00180000,
1739   FCVTZS_wh = FCVTZS | FP16,
1740   FCVTZS_xh = FCVTZS | SixtyFourBits | FP16,
1741   FCVTZS_ws = FCVTZS,
1742   FCVTZS_xs = FCVTZS | SixtyFourBits,
1743   FCVTZS_wd = FCVTZS | FP64,
1744   FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1745   FCVTZU    = FPIntegerConvertFixed | 0x00190000,
1746   FCVTZU_wh = FCVTZU | FP16,
1747   FCVTZU_xh = FCVTZU | SixtyFourBits | FP16,
1748   FCVTZU_ws = FCVTZU,
1749   FCVTZU_xs = FCVTZU | SixtyFourBits,
1750   FCVTZU_wd = FCVTZU | FP64,
1751   FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1752   SCVTF     = FPIntegerConvertFixed | 0x00020000,
1753   SCVTF_hw  = SCVTF | FP16,
1754   SCVTF_hx  = SCVTF | SixtyFourBits | FP16,
1755   SCVTF_sw  = SCVTF,
1756   SCVTF_sx  = SCVTF | SixtyFourBits,
1757   SCVTF_dw  = SCVTF | FP64,
1758   SCVTF_dx  = SCVTF | SixtyFourBits | FP64,
1759   UCVTF     = FPIntegerConvertFixed | 0x00030000,
1760   UCVTF_hw  = UCVTF | FP16,
1761   UCVTF_hx  = UCVTF | SixtyFourBits | FP16,
1762   UCVTF_sw  = UCVTF,
1763   UCVTF_sx  = UCVTF | SixtyFourBits,
1764   UCVTF_dw  = UCVTF | FP64,
1765   UCVTF_dx  = UCVTF | SixtyFourBits | FP64,
1766   FCVTAS    = FPIntegerConvertFixed | 0x00040000,
1767   FCVTAS_wh = FCVTAS | FP16,
1768   FCVTAS_xh = FCVTAS | SixtyFourBits | FP16,
1769   FCVTAS_ws = FCVTAS,
1770   FCVTAS_xs = FCVTAS | SixtyFourBits,
1771   FCVTAS_wd = FCVTAS | FP64,
1772   FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1773   FCVTAU    = FPIntegerConvertFixed | 0x00050000,
1774   FCVTAU_wh = FCVTAU | FP16,
1775   FCVTAU_xh = FCVTAU | SixtyFourBits | FP16,
1776   FCVTAU_ws = FCVTAU,
1777   FCVTAU_xs = FCVTAU | SixtyFourBits,
1778   FCVTAU_wd = FCVTAU | FP64,
1779   FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1780   FMOV_wh   = FPIntegerConvertFixed | 0x00060000 | FP16,
1781   FMOV_hw   = FPIntegerConvertFixed | 0x00070000 | FP16,
1782   FMOV_xh   = FMOV_wh | SixtyFourBits,
1783   FMOV_hx   = FMOV_hw | SixtyFourBits,
1784   FMOV_ws   = FPIntegerConvertFixed | 0x00060000,
1785   FMOV_sw   = FPIntegerConvertFixed | 0x00070000,
1786   FMOV_xd   = FMOV_ws | SixtyFourBits | FP64,
1787   FMOV_dx   = FMOV_sw | SixtyFourBits | FP64,
1788   FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1789   FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000,
1790   FJCVTZS   = FPIntegerConvertFixed | FP64 | 0x001E0000
1791 };
1792 
1793 // Conversion between fixed point and floating point.
1794 enum FPFixedPointConvertOp {
1795   FPFixedPointConvertFixed = 0x1E000000,
1796   FPFixedPointConvertFMask = 0x5F200000,
1797   FPFixedPointConvertMask  = 0xFFFF0000,
1798   FCVTZS_fixed    = FPFixedPointConvertFixed | 0x00180000,
1799   FCVTZS_wh_fixed = FCVTZS_fixed | FP16,
1800   FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16,
1801   FCVTZS_ws_fixed = FCVTZS_fixed,
1802   FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1803   FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1804   FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1805   FCVTZU_fixed    = FPFixedPointConvertFixed | 0x00190000,
1806   FCVTZU_wh_fixed = FCVTZU_fixed | FP16,
1807   FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16,
1808   FCVTZU_ws_fixed = FCVTZU_fixed,
1809   FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1810   FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1811   FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1812   SCVTF_fixed     = FPFixedPointConvertFixed | 0x00020000,
1813   SCVTF_hw_fixed  = SCVTF_fixed | FP16,
1814   SCVTF_hx_fixed  = SCVTF_fixed | SixtyFourBits | FP16,
1815   SCVTF_sw_fixed  = SCVTF_fixed,
1816   SCVTF_sx_fixed  = SCVTF_fixed | SixtyFourBits,
1817   SCVTF_dw_fixed  = SCVTF_fixed | FP64,
1818   SCVTF_dx_fixed  = SCVTF_fixed | SixtyFourBits | FP64,
1819   UCVTF_fixed     = FPFixedPointConvertFixed | 0x00030000,
1820   UCVTF_hw_fixed  = UCVTF_fixed | FP16,
1821   UCVTF_hx_fixed  = UCVTF_fixed | SixtyFourBits | FP16,
1822   UCVTF_sw_fixed  = UCVTF_fixed,
1823   UCVTF_sx_fixed  = UCVTF_fixed | SixtyFourBits,
1824   UCVTF_dw_fixed  = UCVTF_fixed | FP64,
1825   UCVTF_dx_fixed  = UCVTF_fixed | SixtyFourBits | FP64
1826 };
1827 
1828 // Crypto - two register SHA.
1829 enum Crypto2RegSHAOp {
1830   Crypto2RegSHAFixed = 0x5E280800,
1831   Crypto2RegSHAFMask = 0xFF3E0C00
1832 };
1833 
1834 // Crypto - three register SHA.
1835 enum Crypto3RegSHAOp {
1836   Crypto3RegSHAFixed = 0x5E000000,
1837   Crypto3RegSHAFMask = 0xFF208C00
1838 };
1839 
1840 // Crypto - AES.
1841 enum CryptoAESOp {
1842   CryptoAESFixed = 0x4E280800,
1843   CryptoAESFMask = 0xFF3E0C00
1844 };
1845 
1846 // NEON instructions with two register operands.
1847 enum NEON2RegMiscOp {
1848   NEON2RegMiscFixed = 0x0E200800,
1849   NEON2RegMiscFMask = 0x9F3E0C00,
1850   NEON2RegMiscMask  = 0xBF3FFC00,
1851   NEON2RegMiscUBit  = 0x20000000,
1852   NEON_REV64     = NEON2RegMiscFixed | 0x00000000,
1853   NEON_REV32     = NEON2RegMiscFixed | 0x20000000,
1854   NEON_REV16     = NEON2RegMiscFixed | 0x00001000,
1855   NEON_SADDLP    = NEON2RegMiscFixed | 0x00002000,
1856   NEON_UADDLP    = NEON_SADDLP | NEON2RegMiscUBit,
1857   NEON_SUQADD    = NEON2RegMiscFixed | 0x00003000,
1858   NEON_USQADD    = NEON_SUQADD | NEON2RegMiscUBit,
1859   NEON_CLS       = NEON2RegMiscFixed | 0x00004000,
1860   NEON_CLZ       = NEON2RegMiscFixed | 0x20004000,
1861   NEON_CNT       = NEON2RegMiscFixed | 0x00005000,
1862   NEON_RBIT_NOT  = NEON2RegMiscFixed | 0x20005000,
1863   NEON_SADALP    = NEON2RegMiscFixed | 0x00006000,
1864   NEON_UADALP    = NEON_SADALP | NEON2RegMiscUBit,
1865   NEON_SQABS     = NEON2RegMiscFixed | 0x00007000,
1866   NEON_SQNEG     = NEON2RegMiscFixed | 0x20007000,
1867   NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1868   NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1869   NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1870   NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1871   NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1872   NEON_ABS       = NEON2RegMiscFixed | 0x0000B000,
1873   NEON_NEG       = NEON2RegMiscFixed | 0x2000B000,
1874   NEON_XTN       = NEON2RegMiscFixed | 0x00012000,
1875   NEON_SQXTUN    = NEON2RegMiscFixed | 0x20012000,
1876   NEON_SHLL      = NEON2RegMiscFixed | 0x20013000,
1877   NEON_SQXTN     = NEON2RegMiscFixed | 0x00014000,
1878   NEON_UQXTN     = NEON_SQXTN | NEON2RegMiscUBit,
1879 
1880   NEON2RegMiscOpcode = 0x0001F000,
1881   NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1882   NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1883   NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1884   NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1885 
1886   // These instructions use only one bit of the size field. The other bit is
1887   // used to distinguish between instructions.
1888   NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1889   NEON_FABS   = NEON2RegMiscFixed | 0x0080F000,
1890   NEON_FNEG   = NEON2RegMiscFixed | 0x2080F000,
1891   NEON_FCVTN  = NEON2RegMiscFixed | 0x00016000,
1892   NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1893   NEON_FCVTL  = NEON2RegMiscFixed | 0x00017000,
1894   NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000,
1895   NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000,
1896   NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000,
1897   NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000,
1898   NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1899   NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1900   NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1901   NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1902   NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1903   NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1904   NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1905   NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1906   NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1907   NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1908   NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1909   NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1910   NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1911   NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1912   NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1913   NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1914   NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1915   NEON_FSQRT  = NEON2RegMiscFixed | 0x2081F000,
1916   NEON_SCVTF  = NEON2RegMiscFixed | 0x0001D000,
1917   NEON_UCVTF  = NEON_SCVTF | NEON2RegMiscUBit,
1918   NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1919   NEON_URECPE  = NEON2RegMiscFixed | 0x0081C000,
1920   NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1921   NEON_FRECPE  = NEON2RegMiscFixed | 0x0081D000,
1922   NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1923   NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1924   NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1925   NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1926   NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1927 
1928   NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1929   NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1930 };
1931 
1932 // NEON instructions with two register operands (FP16).
1933 enum NEON2RegMiscFP16Op {
1934   NEON2RegMiscFP16Fixed = 0x0E780800,
1935   NEON2RegMiscFP16FMask = 0x9F7E0C00,
1936   NEON2RegMiscFP16Mask  = 0xBFFFFC00,
1937   NEON_FRINTN_H     = NEON2RegMiscFP16Fixed | 0x00018000,
1938   NEON_FRINTM_H     = NEON2RegMiscFP16Fixed | 0x00019000,
1939   NEON_FCVTNS_H     = NEON2RegMiscFP16Fixed | 0x0001A000,
1940   NEON_FCVTMS_H     = NEON2RegMiscFP16Fixed | 0x0001B000,
1941   NEON_FCVTAS_H     = NEON2RegMiscFP16Fixed | 0x0001C000,
1942   NEON_SCVTF_H      = NEON2RegMiscFP16Fixed | 0x0001D000,
1943   NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000,
1944   NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000,
1945   NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000,
1946   NEON_FABS_H       = NEON2RegMiscFP16Fixed | 0x0080F000,
1947   NEON_FRINTP_H     = NEON2RegMiscFP16Fixed | 0x00818000,
1948   NEON_FRINTZ_H     = NEON2RegMiscFP16Fixed | 0x00819000,
1949   NEON_FCVTPS_H     = NEON2RegMiscFP16Fixed | 0x0081A000,
1950   NEON_FCVTZS_H     = NEON2RegMiscFP16Fixed | 0x0081B000,
1951   NEON_FRECPE_H     = NEON2RegMiscFP16Fixed | 0x0081D000,
1952   NEON_FRINTA_H     = NEON2RegMiscFP16Fixed | 0x20018000,
1953   NEON_FRINTX_H     = NEON2RegMiscFP16Fixed | 0x20019000,
1954   NEON_FCVTNU_H     = NEON2RegMiscFP16Fixed | 0x2001A000,
1955   NEON_FCVTMU_H     = NEON2RegMiscFP16Fixed | 0x2001B000,
1956   NEON_FCVTAU_H     = NEON2RegMiscFP16Fixed | 0x2001C000,
1957   NEON_UCVTF_H      = NEON2RegMiscFP16Fixed | 0x2001D000,
1958   NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000,
1959   NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000,
1960   NEON_FNEG_H       = NEON2RegMiscFP16Fixed | 0x2080F000,
1961   NEON_FRINTI_H     = NEON2RegMiscFP16Fixed | 0x20819000,
1962   NEON_FCVTPU_H     = NEON2RegMiscFP16Fixed | 0x2081A000,
1963   NEON_FCVTZU_H     = NEON2RegMiscFP16Fixed | 0x2081B000,
1964   NEON_FRSQRTE_H    = NEON2RegMiscFP16Fixed | 0x2081D000,
1965   NEON_FSQRT_H      = NEON2RegMiscFP16Fixed | 0x2081F000
1966 };
1967 
1968 // NEON instructions with three same-type operands.
1969 enum NEON3SameOp {
1970   NEON3SameFixed = 0x0E200400,
1971   NEON3SameFMask = 0x9F200400,
1972   NEON3SameMask =  0xBF20FC00,
1973   NEON3SameUBit =  0x20000000,
1974   NEON_ADD    = NEON3SameFixed | 0x00008000,
1975   NEON_ADDP   = NEON3SameFixed | 0x0000B800,
1976   NEON_SHADD  = NEON3SameFixed | 0x00000000,
1977   NEON_SHSUB  = NEON3SameFixed | 0x00002000,
1978   NEON_SRHADD = NEON3SameFixed | 0x00001000,
1979   NEON_CMEQ   = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1980   NEON_CMGE   = NEON3SameFixed | 0x00003800,
1981   NEON_CMGT   = NEON3SameFixed | 0x00003000,
1982   NEON_CMHI   = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1983   NEON_CMHS   = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1984   NEON_CMTST  = NEON3SameFixed | 0x00008800,
1985   NEON_MLA    = NEON3SameFixed | 0x00009000,
1986   NEON_MLS    = NEON3SameFixed | 0x20009000,
1987   NEON_MUL    = NEON3SameFixed | 0x00009800,
1988   NEON_PMUL   = NEON3SameFixed | 0x20009800,
1989   NEON_SRSHL  = NEON3SameFixed | 0x00005000,
1990   NEON_SQSHL  = NEON3SameFixed | 0x00004800,
1991   NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1992   NEON_SSHL   = NEON3SameFixed | 0x00004000,
1993   NEON_SMAX   = NEON3SameFixed | 0x00006000,
1994   NEON_SMAXP  = NEON3SameFixed | 0x0000A000,
1995   NEON_SMIN   = NEON3SameFixed | 0x00006800,
1996   NEON_SMINP  = NEON3SameFixed | 0x0000A800,
1997   NEON_SABD   = NEON3SameFixed | 0x00007000,
1998   NEON_SABA   = NEON3SameFixed | 0x00007800,
1999   NEON_UABD   = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
2000   NEON_UABA   = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
2001   NEON_SQADD  = NEON3SameFixed | 0x00000800,
2002   NEON_SQSUB  = NEON3SameFixed | 0x00002800,
2003   NEON_SUB    = NEON3SameFixed | NEON3SameUBit | 0x00008000,
2004   NEON_UHADD  = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
2005   NEON_UHSUB  = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
2006   NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
2007   NEON_UMAX   = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
2008   NEON_UMAXP  = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
2009   NEON_UMIN   = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
2010   NEON_UMINP  = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
2011   NEON_URSHL  = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
2012   NEON_UQADD  = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
2013   NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
2014   NEON_UQSHL  = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
2015   NEON_UQSUB  = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
2016   NEON_USHL   = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
2017   NEON_SQDMULH  = NEON3SameFixed | 0x0000B000,
2018   NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
2019 
2020   // NEON floating point instructions with three same-type operands.
2021   NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
2022   NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
2023   NEON3SameFPMask = NEON3SameMask | 0x00800000,
2024   NEON_FADD    = NEON3SameFixed | 0x0000D000,
2025   NEON_FSUB    = NEON3SameFixed | 0x0080D000,
2026   NEON_FMUL    = NEON3SameFixed | 0x2000D800,
2027   NEON_FDIV    = NEON3SameFixed | 0x2000F800,
2028   NEON_FMAX    = NEON3SameFixed | 0x0000F000,
2029   NEON_FMAXNM  = NEON3SameFixed | 0x0000C000,
2030   NEON_FMAXP   = NEON3SameFixed | 0x2000F000,
2031   NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
2032   NEON_FMIN    = NEON3SameFixed | 0x0080F000,
2033   NEON_FMINNM  = NEON3SameFixed | 0x0080C000,
2034   NEON_FMINP   = NEON3SameFixed | 0x2080F000,
2035   NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
2036   NEON_FMLA    = NEON3SameFixed | 0x0000C800,
2037   NEON_FMLS    = NEON3SameFixed | 0x0080C800,
2038   NEON_FMULX   = NEON3SameFixed | 0x0000D800,
2039   NEON_FRECPS  = NEON3SameFixed | 0x0000F800,
2040   NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
2041   NEON_FABD    = NEON3SameFixed | 0x2080D000,
2042   NEON_FADDP   = NEON3SameFixed | 0x2000D000,
2043   NEON_FCMEQ   = NEON3SameFixed | 0x0000E000,
2044   NEON_FCMGE   = NEON3SameFixed | 0x2000E000,
2045   NEON_FCMGT   = NEON3SameFixed | 0x2080E000,
2046   NEON_FACGE   = NEON3SameFixed | 0x2000E800,
2047   NEON_FACGT   = NEON3SameFixed | 0x2080E800,
2048 
2049   // NEON logical instructions with three same-type operands.
2050   NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
2051   NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
2052   NEON3SameLogicalMask = 0xBFE0FC00,
2053   NEON3SameLogicalFormatMask = NEON_Q,
2054   NEON_AND = NEON3SameLogicalFixed | 0x00000000,
2055   NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
2056   NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
2057   NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
2058   NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
2059   NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
2060   NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
2061   NEON_BSL = NEON3SameLogicalFixed | 0x20400000,
2062 
2063   // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same.
2064   NEON3SameFHMMask = 0xBFE0FC00,                // U  size  opcode
2065   NEON_FMLAL   = NEON3SameFixed | 0x0000E800,   // 0    00   11101
2066   NEON_FMLAL2  = NEON3SameFixed | 0x2000C800,   // 1    00   11001
2067   NEON_FMLSL   = NEON3SameFixed | 0x0080E800,   // 0    10   11101
2068   NEON_FMLSL2  = NEON3SameFixed | 0x2080C800    // 1    10   11001
2069 };
2070 
2071 
2072 enum NEON3SameFP16 {
2073   NEON3SameFP16Fixed = 0x0E400400,
2074   NEON3SameFP16FMask = 0x9F60C400,
2075   NEON3SameFP16Mask =  0xBFE0FC00,
2076   NEON_FMAXNM_H  = NEON3SameFP16Fixed | 0x00000000,
2077   NEON_FMLA_H    = NEON3SameFP16Fixed | 0x00000800,
2078   NEON_FADD_H    = NEON3SameFP16Fixed | 0x00001000,
2079   NEON_FMULX_H   = NEON3SameFP16Fixed | 0x00001800,
2080   NEON_FCMEQ_H   = NEON3SameFP16Fixed | 0x00002000,
2081   NEON_FMAX_H    = NEON3SameFP16Fixed | 0x00003000,
2082   NEON_FRECPS_H  = NEON3SameFP16Fixed | 0x00003800,
2083   NEON_FMINNM_H  = NEON3SameFP16Fixed | 0x00800000,
2084   NEON_FMLS_H    = NEON3SameFP16Fixed | 0x00800800,
2085   NEON_FSUB_H    = NEON3SameFP16Fixed | 0x00801000,
2086   NEON_FMIN_H    = NEON3SameFP16Fixed | 0x00803000,
2087   NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800,
2088   NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000,
2089   NEON_FADDP_H   = NEON3SameFP16Fixed | 0x20001000,
2090   NEON_FMUL_H    = NEON3SameFP16Fixed | 0x20001800,
2091   NEON_FCMGE_H   = NEON3SameFP16Fixed | 0x20002000,
2092   NEON_FACGE_H   = NEON3SameFP16Fixed | 0x20002800,
2093   NEON_FMAXP_H   = NEON3SameFP16Fixed | 0x20003000,
2094   NEON_FDIV_H    = NEON3SameFP16Fixed | 0x20003800,
2095   NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000,
2096   NEON_FABD_H    = NEON3SameFP16Fixed | 0x20801000,
2097   NEON_FCMGT_H   = NEON3SameFP16Fixed | 0x20802000,
2098   NEON_FACGT_H   = NEON3SameFP16Fixed | 0x20802800,
2099   NEON_FMINP_H   = NEON3SameFP16Fixed | 0x20803000
2100 };
2101 
2102 
2103 // 'Extra' NEON instructions with three same-type operands.
2104 enum NEON3SameExtraOp {
2105   NEON3SameExtraFixed = 0x0E008400,
2106   NEON3SameExtraUBit = 0x20000000,
2107   NEON3SameExtraFMask = 0x9E208400,
2108   NEON3SameExtraMask = 0xBE20FC00,
2109   NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit,
2110   NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800,
2111   NEON_SDOT = NEON3SameExtraFixed | 0x00001000,
2112   NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000,
2113 
2114   /* v8.3 Complex Numbers */
2115   NEON3SameExtraFCFixed = 0x2E00C400,
2116   NEON3SameExtraFCFMask = 0xBF20C400,
2117   // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>.
2118   NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000,
2119   NEON_FCMLA = NEON3SameExtraFCFixed,
2120   // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>.
2121   NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800,
2122   NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000
2123   // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED.
2124 };
2125 
2126 // NEON instructions with three different-type operands.
2127 enum NEON3DifferentOp {
2128   NEON3DifferentFixed = 0x0E200000,
2129   NEON3DifferentFMask = 0x9F200C00,
2130   NEON3DifferentMask  = 0xFF20FC00,
2131   NEON_ADDHN    = NEON3DifferentFixed | 0x00004000,
2132   NEON_ADDHN2   = NEON_ADDHN | NEON_Q,
2133   NEON_PMULL    = NEON3DifferentFixed | 0x0000E000,
2134   NEON_PMULL2   = NEON_PMULL | NEON_Q,
2135   NEON_RADDHN   = NEON3DifferentFixed | 0x20004000,
2136   NEON_RADDHN2  = NEON_RADDHN | NEON_Q,
2137   NEON_RSUBHN   = NEON3DifferentFixed | 0x20006000,
2138   NEON_RSUBHN2  = NEON_RSUBHN | NEON_Q,
2139   NEON_SABAL    = NEON3DifferentFixed | 0x00005000,
2140   NEON_SABAL2   = NEON_SABAL | NEON_Q,
2141   NEON_SABDL    = NEON3DifferentFixed | 0x00007000,
2142   NEON_SABDL2   = NEON_SABDL | NEON_Q,
2143   NEON_SADDL    = NEON3DifferentFixed | 0x00000000,
2144   NEON_SADDL2   = NEON_SADDL | NEON_Q,
2145   NEON_SADDW    = NEON3DifferentFixed | 0x00001000,
2146   NEON_SADDW2   = NEON_SADDW | NEON_Q,
2147   NEON_SMLAL    = NEON3DifferentFixed | 0x00008000,
2148   NEON_SMLAL2   = NEON_SMLAL | NEON_Q,
2149   NEON_SMLSL    = NEON3DifferentFixed | 0x0000A000,
2150   NEON_SMLSL2   = NEON_SMLSL | NEON_Q,
2151   NEON_SMULL    = NEON3DifferentFixed | 0x0000C000,
2152   NEON_SMULL2   = NEON_SMULL | NEON_Q,
2153   NEON_SSUBL    = NEON3DifferentFixed | 0x00002000,
2154   NEON_SSUBL2   = NEON_SSUBL | NEON_Q,
2155   NEON_SSUBW    = NEON3DifferentFixed | 0x00003000,
2156   NEON_SSUBW2   = NEON_SSUBW | NEON_Q,
2157   NEON_SQDMLAL  = NEON3DifferentFixed | 0x00009000,
2158   NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
2159   NEON_SQDMLSL  = NEON3DifferentFixed | 0x0000B000,
2160   NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
2161   NEON_SQDMULL  = NEON3DifferentFixed | 0x0000D000,
2162   NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
2163   NEON_SUBHN    = NEON3DifferentFixed | 0x00006000,
2164   NEON_SUBHN2   = NEON_SUBHN | NEON_Q,
2165   NEON_UABAL    = NEON_SABAL | NEON3SameUBit,
2166   NEON_UABAL2   = NEON_UABAL | NEON_Q,
2167   NEON_UABDL    = NEON_SABDL | NEON3SameUBit,
2168   NEON_UABDL2   = NEON_UABDL | NEON_Q,
2169   NEON_UADDL    = NEON_SADDL | NEON3SameUBit,
2170   NEON_UADDL2   = NEON_UADDL | NEON_Q,
2171   NEON_UADDW    = NEON_SADDW | NEON3SameUBit,
2172   NEON_UADDW2   = NEON_UADDW | NEON_Q,
2173   NEON_UMLAL    = NEON_SMLAL | NEON3SameUBit,
2174   NEON_UMLAL2   = NEON_UMLAL | NEON_Q,
2175   NEON_UMLSL    = NEON_SMLSL | NEON3SameUBit,
2176   NEON_UMLSL2   = NEON_UMLSL | NEON_Q,
2177   NEON_UMULL    = NEON_SMULL | NEON3SameUBit,
2178   NEON_UMULL2   = NEON_UMULL | NEON_Q,
2179   NEON_USUBL    = NEON_SSUBL | NEON3SameUBit,
2180   NEON_USUBL2   = NEON_USUBL | NEON_Q,
2181   NEON_USUBW    = NEON_SSUBW | NEON3SameUBit,
2182   NEON_USUBW2   = NEON_USUBW | NEON_Q
2183 };
2184 
2185 // NEON instructions operating across vectors.
2186 enum NEONAcrossLanesOp {
2187   NEONAcrossLanesFixed = 0x0E300800,
2188   NEONAcrossLanesFMask = 0x9F3E0C00,
2189   NEONAcrossLanesMask  = 0xBF3FFC00,
2190   NEON_ADDV   = NEONAcrossLanesFixed | 0x0001B000,
2191   NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
2192   NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
2193   NEON_SMAXV  = NEONAcrossLanesFixed | 0x0000A000,
2194   NEON_SMINV  = NEONAcrossLanesFixed | 0x0001A000,
2195   NEON_UMAXV  = NEONAcrossLanesFixed | 0x2000A000,
2196   NEON_UMINV  = NEONAcrossLanesFixed | 0x2001A000,
2197 
2198   NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000,
2199   NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000,
2200   NEONAcrossLanesFP16Mask  = NEONAcrossLanesMask  | 0x20800000,
2201   NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000,
2202   NEON_FMAXV_H   = NEONAcrossLanesFP16Fixed | 0x00003000,
2203   NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000,
2204   NEON_FMINV_H   = NEONAcrossLanesFP16Fixed | 0x00803000,
2205 
2206   // NEON floating point across instructions.
2207   NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000,
2208   NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000,
2209   NEONAcrossLanesFPMask  = NEONAcrossLanesMask  | 0x20800000,
2210 
2211   NEON_FMAXV   = NEONAcrossLanesFPFixed | 0x2000F000,
2212   NEON_FMINV   = NEONAcrossLanesFPFixed | 0x2080F000,
2213   NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
2214   NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
2215 };
2216 
2217 // NEON instructions with indexed element operand.
2218 enum NEONByIndexedElementOp {
2219   NEONByIndexedElementFixed = 0x0F000000,
2220   NEONByIndexedElementFMask = 0x9F000400,
2221   NEONByIndexedElementMask  = 0xBF00F400,
2222   NEON_MUL_byelement   = NEONByIndexedElementFixed | 0x00008000,
2223   NEON_MLA_byelement   = NEONByIndexedElementFixed | 0x20000000,
2224   NEON_MLS_byelement   = NEONByIndexedElementFixed | 0x20004000,
2225   NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
2226   NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
2227   NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
2228   NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
2229   NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
2230   NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
2231   NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
2232   NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
2233   NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
2234   NEON_SQDMULH_byelement  = NEONByIndexedElementFixed | 0x0000C000,
2235   NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
2236   NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000,
2237   NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000,
2238   NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000,
2239   NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000,
2240 
2241   NEON_FMLA_H_byelement   = NEONByIndexedElementFixed | 0x00001000,
2242   NEON_FMLS_H_byelement   = NEONByIndexedElementFixed | 0x00005000,
2243   NEON_FMUL_H_byelement   = NEONByIndexedElementFixed | 0x00009000,
2244   NEON_FMULX_H_byelement  = NEONByIndexedElementFixed | 0x20009000,
2245 
2246   // Floating point instructions.
2247   NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
2248   NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
2249   NEON_FMLA_byelement  = NEONByIndexedElementFPFixed | 0x00001000,
2250   NEON_FMLS_byelement  = NEONByIndexedElementFPFixed | 0x00005000,
2251   NEON_FMUL_byelement  = NEONByIndexedElementFPFixed | 0x00009000,
2252   NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000,
2253 
2254   // FMLAL-like instructions.
2255   // For all cases: U = x, size = 10, opcode = xx00
2256   NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000,
2257   NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000,
2258   NEONByIndexedElementFPLongMask = 0xBFC0F400,
2259   NEON_FMLAL_H_byelement  = NEONByIndexedElementFixed | 0x00800000,
2260   NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000,
2261   NEON_FMLSL_H_byelement  = NEONByIndexedElementFixed | 0x00804000,
2262   NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000,
2263 
2264   // Complex instruction(s).
2265   // This is necessary because the 'rot' encoding moves into the
2266   // NEONByIndex..Mask space.
2267   NEONByIndexedElementFPComplexMask = 0xBF009400,
2268   NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000
2269 };
2270 
2271 // NEON register copy.
2272 enum NEONCopyOp {
2273   NEONCopyFixed = 0x0E000400,
2274   NEONCopyFMask = 0x9FE08400,
2275   NEONCopyMask  = 0x3FE08400,
2276   NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
2277   NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
2278   NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
2279   NEONCopyDupGeneralMask = NEONCopyDupElementMask,
2280   NEONCopyUmovMask       = NEONCopyMask | 0x20007800,
2281   NEONCopySmovMask       = NEONCopyMask | 0x20007800,
2282   NEON_INS_ELEMENT       = NEONCopyFixed | 0x60000000,
2283   NEON_INS_GENERAL       = NEONCopyFixed | 0x40001800,
2284   NEON_DUP_ELEMENT       = NEONCopyFixed | 0x00000000,
2285   NEON_DUP_GENERAL       = NEONCopyFixed | 0x00000800,
2286   NEON_SMOV              = NEONCopyFixed | 0x00002800,
2287   NEON_UMOV              = NEONCopyFixed | 0x00003800
2288 };
2289 
2290 // NEON extract.
2291 enum NEONExtractOp {
2292   NEONExtractFixed = 0x2E000000,
2293   NEONExtractFMask = 0xBF208400,
2294   NEONExtractMask =  0xBFE08400,
2295   NEON_EXT = NEONExtractFixed | 0x00000000
2296 };
2297 
2298 enum NEONLoadStoreMultiOp {
2299   NEONLoadStoreMultiL    = 0x00400000,
2300   NEONLoadStoreMulti1_1v = 0x00007000,
2301   NEONLoadStoreMulti1_2v = 0x0000A000,
2302   NEONLoadStoreMulti1_3v = 0x00006000,
2303   NEONLoadStoreMulti1_4v = 0x00002000,
2304   NEONLoadStoreMulti2    = 0x00008000,
2305   NEONLoadStoreMulti3    = 0x00004000,
2306   NEONLoadStoreMulti4    = 0x00000000
2307 };
2308 
2309 // NEON load/store multiple structures.
2310 enum NEONLoadStoreMultiStructOp {
2311   NEONLoadStoreMultiStructFixed = 0x0C000000,
2312   NEONLoadStoreMultiStructFMask = 0xBFBF0000,
2313   NEONLoadStoreMultiStructMask  = 0xBFFFF000,
2314   NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
2315   NEONLoadStoreMultiStructLoad  = NEONLoadStoreMultiStructFixed |
2316                                   NEONLoadStoreMultiL,
2317   NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
2318   NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
2319   NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
2320   NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
2321   NEON_LD2    = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
2322   NEON_LD3    = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
2323   NEON_LD4    = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
2324   NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
2325   NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
2326   NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
2327   NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
2328   NEON_ST2    = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
2329   NEON_ST3    = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
2330   NEON_ST4    = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
2331 };
2332 
2333 // NEON load/store multiple structures with post-index addressing.
2334 enum NEONLoadStoreMultiStructPostIndexOp {
2335   NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
2336   NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
2337   NEONLoadStoreMultiStructPostIndexMask  = 0xBFE0F000,
2338   NEONLoadStoreMultiStructPostIndex = 0x00800000,
2339   NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
2340   NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
2341   NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
2342   NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
2343   NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
2344   NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
2345   NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
2346   NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
2347   NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
2348   NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
2349   NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
2350   NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
2351   NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
2352   NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
2353 };
2354 
2355 enum NEONLoadStoreSingleOp {
2356   NEONLoadStoreSingle1        = 0x00000000,
2357   NEONLoadStoreSingle2        = 0x00200000,
2358   NEONLoadStoreSingle3        = 0x00002000,
2359   NEONLoadStoreSingle4        = 0x00202000,
2360   NEONLoadStoreSingleL        = 0x00400000,
2361   NEONLoadStoreSingle_b       = 0x00000000,
2362   NEONLoadStoreSingle_h       = 0x00004000,
2363   NEONLoadStoreSingle_s       = 0x00008000,
2364   NEONLoadStoreSingle_d       = 0x00008400,
2365   NEONLoadStoreSingleAllLanes = 0x0000C000,
2366   NEONLoadStoreSingleLenMask  = 0x00202000
2367 };
2368 
2369 // NEON load/store single structure.
2370 enum NEONLoadStoreSingleStructOp {
2371   NEONLoadStoreSingleStructFixed = 0x0D000000,
2372   NEONLoadStoreSingleStructFMask = 0xBF9F0000,
2373   NEONLoadStoreSingleStructMask  = 0xBFFFE000,
2374   NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
2375   NEONLoadStoreSingleStructLoad  = NEONLoadStoreSingleStructFixed |
2376                                    NEONLoadStoreSingleL,
2377   NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
2378                                    NEONLoadStoreSingleStructLoad,
2379   NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
2380                                    NEONLoadStoreSingleStructLoad,
2381   NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
2382                                    NEONLoadStoreSingleStructLoad,
2383   NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
2384                                    NEONLoadStoreSingleStructLoad,
2385   NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
2386                                     NEONLoadStoreSingleStructFixed,
2387   NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
2388                                     NEONLoadStoreSingleStructFixed,
2389   NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
2390                                     NEONLoadStoreSingleStructFixed,
2391   NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
2392                                     NEONLoadStoreSingleStructFixed,
2393   NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
2394   NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
2395   NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
2396   NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
2397   NEON_LD1R  = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
2398   NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
2399   NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
2400   NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
2401   NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
2402 
2403   NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
2404   NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
2405   NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
2406   NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
2407   NEON_LD2R  = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
2408   NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
2409   NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
2410   NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
2411   NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
2412 
2413   NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
2414   NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
2415   NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
2416   NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
2417   NEON_LD3R  = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
2418   NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
2419   NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
2420   NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
2421   NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
2422 
2423   NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
2424   NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
2425   NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
2426   NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
2427   NEON_LD4R  = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
2428   NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
2429   NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
2430   NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
2431   NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
2432 };
2433 
2434 // NEON load/store single structure with post-index addressing.
2435 enum NEONLoadStoreSingleStructPostIndexOp {
2436   NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
2437   NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
2438   NEONLoadStoreSingleStructPostIndexMask  = 0xBFE0E000,
2439   NEONLoadStoreSingleStructPostIndex =      0x00800000,
2440   NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
2441   NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
2442   NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
2443   NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
2444   NEON_LD1R_post  = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
2445   NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
2446   NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
2447   NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
2448   NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
2449 
2450   NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
2451   NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
2452   NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
2453   NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
2454   NEON_LD2R_post  = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
2455   NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
2456   NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
2457   NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
2458   NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
2459 
2460   NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
2461   NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
2462   NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
2463   NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
2464   NEON_LD3R_post  = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
2465   NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
2466   NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
2467   NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
2468   NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
2469 
2470   NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
2471   NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
2472   NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
2473   NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
2474   NEON_LD4R_post  = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
2475   NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
2476   NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
2477   NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
2478   NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
2479 };
2480 
2481 // NEON modified immediate.
2482 enum NEONModifiedImmediateOp {
2483   NEONModifiedImmediateFixed = 0x0F000400,
2484   NEONModifiedImmediateFMask = 0x9FF80400,
2485   NEONModifiedImmediateOpBit = 0x20000000,
2486   NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800,
2487   NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
2488   NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
2489   NEONModifiedImmediate_ORR  = NEONModifiedImmediateFixed | 0x00001000,
2490   NEONModifiedImmediate_BIC  = NEONModifiedImmediateFixed | 0x20001000
2491 };
2492 
2493 // NEON shift immediate.
2494 enum NEONShiftImmediateOp {
2495   NEONShiftImmediateFixed = 0x0F000400,
2496   NEONShiftImmediateFMask = 0x9F800400,
2497   NEONShiftImmediateMask  = 0xBF80FC00,
2498   NEONShiftImmediateUBit  = 0x20000000,
2499   NEON_SHL      = NEONShiftImmediateFixed | 0x00005000,
2500   NEON_SSHLL    = NEONShiftImmediateFixed | 0x0000A000,
2501   NEON_USHLL    = NEONShiftImmediateFixed | 0x2000A000,
2502   NEON_SLI      = NEONShiftImmediateFixed | 0x20005000,
2503   NEON_SRI      = NEONShiftImmediateFixed | 0x20004000,
2504   NEON_SHRN     = NEONShiftImmediateFixed | 0x00008000,
2505   NEON_RSHRN    = NEONShiftImmediateFixed | 0x00008800,
2506   NEON_UQSHRN   = NEONShiftImmediateFixed | 0x20009000,
2507   NEON_UQRSHRN  = NEONShiftImmediateFixed | 0x20009800,
2508   NEON_SQSHRN   = NEONShiftImmediateFixed | 0x00009000,
2509   NEON_SQRSHRN  = NEONShiftImmediateFixed | 0x00009800,
2510   NEON_SQSHRUN  = NEONShiftImmediateFixed | 0x20008000,
2511   NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
2512   NEON_SSHR     = NEONShiftImmediateFixed | 0x00000000,
2513   NEON_SRSHR    = NEONShiftImmediateFixed | 0x00002000,
2514   NEON_USHR     = NEONShiftImmediateFixed | 0x20000000,
2515   NEON_URSHR    = NEONShiftImmediateFixed | 0x20002000,
2516   NEON_SSRA     = NEONShiftImmediateFixed | 0x00001000,
2517   NEON_SRSRA    = NEONShiftImmediateFixed | 0x00003000,
2518   NEON_USRA     = NEONShiftImmediateFixed | 0x20001000,
2519   NEON_URSRA    = NEONShiftImmediateFixed | 0x20003000,
2520   NEON_SQSHLU   = NEONShiftImmediateFixed | 0x20006000,
2521   NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
2522   NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
2523   NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
2524   NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
2525   NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
2526   NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
2527 };
2528 
2529 // NEON table.
2530 enum NEONTableOp {
2531   NEONTableFixed = 0x0E000000,
2532   NEONTableFMask = 0xBF208C00,
2533   NEONTableExt   = 0x00001000,
2534   NEONTableMask  = 0xBF20FC00,
2535   NEON_TBL_1v    = NEONTableFixed | 0x00000000,
2536   NEON_TBL_2v    = NEONTableFixed | 0x00002000,
2537   NEON_TBL_3v    = NEONTableFixed | 0x00004000,
2538   NEON_TBL_4v    = NEONTableFixed | 0x00006000,
2539   NEON_TBX_1v    = NEON_TBL_1v | NEONTableExt,
2540   NEON_TBX_2v    = NEON_TBL_2v | NEONTableExt,
2541   NEON_TBX_3v    = NEON_TBL_3v | NEONTableExt,
2542   NEON_TBX_4v    = NEON_TBL_4v | NEONTableExt
2543 };
2544 
2545 // NEON perm.
2546 enum NEONPermOp {
2547   NEONPermFixed = 0x0E000800,
2548   NEONPermFMask = 0xBF208C00,
2549   NEONPermMask  = 0x3F20FC00,
2550   NEON_UZP1 = NEONPermFixed | 0x00001000,
2551   NEON_TRN1 = NEONPermFixed | 0x00002000,
2552   NEON_ZIP1 = NEONPermFixed | 0x00003000,
2553   NEON_UZP2 = NEONPermFixed | 0x00005000,
2554   NEON_TRN2 = NEONPermFixed | 0x00006000,
2555   NEON_ZIP2 = NEONPermFixed | 0x00007000
2556 };
2557 
2558 // NEON scalar instructions with two register operands.
2559 enum NEONScalar2RegMiscOp {
2560   NEONScalar2RegMiscFixed = 0x5E200800,
2561   NEONScalar2RegMiscFMask = 0xDF3E0C00,
2562   NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
2563   NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
2564   NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
2565   NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
2566   NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
2567   NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
2568   NEON_ABS_scalar       = NEON_Q | NEONScalar | NEON_ABS,
2569   NEON_SQABS_scalar     = NEON_Q | NEONScalar | NEON_SQABS,
2570   NEON_NEG_scalar       = NEON_Q | NEONScalar | NEON_NEG,
2571   NEON_SQNEG_scalar     = NEON_Q | NEONScalar | NEON_SQNEG,
2572   NEON_SQXTN_scalar     = NEON_Q | NEONScalar | NEON_SQXTN,
2573   NEON_UQXTN_scalar     = NEON_Q | NEONScalar | NEON_UQXTN,
2574   NEON_SQXTUN_scalar    = NEON_Q | NEONScalar | NEON_SQXTUN,
2575   NEON_SUQADD_scalar    = NEON_Q | NEONScalar | NEON_SUQADD,
2576   NEON_USQADD_scalar    = NEON_Q | NEONScalar | NEON_USQADD,
2577 
2578   NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2579   NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2580 
2581   NEONScalar2RegMiscFPMask  = NEONScalar2RegMiscMask | 0x00800000,
2582   NEON_FRSQRTE_scalar    = NEON_Q | NEONScalar | NEON_FRSQRTE,
2583   NEON_FRECPE_scalar     = NEON_Q | NEONScalar | NEON_FRECPE,
2584   NEON_SCVTF_scalar      = NEON_Q | NEONScalar | NEON_SCVTF,
2585   NEON_UCVTF_scalar      = NEON_Q | NEONScalar | NEON_UCVTF,
2586   NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2587   NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2588   NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2589   NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2590   NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2591   NEON_FRECPX_scalar     = NEONScalar2RegMiscFixed | 0x0081F000,
2592   NEON_FCVTNS_scalar     = NEON_Q | NEONScalar | NEON_FCVTNS,
2593   NEON_FCVTNU_scalar     = NEON_Q | NEONScalar | NEON_FCVTNU,
2594   NEON_FCVTPS_scalar     = NEON_Q | NEONScalar | NEON_FCVTPS,
2595   NEON_FCVTPU_scalar     = NEON_Q | NEONScalar | NEON_FCVTPU,
2596   NEON_FCVTMS_scalar     = NEON_Q | NEONScalar | NEON_FCVTMS,
2597   NEON_FCVTMU_scalar     = NEON_Q | NEONScalar | NEON_FCVTMU,
2598   NEON_FCVTZS_scalar     = NEON_Q | NEONScalar | NEON_FCVTZS,
2599   NEON_FCVTZU_scalar     = NEON_Q | NEONScalar | NEON_FCVTZU,
2600   NEON_FCVTAS_scalar     = NEON_Q | NEONScalar | NEON_FCVTAS,
2601   NEON_FCVTAU_scalar     = NEON_Q | NEONScalar | NEON_FCVTAU,
2602   NEON_FCVTXN_scalar     = NEON_Q | NEONScalar | NEON_FCVTXN
2603 };
2604 
2605 // NEON instructions with two register operands (FP16).
2606 enum NEONScalar2RegMiscFP16Op {
2607   NEONScalar2RegMiscFP16Fixed = 0x5E780800,
2608   NEONScalar2RegMiscFP16FMask = 0xDF7E0C00,
2609   NEONScalar2RegMiscFP16Mask  = 0xFFFFFC00,
2610   NEON_FCVTNS_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTNS_H,
2611   NEON_FCVTMS_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTMS_H,
2612   NEON_FCVTAS_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTAS_H,
2613   NEON_SCVTF_H_scalar      = NEON_Q | NEONScalar | NEON_SCVTF_H,
2614   NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero,
2615   NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero,
2616   NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero,
2617   NEON_FCVTPS_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTPS_H,
2618   NEON_FCVTZS_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTZS_H,
2619   NEON_FRECPE_H_scalar     = NEON_Q | NEONScalar | NEON_FRECPE_H,
2620   NEON_FRECPX_H_scalar     = NEONScalar2RegMiscFP16Fixed | 0x0081F000,
2621   NEON_FCVTNU_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTNU_H,
2622   NEON_FCVTMU_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTMU_H,
2623   NEON_FCVTAU_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTAU_H,
2624   NEON_UCVTF_H_scalar      = NEON_Q | NEONScalar | NEON_UCVTF_H,
2625   NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero,
2626   NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero,
2627   NEON_FCVTPU_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTPU_H,
2628   NEON_FCVTZU_H_scalar     = NEON_Q | NEONScalar | NEON_FCVTZU_H,
2629   NEON_FRSQRTE_H_scalar    = NEON_Q | NEONScalar | NEON_FRSQRTE_H
2630 };
2631 
2632 // NEON scalar instructions with three same-type operands.
2633 enum NEONScalar3SameOp {
2634   NEONScalar3SameFixed = 0x5E200400,
2635   NEONScalar3SameFMask = 0xDF200400,
2636   NEONScalar3SameMask  = 0xFF20FC00,
2637   NEON_ADD_scalar    = NEON_Q | NEONScalar | NEON_ADD,
2638   NEON_CMEQ_scalar   = NEON_Q | NEONScalar | NEON_CMEQ,
2639   NEON_CMGE_scalar   = NEON_Q | NEONScalar | NEON_CMGE,
2640   NEON_CMGT_scalar   = NEON_Q | NEONScalar | NEON_CMGT,
2641   NEON_CMHI_scalar   = NEON_Q | NEONScalar | NEON_CMHI,
2642   NEON_CMHS_scalar   = NEON_Q | NEONScalar | NEON_CMHS,
2643   NEON_CMTST_scalar  = NEON_Q | NEONScalar | NEON_CMTST,
2644   NEON_SUB_scalar    = NEON_Q | NEONScalar | NEON_SUB,
2645   NEON_UQADD_scalar  = NEON_Q | NEONScalar | NEON_UQADD,
2646   NEON_SQADD_scalar  = NEON_Q | NEONScalar | NEON_SQADD,
2647   NEON_UQSUB_scalar  = NEON_Q | NEONScalar | NEON_UQSUB,
2648   NEON_SQSUB_scalar  = NEON_Q | NEONScalar | NEON_SQSUB,
2649   NEON_USHL_scalar   = NEON_Q | NEONScalar | NEON_USHL,
2650   NEON_SSHL_scalar   = NEON_Q | NEONScalar | NEON_SSHL,
2651   NEON_UQSHL_scalar  = NEON_Q | NEONScalar | NEON_UQSHL,
2652   NEON_SQSHL_scalar  = NEON_Q | NEONScalar | NEON_SQSHL,
2653   NEON_URSHL_scalar  = NEON_Q | NEONScalar | NEON_URSHL,
2654   NEON_SRSHL_scalar  = NEON_Q | NEONScalar | NEON_SRSHL,
2655   NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2656   NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2657   NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2658   NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2659 
2660   // NEON floating point scalar instructions with three same-type operands.
2661   NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2662   NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2663   NEONScalar3SameFPMask  = NEONScalar3SameMask | 0x00800000,
2664   NEON_FACGE_scalar   = NEON_Q | NEONScalar | NEON_FACGE,
2665   NEON_FACGT_scalar   = NEON_Q | NEONScalar | NEON_FACGT,
2666   NEON_FCMEQ_scalar   = NEON_Q | NEONScalar | NEON_FCMEQ,
2667   NEON_FCMGE_scalar   = NEON_Q | NEONScalar | NEON_FCMGE,
2668   NEON_FCMGT_scalar   = NEON_Q | NEONScalar | NEON_FCMGT,
2669   NEON_FMULX_scalar   = NEON_Q | NEONScalar | NEON_FMULX,
2670   NEON_FRECPS_scalar  = NEON_Q | NEONScalar | NEON_FRECPS,
2671   NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2672   NEON_FABD_scalar    = NEON_Q | NEONScalar | NEON_FABD
2673 };
2674 
2675 // NEON scalar FP16 instructions with three same-type operands.
2676 enum NEONScalar3SameFP16Op {
2677   NEONScalar3SameFP16Fixed = 0x5E400400,
2678   NEONScalar3SameFP16FMask = 0xDF60C400,
2679   NEONScalar3SameFP16Mask  = 0xFFE0FC00,
2680   NEON_FABD_H_scalar    = NEON_Q | NEONScalar | NEON_FABD_H,
2681   NEON_FMULX_H_scalar   = NEON_Q | NEONScalar | NEON_FMULX_H,
2682   NEON_FCMEQ_H_scalar   = NEON_Q | NEONScalar | NEON_FCMEQ_H,
2683   NEON_FCMGE_H_scalar   = NEON_Q | NEONScalar | NEON_FCMGE_H,
2684   NEON_FCMGT_H_scalar   = NEON_Q | NEONScalar | NEON_FCMGT_H,
2685   NEON_FACGE_H_scalar   = NEON_Q | NEONScalar | NEON_FACGE_H,
2686   NEON_FACGT_H_scalar   = NEON_Q | NEONScalar | NEON_FACGT_H,
2687   NEON_FRECPS_H_scalar  = NEON_Q | NEONScalar | NEON_FRECPS_H,
2688   NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H
2689 };
2690 
2691 // 'Extra' NEON scalar instructions with three same-type operands.
2692 enum NEONScalar3SameExtraOp {
2693   NEONScalar3SameExtraFixed = 0x5E008400,
2694   NEONScalar3SameExtraFMask = 0xDF208400,
2695   NEONScalar3SameExtraMask = 0xFF20FC00,
2696   NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH,
2697   NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH
2698 };
2699 
2700 // NEON scalar instructions with three different-type operands.
2701 enum NEONScalar3DiffOp {
2702   NEONScalar3DiffFixed = 0x5E200000,
2703   NEONScalar3DiffFMask = 0xDF200C00,
2704   NEONScalar3DiffMask  = NEON_Q | NEONScalar | NEON3DifferentMask,
2705   NEON_SQDMLAL_scalar  = NEON_Q | NEONScalar | NEON_SQDMLAL,
2706   NEON_SQDMLSL_scalar  = NEON_Q | NEONScalar | NEON_SQDMLSL,
2707   NEON_SQDMULL_scalar  = NEON_Q | NEONScalar | NEON_SQDMULL
2708 };
2709 
2710 // NEON scalar instructions with indexed element operand.
2711 enum NEONScalarByIndexedElementOp {
2712   NEONScalarByIndexedElementFixed = 0x5F000000,
2713   NEONScalarByIndexedElementFMask = 0xDF000400,
2714   NEONScalarByIndexedElementMask  = 0xFF00F400,
2715   NEON_SQDMLAL_byelement_scalar  = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2716   NEON_SQDMLSL_byelement_scalar  = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2717   NEON_SQDMULL_byelement_scalar  = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2718   NEON_SQDMULH_byelement_scalar  = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2719   NEON_SQRDMULH_byelement_scalar
2720     = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2721   NEON_SQRDMLAH_byelement_scalar
2722     = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement,
2723   NEON_SQRDMLSH_byelement_scalar
2724     = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement,
2725   NEON_FMLA_H_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMLA_H_byelement,
2726   NEON_FMLS_H_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMLS_H_byelement,
2727   NEON_FMUL_H_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMUL_H_byelement,
2728   NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement,
2729 
2730   // Floating point instructions.
2731   NEONScalarByIndexedElementFPFixed
2732     = NEONScalarByIndexedElementFixed | 0x00800000,
2733   NEONScalarByIndexedElementFPMask
2734     = NEONScalarByIndexedElementMask | 0x00800000,
2735   NEON_FMLA_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2736   NEON_FMLS_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2737   NEON_FMUL_byelement_scalar  = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2738   NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2739 };
2740 
2741 // NEON scalar register copy.
2742 enum NEONScalarCopyOp {
2743   NEONScalarCopyFixed = 0x5E000400,
2744   NEONScalarCopyFMask = 0xDFE08400,
2745   NEONScalarCopyMask  = 0xFFE0FC00,
2746   NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2747 };
2748 
2749 // NEON scalar pairwise instructions.
2750 enum NEONScalarPairwiseOp {
2751   NEONScalarPairwiseFixed = 0x5E300800,
2752   NEONScalarPairwiseFMask = 0xDF3E0C00,
2753   NEONScalarPairwiseMask  = 0xFFB1F800,
2754   NEON_ADDP_scalar      = NEONScalarPairwiseFixed | 0x0081B000,
2755   NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000,
2756   NEON_FADDP_h_scalar   = NEONScalarPairwiseFixed | 0x0000D000,
2757   NEON_FMAXP_h_scalar   = NEONScalarPairwiseFixed | 0x0000F000,
2758   NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000,
2759   NEON_FMINP_h_scalar   = NEONScalarPairwiseFixed | 0x0080F000,
2760   NEON_FMAXNMP_scalar   = NEONScalarPairwiseFixed | 0x2000C000,
2761   NEON_FMINNMP_scalar   = NEONScalarPairwiseFixed | 0x2080C000,
2762   NEON_FADDP_scalar     = NEONScalarPairwiseFixed | 0x2000D000,
2763   NEON_FMAXP_scalar     = NEONScalarPairwiseFixed | 0x2000F000,
2764   NEON_FMINP_scalar     = NEONScalarPairwiseFixed | 0x2080F000
2765 };
2766 
2767 // NEON scalar shift immediate.
2768 enum NEONScalarShiftImmediateOp {
2769   NEONScalarShiftImmediateFixed = 0x5F000400,
2770   NEONScalarShiftImmediateFMask = 0xDF800400,
2771   NEONScalarShiftImmediateMask  = 0xFF80FC00,
2772   NEON_SHL_scalar  =       NEON_Q | NEONScalar | NEON_SHL,
2773   NEON_SLI_scalar  =       NEON_Q | NEONScalar | NEON_SLI,
2774   NEON_SRI_scalar  =       NEON_Q | NEONScalar | NEON_SRI,
2775   NEON_SSHR_scalar =       NEON_Q | NEONScalar | NEON_SSHR,
2776   NEON_USHR_scalar =       NEON_Q | NEONScalar | NEON_USHR,
2777   NEON_SRSHR_scalar =      NEON_Q | NEONScalar | NEON_SRSHR,
2778   NEON_URSHR_scalar =      NEON_Q | NEONScalar | NEON_URSHR,
2779   NEON_SSRA_scalar =       NEON_Q | NEONScalar | NEON_SSRA,
2780   NEON_USRA_scalar =       NEON_Q | NEONScalar | NEON_USRA,
2781   NEON_SRSRA_scalar =      NEON_Q | NEONScalar | NEON_SRSRA,
2782   NEON_URSRA_scalar =      NEON_Q | NEONScalar | NEON_URSRA,
2783   NEON_UQSHRN_scalar =     NEON_Q | NEONScalar | NEON_UQSHRN,
2784   NEON_UQRSHRN_scalar =    NEON_Q | NEONScalar | NEON_UQRSHRN,
2785   NEON_SQSHRN_scalar =     NEON_Q | NEONScalar | NEON_SQSHRN,
2786   NEON_SQRSHRN_scalar =    NEON_Q | NEONScalar | NEON_SQRSHRN,
2787   NEON_SQSHRUN_scalar =    NEON_Q | NEONScalar | NEON_SQSHRUN,
2788   NEON_SQRSHRUN_scalar =   NEON_Q | NEONScalar | NEON_SQRSHRUN,
2789   NEON_SQSHLU_scalar =     NEON_Q | NEONScalar | NEON_SQSHLU,
2790   NEON_SQSHL_imm_scalar  = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2791   NEON_UQSHL_imm_scalar  = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2792   NEON_SCVTF_imm_scalar =  NEON_Q | NEONScalar | NEON_SCVTF_imm,
2793   NEON_UCVTF_imm_scalar =  NEON_Q | NEONScalar | NEON_UCVTF_imm,
2794   NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2795   NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2796 };
2797 
2798 enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp {
2799   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000,
2800   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
2801   SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
2802   LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed,
2803   LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
2804   LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2805   LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2806 };
2807 
2808 enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp {
2809   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000,
2810   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
2811   SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
2812   LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2813   LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2814 };
2815 
2816 enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp {
2817   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000,
2818   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000,
2819   SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000,
2820   LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed,
2821   LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000,
2822   LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000,
2823   LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000,
2824   LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
2825   LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000,
2826   LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000,
2827   LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000,
2828   LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000,
2829   LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000
2830 };
2831 
2832 enum SVE32BitGatherLoad_VectorPlusImmOp {
2833   SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000,
2834   SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
2835   SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
2836   LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed,
2837   LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000,
2838   LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000,
2839   LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000,
2840   LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000,
2841   LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000,
2842   LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000,
2843   LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000,
2844   LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000,
2845   LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000
2846 };
2847 
2848 enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp {
2849   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000,
2850   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010,
2851   SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010,
2852   PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed,
2853   PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
2854   PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2855   PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2856 };
2857 
2858 enum SVE32BitGatherPrefetch_VectorPlusImmOp {
2859   SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000,
2860   SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
2861   SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
2862   PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed,
2863   PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
2864   PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
2865   PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
2866 };
2867 
2868 enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp {
2869   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000,
2870   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000,
2871   SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000,
2872   ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000,
2873   ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000
2874 };
2875 
2876 enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp {
2877   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000,
2878   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000,
2879   SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000,
2880   ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed,
2881   ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
2882   ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000
2883 };
2884 
2885 enum SVE32BitScatterStore_VectorPlusImmOp {
2886   SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000,
2887   SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
2888   SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
2889   ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed,
2890   ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000,
2891   ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000
2892 };
2893 
2894 enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp {
2895   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000,
2896   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000,
2897   SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000,
2898   LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000,
2899   LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000,
2900   LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000,
2901   LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000,
2902   LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000,
2903   LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000,
2904   LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000,
2905   LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000,
2906   LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000,
2907   LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000
2908 };
2909 
2910 enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp {
2911   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
2912   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000,
2913   SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
2914   LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
2915   LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000,
2916   LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000,
2917   LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000,
2918   LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
2919   LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000,
2920   LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000,
2921   LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000,
2922   LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000,
2923   LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000
2924 };
2925 
2926 enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp {
2927   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000,
2928   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000,
2929   SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
2930   LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed,
2931   LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000,
2932   LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000,
2933   LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000,
2934   LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
2935   LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000,
2936   LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000,
2937   LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000,
2938   LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
2939   LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000,
2940   LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000,
2941   LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000,
2942   LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000,
2943   LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000
2944 };
2945 
2946 enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
2947   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000,
2948   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000,
2949   SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000,
2950   LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
2951   LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000,
2952   LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000,
2953   LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000,
2954   LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
2955   LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000,
2956   LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000,
2957   LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000,
2958   LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
2959   LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000,
2960   LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000,
2961   LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000,
2962   LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000,
2963   LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000
2964 };
2965 
2966 enum SVE64BitGatherLoad_VectorPlusImmOp {
2967   SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000,
2968   SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
2969   SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
2970   LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed,
2971   LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000,
2972   LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000,
2973   LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000,
2974   LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000,
2975   LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000,
2976   LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000,
2977   LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000,
2978   LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000,
2979   LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000,
2980   LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000,
2981   LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000,
2982   LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000,
2983   LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000
2984 };
2985 
2986 enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp {
2987   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
2988   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010,
2989   SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010,
2990   PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed,
2991   PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000,
2992   PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000,
2993   PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000
2994 };
2995 
2996 enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp {
2997   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000,
2998   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010,
2999   SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010,
3000   PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed,
3001   PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000,
3002   PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000,
3003   PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000
3004 };
3005 
3006 enum SVE64BitGatherPrefetch_VectorPlusImmOp {
3007   SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000,
3008   SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
3009   SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
3010   PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed,
3011   PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
3012   PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
3013   PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
3014 };
3015 
3016 enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp {
3017   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000,
3018   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000,
3019   SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
3020   ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
3021   ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
3022   ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000
3023 };
3024 
3025 enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp {
3026   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000,
3027   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000,
3028   SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
3029   ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed,
3030   ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
3031   ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
3032   ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000
3033 };
3034 
3035 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp {
3036   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000,
3037   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000,
3038   SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000,
3039   ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000,
3040   ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000,
3041   ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000
3042 };
3043 
3044 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
3045   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000,
3046   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000,
3047   SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000,
3048   ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
3049   ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
3050   ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
3051   ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000
3052 };
3053 
3054 enum SVE64BitScatterStore_VectorPlusImmOp {
3055   SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000,
3056   SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
3057   SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
3058   ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed,
3059   ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000,
3060   ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000,
3061   ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000
3062 };
3063 
3064 enum SVEAddressGenerationOp {
3065   SVEAddressGenerationFixed = 0x0420A000,
3066   SVEAddressGenerationFMask = 0xFF20F000,
3067   SVEAddressGenerationMask = 0xFFE0F000,
3068   ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed,
3069   ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000,
3070   ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000,
3071   ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000
3072 };
3073 
3074 enum SVEBitwiseLogicalUnpredicatedOp {
3075   SVEBitwiseLogicalUnpredicatedFixed = 0x04202000,
3076   SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000,
3077   SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00,
3078   AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000,
3079   ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000,
3080   EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000,
3081   BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000
3082 };
3083 
3084 enum SVEBitwiseLogicalWithImm_UnpredicatedOp {
3085   SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000,
3086   SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000,
3087   SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000,
3088   ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed,
3089   EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000,
3090   AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000
3091 };
3092 
3093 enum SVEBitwiseLogical_PredicatedOp {
3094   SVEBitwiseLogical_PredicatedFixed = 0x04180000,
3095   SVEBitwiseLogical_PredicatedFMask = 0xFF38E000,
3096   SVEBitwiseLogical_PredicatedMask = 0xFF3FE000,
3097   ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed,
3098   EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000,
3099   AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000,
3100   BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000
3101 };
3102 
3103 enum SVEBitwiseShiftByImm_PredicatedOp {
3104   SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000,
3105   SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000,
3106   SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000,
3107   ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed,
3108   LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000,
3109   LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000,
3110   ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000
3111 };
3112 
3113 enum SVEBitwiseShiftByVector_PredicatedOp {
3114   SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000,
3115   SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000,
3116   SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000,
3117   ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed,
3118   LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000,
3119   LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000,
3120   ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000,
3121   LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000,
3122   LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000
3123 };
3124 
3125 enum SVEBitwiseShiftByWideElements_PredicatedOp {
3126   SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000,
3127   SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000,
3128   SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000,
3129   ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed,
3130   LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000,
3131   LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000
3132 };
3133 
3134 enum SVEBitwiseShiftUnpredicatedOp {
3135   SVEBitwiseShiftUnpredicatedFixed = 0x04208000,
3136   SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000,
3137   SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00,
3138   ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed,
3139   LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400,
3140   LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00,
3141   ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000,
3142   LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400,
3143   LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00
3144 };
3145 
3146 enum SVEBroadcastBitmaskImmOp {
3147   SVEBroadcastBitmaskImmFixed = 0x05C00000,
3148   SVEBroadcastBitmaskImmFMask = 0xFFFC0000,
3149   SVEBroadcastBitmaskImmMask = 0xFFFC0000,
3150   DUPM_z_i = SVEBroadcastBitmaskImmFixed
3151 };
3152 
3153 enum SVEBroadcastFPImm_UnpredicatedOp {
3154   SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000,
3155   SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000,
3156   SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000,
3157   FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed
3158 };
3159 
3160 enum SVEBroadcastGeneralRegisterOp {
3161   SVEBroadcastGeneralRegisterFixed = 0x05203800,
3162   SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00,
3163   SVEBroadcastGeneralRegisterMask = 0xFF3FFC00,
3164   DUP_z_r = SVEBroadcastGeneralRegisterFixed
3165 };
3166 
3167 enum SVEBroadcastIndexElementOp {
3168   SVEBroadcastIndexElementFixed = 0x05202000,
3169   SVEBroadcastIndexElementFMask = 0xFF20FC00,
3170   SVEBroadcastIndexElementMask = 0xFF20FC00,
3171   DUP_z_zi = SVEBroadcastIndexElementFixed
3172 };
3173 
3174 enum SVEBroadcastIntImm_UnpredicatedOp {
3175   SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000,
3176   SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000,
3177   SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000,
3178   DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed
3179 };
3180 
3181 enum SVECompressActiveElementsOp {
3182   SVECompressActiveElementsFixed = 0x05A18000,
3183   SVECompressActiveElementsFMask = 0xFFBFE000,
3184   SVECompressActiveElementsMask = 0xFFBFE000,
3185   COMPACT_z_p_z = SVECompressActiveElementsFixed
3186 };
3187 
3188 enum SVEConditionallyBroadcastElementToVectorOp {
3189   SVEConditionallyBroadcastElementToVectorFixed = 0x05288000,
3190   SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000,
3191   SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000,
3192   CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed,
3193   CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000
3194 };
3195 
3196 enum SVEConditionallyExtractElementToGeneralRegisterOp {
3197   SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000,
3198   SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000,
3199   SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000,
3200   CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed,
3201   CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000
3202 };
3203 
3204 enum SVEConditionallyExtractElementToSIMDFPScalarOp {
3205   SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000,
3206   SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000,
3207   SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000,
3208   CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed,
3209   CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000
3210 };
3211 
3212 enum SVEConditionallyTerminateScalarsOp {
3213   SVEConditionallyTerminateScalarsFixed = 0x25202000,
3214   SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F,
3215   SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F,
3216   CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000,
3217   CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010
3218 };
3219 
3220 enum SVEConstructivePrefix_UnpredicatedOp {
3221   SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00,
3222   SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00,
3223   SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00,
3224   MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed
3225 };
3226 
3227 enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp {
3228   SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000,
3229   SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000,
3230   SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000,
3231   LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed,
3232   LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000,
3233   LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000,
3234   LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000,
3235   LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000,
3236   LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000,
3237   LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000,
3238   LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000,
3239   LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000,
3240   LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000,
3241   LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000,
3242   LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000,
3243   LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000,
3244   LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000,
3245   LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000,
3246   LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000
3247 };
3248 
3249 enum SVEContiguousLoad_ScalarPlusImmOp {
3250   SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000,
3251   SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000,
3252   SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000,
3253   LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed,
3254   LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000,
3255   LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000,
3256   LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000,
3257   LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000,
3258   LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000,
3259   LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000,
3260   LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000,
3261   LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000,
3262   LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000,
3263   LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000,
3264   LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000,
3265   LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000,
3266   LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000,
3267   LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000,
3268   LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000
3269 };
3270 
3271 enum SVEContiguousLoad_ScalarPlusScalarOp {
3272   SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000,
3273   SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000,
3274   SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000,
3275   LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed,
3276   LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000,
3277   LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000,
3278   LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000,
3279   LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000,
3280   LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000,
3281   LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000,
3282   LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000,
3283   LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000,
3284   LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000,
3285   LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000,
3286   LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000,
3287   LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000,
3288   LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000,
3289   LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000,
3290   LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000
3291 };
3292 
3293 enum SVEContiguousNonFaultLoad_ScalarPlusImmOp {
3294   SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000,
3295   SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000,
3296   SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000,
3297   LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed,
3298   LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000,
3299   LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000,
3300   LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000,
3301   LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000,
3302   LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000,
3303   LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000,
3304   LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000,
3305   LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000,
3306   LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000,
3307   LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000,
3308   LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000,
3309   LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000,
3310   LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000,
3311   LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000,
3312   LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000
3313 };
3314 
3315 enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp {
3316   SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000,
3317   SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000,
3318   SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000,
3319   LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed,
3320   LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000,
3321   LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000,
3322   LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000
3323 };
3324 
3325 enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp {
3326   SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000,
3327   SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000,
3328   SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000,
3329   LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed,
3330   LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000,
3331   LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000,
3332   LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000
3333 };
3334 
3335 enum SVEContiguousNonTemporalStore_ScalarPlusImmOp {
3336   SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000,
3337   SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000,
3338   SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000,
3339   STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed,
3340   STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000,
3341   STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000,
3342   STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000
3343 };
3344 
3345 enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp {
3346   SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000,
3347   SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000,
3348   SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000,
3349   STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed,
3350   STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000,
3351   STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000,
3352   STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000
3353 };
3354 
3355 enum SVEContiguousPrefetch_ScalarPlusImmOp {
3356   SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000,
3357   SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010,
3358   SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010,
3359   PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed,
3360   PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000,
3361   PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000,
3362   PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000
3363 };
3364 
3365 enum SVEContiguousPrefetch_ScalarPlusScalarOp {
3366   SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000,
3367   SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010,
3368   SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010,
3369   PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed,
3370   PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000,
3371   PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000,
3372   PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000
3373 };
3374 
3375 enum SVEContiguousStore_ScalarPlusImmOp {
3376   SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000,
3377   SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000,
3378   SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000,
3379   ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed,
3380   ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000,
3381   ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000,
3382   ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000
3383 };
3384 
3385 enum SVEContiguousStore_ScalarPlusScalarOp {
3386   SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000,
3387   SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000,
3388   SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000,
3389   ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed,
3390   ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000,
3391   ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000,
3392   ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000
3393 };
3394 
3395 enum SVECopyFPImm_PredicatedOp {
3396   SVECopyFPImm_PredicatedFixed = 0x0510C000,
3397   SVECopyFPImm_PredicatedFMask = 0xFF30E000,
3398   SVECopyFPImm_PredicatedMask = 0xFF30E000,
3399   FCPY_z_p_i = SVECopyFPImm_PredicatedFixed
3400 };
3401 
3402 enum SVECopyGeneralRegisterToVector_PredicatedOp {
3403   SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000,
3404   SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000,
3405   SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000,
3406   CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed
3407 };
3408 
3409 enum SVECopyIntImm_PredicatedOp {
3410   SVECopyIntImm_PredicatedFixed = 0x05100000,
3411   SVECopyIntImm_PredicatedFMask = 0xFF308000,
3412   SVECopyIntImm_PredicatedMask = 0xFF308000,
3413   CPY_z_p_i = SVECopyIntImm_PredicatedFixed
3414 };
3415 
3416 enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp {
3417   SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000,
3418   SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000,
3419   SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000,
3420   CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed
3421 };
3422 
3423 enum SVEElementCountOp {
3424   SVEElementCountFixed = 0x0420E000,
3425   SVEElementCountFMask = 0xFF30F800,
3426   SVEElementCountMask = 0xFFF0FC00,
3427   CNTB_r_s = SVEElementCountFixed,
3428   CNTH_r_s = SVEElementCountFixed | 0x00400000,
3429   CNTW_r_s = SVEElementCountFixed | 0x00800000,
3430   CNTD_r_s = SVEElementCountFixed | 0x00C00000
3431 };
3432 
3433 enum SVEExtractElementToGeneralRegisterOp {
3434   SVEExtractElementToGeneralRegisterFixed = 0x0520A000,
3435   SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000,
3436   SVEExtractElementToGeneralRegisterMask = 0xFF3FE000,
3437   LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed,
3438   LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000
3439 };
3440 
3441 enum SVEExtractElementToSIMDFPScalarRegisterOp {
3442   SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000,
3443   SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000,
3444   SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000,
3445   LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed,
3446   LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000
3447 };
3448 
3449 enum SVEFFRInitialiseOp {
3450   SVEFFRInitialiseFixed = 0x252C9000,
3451   SVEFFRInitialiseFMask = 0xFF3FFFFF,
3452   SVEFFRInitialiseMask = 0xFFFFFFFF,
3453   SETFFR_f = SVEFFRInitialiseFixed
3454 };
3455 
3456 enum SVEFFRWriteFromPredicateOp {
3457   SVEFFRWriteFromPredicateFixed = 0x25289000,
3458   SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F,
3459   SVEFFRWriteFromPredicateMask = 0xFFFFFE1F,
3460   WRFFR_f_p = SVEFFRWriteFromPredicateFixed
3461 };
3462 
3463 enum SVEFPAccumulatingReductionOp {
3464   SVEFPAccumulatingReductionFixed = 0x65182000,
3465   SVEFPAccumulatingReductionFMask = 0xFF38E000,
3466   SVEFPAccumulatingReductionMask = 0xFF3FE000,
3467   FADDA_v_p_z = SVEFPAccumulatingReductionFixed
3468 };
3469 
3470 enum SVEFPArithmeticUnpredicatedOp {
3471   SVEFPArithmeticUnpredicatedFixed = 0x65000000,
3472   SVEFPArithmeticUnpredicatedFMask = 0xFF20E000,
3473   SVEFPArithmeticUnpredicatedMask = 0xFF20FC00,
3474   FADD_z_zz = SVEFPArithmeticUnpredicatedFixed,
3475   FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400,
3476   FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800,
3477   FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00,
3478   FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800,
3479   FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00
3480 };
3481 
3482 enum SVEFPArithmeticWithImm_PredicatedOp {
3483   SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000,
3484   SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0,
3485   SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0,
3486   FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed,
3487   FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000,
3488   FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000,
3489   FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000,
3490   FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000,
3491   FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000,
3492   FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000,
3493   FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000
3494 };
3495 
3496 enum SVEFPArithmetic_PredicatedOp {
3497   SVEFPArithmetic_PredicatedFixed = 0x65008000,
3498   SVEFPArithmetic_PredicatedFMask = 0xFF30E000,
3499   SVEFPArithmetic_PredicatedMask = 0xFF3FE000,
3500   FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed,
3501   FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000,
3502   FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000,
3503   FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000,
3504   FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000,
3505   FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000,
3506   FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000,
3507   FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000,
3508   FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000,
3509   FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000,
3510   FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000,
3511   FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000,
3512   FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000
3513 };
3514 
3515 enum SVEFPCompareVectorsOp {
3516   SVEFPCompareVectorsFixed = 0x65004000,
3517   SVEFPCompareVectorsFMask = 0xFF204000,
3518   SVEFPCompareVectorsMask = 0xFF20E010,
3519   FCMGE_p_p_zz = SVEFPCompareVectorsFixed,
3520   FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010,
3521   FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000,
3522   FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010,
3523   FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000,
3524   FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010,
3525   FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010
3526 };
3527 
3528 enum SVEFPCompareWithZeroOp {
3529   SVEFPCompareWithZeroFixed = 0x65102000,
3530   SVEFPCompareWithZeroFMask = 0xFF38E000,
3531   SVEFPCompareWithZeroMask = 0xFF3FE010,
3532   FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed,
3533   FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010,
3534   FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000,
3535   FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010,
3536   FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000,
3537   FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000
3538 };
3539 
3540 enum SVEFPComplexAdditionOp {
3541   SVEFPComplexAdditionFixed = 0x64008000,
3542   SVEFPComplexAdditionFMask = 0xFF3EE000,
3543   SVEFPComplexAdditionMask = 0xFF3EE000,
3544   FCADD_z_p_zz = SVEFPComplexAdditionFixed
3545 };
3546 
3547 enum SVEFPComplexMulAddOp {
3548   SVEFPComplexMulAddFixed = 0x64000000,
3549   SVEFPComplexMulAddFMask = 0xFF208000,
3550   SVEFPComplexMulAddMask = 0xFF208000,
3551   FCMLA_z_p_zzz = SVEFPComplexMulAddFixed
3552 };
3553 
3554 enum SVEFPComplexMulAddIndexOp {
3555   SVEFPComplexMulAddIndexFixed = 0x64201000,
3556   SVEFPComplexMulAddIndexFMask = 0xFF20F000,
3557   SVEFPComplexMulAddIndexMask = 0xFFE0F000,
3558   FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000,
3559   FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000
3560 };
3561 
3562 enum SVEFPConvertPrecisionOp {
3563   SVEFPConvertPrecisionFixed = 0x6508A000,
3564   SVEFPConvertPrecisionFMask = 0xFF3CE000,
3565   SVEFPConvertPrecisionMask = 0xFFFFE000,
3566   FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000,
3567   FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000,
3568   FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000,
3569   FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000,
3570   FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000,
3571   FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000
3572 };
3573 
3574 enum SVEFPConvertToIntOp {
3575   SVEFPConvertToIntFixed = 0x6518A000,
3576   SVEFPConvertToIntFMask = 0xFF38E000,
3577   SVEFPConvertToIntMask = 0xFFFFE000,
3578   FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000,
3579   FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000,
3580   FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000,
3581   FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000,
3582   FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000,
3583   FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000,
3584   FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000,
3585   FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000,
3586   FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000,
3587   FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000,
3588   FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000,
3589   FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000,
3590   FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000,
3591   FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000
3592 };
3593 
3594 enum SVEFPExponentialAcceleratorOp {
3595   SVEFPExponentialAcceleratorFixed = 0x0420B800,
3596   SVEFPExponentialAcceleratorFMask = 0xFF20FC00,
3597   SVEFPExponentialAcceleratorMask = 0xFF3FFC00,
3598   FEXPA_z_z = SVEFPExponentialAcceleratorFixed
3599 };
3600 
3601 enum SVEFPFastReductionOp {
3602   SVEFPFastReductionFixed = 0x65002000,
3603   SVEFPFastReductionFMask = 0xFF38E000,
3604   SVEFPFastReductionMask = 0xFF3FE000,
3605   FADDV_v_p_z = SVEFPFastReductionFixed,
3606   FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000,
3607   FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000,
3608   FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000,
3609   FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000
3610 };
3611 
3612 enum SVEFPMulAddOp {
3613   SVEFPMulAddFixed = 0x65200000,
3614   SVEFPMulAddFMask = 0xFF200000,
3615   SVEFPMulAddMask = 0xFF20E000,
3616   FMLA_z_p_zzz = SVEFPMulAddFixed,
3617   FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000,
3618   FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000,
3619   FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000,
3620   FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000,
3621   FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000,
3622   FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000,
3623   FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000
3624 };
3625 
3626 enum SVEFPMulAddIndexOp {
3627   SVEFPMulAddIndexFixed = 0x64200000,
3628   SVEFPMulAddIndexFMask = 0xFF20F800,
3629   SVEFPMulAddIndexMask = 0xFFE0FC00,
3630   FMLA_z_zzzi_h = SVEFPMulAddIndexFixed,
3631   FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000,
3632   FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400,
3633   FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000,
3634   FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000,
3635   FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400,
3636   FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000,
3637   FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400
3638 };
3639 
3640 enum SVEFPMulIndexOp {
3641   SVEFPMulIndexFixed = 0x64202000,
3642   SVEFPMulIndexFMask = 0xFF20FC00,
3643   SVEFPMulIndexMask = 0xFFE0FC00,
3644   FMUL_z_zzi_h = SVEFPMulIndexFixed,
3645   FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000,
3646   FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000,
3647   FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000
3648 };
3649 
3650 enum SVEFPRoundToIntegralValueOp {
3651   SVEFPRoundToIntegralValueFixed = 0x6500A000,
3652   SVEFPRoundToIntegralValueFMask = 0xFF38E000,
3653   SVEFPRoundToIntegralValueMask = 0xFF3FE000,
3654   FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed,
3655   FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000,
3656   FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000,
3657   FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000,
3658   FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000,
3659   FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000,
3660   FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000
3661 };
3662 
3663 enum SVEFPTrigMulAddCoefficientOp {
3664   SVEFPTrigMulAddCoefficientFixed = 0x65108000,
3665   SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00,
3666   SVEFPTrigMulAddCoefficientMask = 0xFF38FC00,
3667   FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed
3668 };
3669 
3670 enum SVEFPTrigSelectCoefficientOp {
3671   SVEFPTrigSelectCoefficientFixed = 0x0420B000,
3672   SVEFPTrigSelectCoefficientFMask = 0xFF20F800,
3673   SVEFPTrigSelectCoefficientMask = 0xFF20FC00,
3674   FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed
3675 };
3676 
3677 enum SVEFPUnaryOpOp {
3678   SVEFPUnaryOpFixed = 0x650CA000,
3679   SVEFPUnaryOpFMask = 0xFF3CE000,
3680   SVEFPUnaryOpMask = 0xFF3FE000,
3681   FRECPX_z_p_z = SVEFPUnaryOpFixed,
3682   FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000
3683 };
3684 
3685 enum SVEFPUnaryOpUnpredicatedOp {
3686   SVEFPUnaryOpUnpredicatedFixed = 0x65083000,
3687   SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000,
3688   SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00,
3689   FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000,
3690   FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000
3691 };
3692 
3693 enum SVEIncDecByPredicateCountOp {
3694   SVEIncDecByPredicateCountFixed = 0x25288000,
3695   SVEIncDecByPredicateCountFMask = 0xFF38F000,
3696   SVEIncDecByPredicateCountMask = 0xFF3FFE00,
3697   SQINCP_z_p_z = SVEIncDecByPredicateCountFixed,
3698   SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800,
3699   SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00,
3700   UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000,
3701   UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800,
3702   UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00,
3703   SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000,
3704   SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800,
3705   SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00,
3706   UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000,
3707   UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800,
3708   UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00,
3709   INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000,
3710   INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800,
3711   DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000,
3712   DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800
3713 };
3714 
3715 enum SVEIncDecRegisterByElementCountOp {
3716   SVEIncDecRegisterByElementCountFixed = 0x0430E000,
3717   SVEIncDecRegisterByElementCountFMask = 0xFF30F800,
3718   SVEIncDecRegisterByElementCountMask = 0xFFF0FC00,
3719   INCB_r_rs = SVEIncDecRegisterByElementCountFixed,
3720   DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400,
3721   INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000,
3722   DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400,
3723   INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000,
3724   DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400,
3725   INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000,
3726   DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400
3727 };
3728 
3729 enum SVEIncDecVectorByElementCountOp {
3730   SVEIncDecVectorByElementCountFixed = 0x0430C000,
3731   SVEIncDecVectorByElementCountFMask = 0xFF30F800,
3732   SVEIncDecVectorByElementCountMask = 0xFFF0FC00,
3733   INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000,
3734   DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400,
3735   INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000,
3736   DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400,
3737   INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000,
3738   DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400
3739 };
3740 
3741 enum SVEIndexGenerationOp {
3742   SVEIndexGenerationFixed = 0x04204000,
3743   SVEIndexGenerationFMask = 0xFF20F000,
3744   SVEIndexGenerationMask = 0xFF20FC00,
3745   INDEX_z_ii = SVEIndexGenerationFixed,
3746   INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400,
3747   INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800,
3748   INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00
3749 };
3750 
3751 enum SVEInsertGeneralRegisterOp {
3752   SVEInsertGeneralRegisterFixed = 0x05243800,
3753   SVEInsertGeneralRegisterFMask = 0xFF3FFC00,
3754   SVEInsertGeneralRegisterMask = 0xFF3FFC00,
3755   INSR_z_r = SVEInsertGeneralRegisterFixed
3756 };
3757 
3758 enum SVEInsertSIMDFPScalarRegisterOp {
3759   SVEInsertSIMDFPScalarRegisterFixed = 0x05343800,
3760   SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00,
3761   SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00,
3762   INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed
3763 };
3764 
3765 enum SVEIntAddSubtractImm_UnpredicatedOp {
3766   SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000,
3767   SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000,
3768   SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000,
3769   ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed,
3770   SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000,
3771   SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000,
3772   SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000,
3773   UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000,
3774   SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000,
3775   UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000
3776 };
3777 
3778 enum SVEIntAddSubtractVectors_PredicatedOp {
3779   SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000,
3780   SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000,
3781   SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000,
3782   ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed,
3783   SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000,
3784   SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000
3785 };
3786 
3787 enum SVEIntArithmeticUnpredicatedOp {
3788   SVEIntArithmeticUnpredicatedFixed = 0x04200000,
3789   SVEIntArithmeticUnpredicatedFMask = 0xFF20E000,
3790   SVEIntArithmeticUnpredicatedMask = 0xFF20FC00,
3791   ADD_z_zz = SVEIntArithmeticUnpredicatedFixed,
3792   SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400,
3793   SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000,
3794   UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400,
3795   SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800,
3796   UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00
3797 };
3798 
3799 enum SVEIntCompareScalarCountAndLimitOp {
3800   SVEIntCompareScalarCountAndLimitFixed = 0x25200000,
3801   SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000,
3802   SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10,
3803   WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400,
3804   WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410,
3805   WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00,
3806   WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10
3807 };
3808 
3809 enum SVEIntCompareSignedImmOp {
3810   SVEIntCompareSignedImmFixed = 0x25000000,
3811   SVEIntCompareSignedImmFMask = 0xFF204000,
3812   SVEIntCompareSignedImmMask = 0xFF20E010,
3813   CMPGE_p_p_zi = SVEIntCompareSignedImmFixed,
3814   CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010,
3815   CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000,
3816   CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010,
3817   CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000,
3818   CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010
3819 };
3820 
3821 enum SVEIntCompareUnsignedImmOp {
3822   SVEIntCompareUnsignedImmFixed = 0x24200000,
3823   SVEIntCompareUnsignedImmFMask = 0xFF200000,
3824   SVEIntCompareUnsignedImmMask = 0xFF202010,
3825   CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed,
3826   CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010,
3827   CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000,
3828   CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010
3829 };
3830 
3831 enum SVEIntCompareVectorsOp {
3832   SVEIntCompareVectorsFixed = 0x24000000,
3833   SVEIntCompareVectorsFMask = 0xFF200000,
3834   SVEIntCompareVectorsMask = 0xFF20E010,
3835   CMPHS_p_p_zz = SVEIntCompareVectorsFixed,
3836   CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010,
3837   CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000,
3838   CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010,
3839   CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000,
3840   CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010,
3841   CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000,
3842   CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010,
3843   CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000,
3844   CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010,
3845   CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000,
3846   CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010,
3847   CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000,
3848   CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010,
3849   CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000,
3850   CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010
3851 };
3852 
3853 enum SVEIntConvertToFPOp {
3854   SVEIntConvertToFPFixed = 0x6510A000,
3855   SVEIntConvertToFPFMask = 0xFF38E000,
3856   SVEIntConvertToFPMask = 0xFFFFE000,
3857   SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000,
3858   UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000,
3859   SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000,
3860   UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000,
3861   SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000,
3862   UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000,
3863   SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000,
3864   UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000,
3865   SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000,
3866   UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000,
3867   SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000,
3868   UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000,
3869   SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000,
3870   UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000
3871 };
3872 
3873 enum SVEIntDivideVectors_PredicatedOp {
3874   SVEIntDivideVectors_PredicatedFixed = 0x04140000,
3875   SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000,
3876   SVEIntDivideVectors_PredicatedMask = 0xFF3FE000,
3877   SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed,
3878   UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000,
3879   SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000,
3880   UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000
3881 };
3882 
3883 enum SVEIntMinMaxDifference_PredicatedOp {
3884   SVEIntMinMaxDifference_PredicatedFixed = 0x04080000,
3885   SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000,
3886   SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000,
3887   SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed,
3888   UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000,
3889   SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000,
3890   UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000,
3891   SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000,
3892   UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000
3893 };
3894 
3895 enum SVEIntMinMaxImm_UnpredicatedOp {
3896   SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000,
3897   SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000,
3898   SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000,
3899   SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed,
3900   UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000,
3901   SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000,
3902   UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000
3903 };
3904 
3905 enum SVEIntMulAddPredicatedOp {
3906   SVEIntMulAddPredicatedFixed = 0x04004000,
3907   SVEIntMulAddPredicatedFMask = 0xFF204000,
3908   SVEIntMulAddPredicatedMask = 0xFF20E000,
3909   MLA_z_p_zzz = SVEIntMulAddPredicatedFixed,
3910   MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000,
3911   MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000,
3912   MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000
3913 };
3914 
3915 enum SVEIntMulAddUnpredicatedOp {
3916   SVEIntMulAddUnpredicatedFixed = 0x44000000,
3917   SVEIntMulAddUnpredicatedFMask = 0xFF208000,
3918   SVEIntMulAddUnpredicatedMask = 0xFF20FC00,
3919   SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed,
3920   UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400
3921 };
3922 
3923 enum SVEIntMulImm_UnpredicatedOp {
3924   SVEIntMulImm_UnpredicatedFixed = 0x2530C000,
3925   SVEIntMulImm_UnpredicatedFMask = 0xFF38C000,
3926   SVEIntMulImm_UnpredicatedMask = 0xFF3FE000,
3927   MUL_z_zi = SVEIntMulImm_UnpredicatedFixed
3928 };
3929 
3930 enum SVEIntMulVectors_PredicatedOp {
3931   SVEIntMulVectors_PredicatedFixed = 0x04100000,
3932   SVEIntMulVectors_PredicatedFMask = 0xFF3CE000,
3933   SVEIntMulVectors_PredicatedMask = 0xFF3FE000,
3934   MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed,
3935   SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000,
3936   UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000
3937 };
3938 
3939 enum SVEMovprfxOp {
3940   SVEMovprfxFixed = 0x04002000,
3941   SVEMovprfxFMask = 0xFF20E000,
3942   SVEMovprfxMask = 0xFF3EE000,
3943   MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000
3944 };
3945 
3946 enum SVEIntReductionOp {
3947   SVEIntReductionFixed = 0x04002000,
3948   SVEIntReductionFMask = 0xFF20E000,
3949   SVEIntReductionMask = 0xFF3FE000,
3950   SADDV_r_p_z = SVEIntReductionFixed,
3951   UADDV_r_p_z = SVEIntReductionFixed | 0x00010000,
3952   SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000,
3953   UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000,
3954   SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000,
3955   UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000
3956 };
3957 
3958 enum SVEIntReductionLogicalOp {
3959   SVEIntReductionLogicalFixed = 0x04182000,
3960   SVEIntReductionLogicalFMask = 0xFF38E000,
3961   SVEIntReductionLogicalMask = 0xFF3FE000,
3962   ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000,
3963   EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000,
3964   ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000
3965 };
3966 
3967 enum SVEIntUnaryArithmeticPredicatedOp {
3968   SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000,
3969   SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000,
3970   SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000,
3971   SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000,
3972   UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000,
3973   SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000,
3974   UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000,
3975   SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000,
3976   UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000,
3977   ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000,
3978   NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000,
3979   CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000,
3980   CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000,
3981   CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000,
3982   CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000,
3983   FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000,
3984   FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000,
3985   NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000
3986 };
3987 
3988 enum SVELoadAndBroadcastElementOp {
3989   SVELoadAndBroadcastElementFixed = 0x84408000,
3990   SVELoadAndBroadcastElementFMask = 0xFE408000,
3991   SVELoadAndBroadcastElementMask = 0xFFC0E000,
3992   LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed,
3993   LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000,
3994   LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000,
3995   LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000,
3996   LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000,
3997   LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000,
3998   LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000,
3999   LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000,
4000   LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000,
4001   LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000,
4002   LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000,
4003   LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000,
4004   LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000,
4005   LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000,
4006   LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000,
4007   LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000
4008 };
4009 
4010 enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {
4011   SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000,
4012   SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000,
4013   SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000,
4014   LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed,
4015   LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000,
4016   LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000,
4017   LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000
4018 };
4019 
4020 enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {
4021   SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000,
4022   SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000,
4023   SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000,
4024   LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed,
4025   LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000,
4026   LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000,
4027   LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000
4028 };
4029 
4030 enum SVELoadMultipleStructures_ScalarPlusImmOp {
4031   SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000,
4032   SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
4033   SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
4034   LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000,
4035   LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000,
4036   LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000,
4037   LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
4038   LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
4039   LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
4040   LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000,
4041   LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000,
4042   LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000,
4043   LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
4044   LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
4045   LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000
4046 };
4047 
4048 enum SVELoadMultipleStructures_ScalarPlusScalarOp {
4049   SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000,
4050   SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
4051   SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
4052   LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
4053   LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
4054   LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
4055   LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
4056   LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
4057   LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
4058   LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
4059   LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
4060   LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
4061   LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
4062   LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
4063   LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
4064 };
4065 
4066 enum SVELoadPredicateRegisterOp {
4067   SVELoadPredicateRegisterFixed = 0x85800000,
4068   SVELoadPredicateRegisterFMask = 0xFFC0E010,
4069   SVELoadPredicateRegisterMask = 0xFFC0E010,
4070   LDR_p_bi = SVELoadPredicateRegisterFixed
4071 };
4072 
4073 enum SVELoadVectorRegisterOp {
4074   SVELoadVectorRegisterFixed = 0x85804000,
4075   SVELoadVectorRegisterFMask = 0xFFC0E000,
4076   SVELoadVectorRegisterMask = 0xFFC0E000,
4077   LDR_z_bi = SVELoadVectorRegisterFixed
4078 };
4079 
4080 enum SVEMulIndexOp {
4081   SVEMulIndexFixed = 0x44200000,
4082   SVEMulIndexFMask = 0xFF200000,
4083   SVEMulIndexMask = 0xFFE0FC00,
4084   SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000,
4085   UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400,
4086   SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000,
4087   UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400
4088 };
4089 
4090 enum SVEPartitionBreakConditionOp {
4091   SVEPartitionBreakConditionFixed = 0x25104000,
4092   SVEPartitionBreakConditionFMask = 0xFF3FC200,
4093   SVEPartitionBreakConditionMask = 0xFFFFC200,
4094   BRKA_p_p_p = SVEPartitionBreakConditionFixed,
4095   BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000,
4096   BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000,
4097   BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000
4098 };
4099 
4100 enum SVEPermutePredicateElementsOp {
4101   SVEPermutePredicateElementsFixed = 0x05204000,
4102   SVEPermutePredicateElementsFMask = 0xFF30E210,
4103   SVEPermutePredicateElementsMask = 0xFF30FE10,
4104   ZIP1_p_pp = SVEPermutePredicateElementsFixed,
4105   ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400,
4106   UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800,
4107   UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00,
4108   TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000,
4109   TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400
4110 };
4111 
4112 enum SVEPermuteVectorExtractOp {
4113   SVEPermuteVectorExtractFixed = 0x05200000,
4114   SVEPermuteVectorExtractFMask = 0xFF20E000,
4115   SVEPermuteVectorExtractMask = 0xFFE0E000,
4116   EXT_z_zi_des = SVEPermuteVectorExtractFixed
4117 };
4118 
4119 enum SVEPermuteVectorInterleavingOp {
4120   SVEPermuteVectorInterleavingFixed = 0x05206000,
4121   SVEPermuteVectorInterleavingFMask = 0xFF20E000,
4122   SVEPermuteVectorInterleavingMask = 0xFF20FC00,
4123   ZIP1_z_zz = SVEPermuteVectorInterleavingFixed,
4124   ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400,
4125   UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800,
4126   UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00,
4127   TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000,
4128   TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400
4129 };
4130 
4131 enum SVEPredicateCountOp {
4132   SVEPredicateCountFixed = 0x25208000,
4133   SVEPredicateCountFMask = 0xFF38C000,
4134   SVEPredicateCountMask = 0xFF3FC200,
4135   CNTP_r_p_p = SVEPredicateCountFixed
4136 };
4137 
4138 enum SVEPredicateFirstActiveOp {
4139   SVEPredicateFirstActiveFixed = 0x2518C000,
4140   SVEPredicateFirstActiveFMask = 0xFF3FFE10,
4141   SVEPredicateFirstActiveMask = 0xFFFFFE10,
4142   PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000
4143 };
4144 
4145 enum SVEPredicateInitializeOp {
4146   SVEPredicateInitializeFixed = 0x2518E000,
4147   SVEPredicateInitializeFMask = 0xFF3EFC10,
4148   SVEPredicateInitializeMask = 0xFF3FFC10,
4149   SVEPredicateInitializeSetFlagsBit = 0x00010000,
4150   PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000,
4151   PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit
4152 };
4153 
4154 enum SVEPredicateLogicalOp {
4155   SVEPredicateLogicalFixed = 0x25004000,
4156   SVEPredicateLogicalFMask = 0xFF30C000,
4157   SVEPredicateLogicalMask = 0xFFF0C210,
4158   SVEPredicateLogicalSetFlagsBit = 0x00400000,
4159   AND_p_p_pp_z = SVEPredicateLogicalFixed,
4160   ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4161   BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010,
4162   BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4163   EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200,
4164   EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4165   ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000,
4166   ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4167   ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010,
4168   ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4169   NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210,
4170   NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4171   NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200,
4172   NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4173   SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210
4174 };
4175 
4176 enum SVEPredicateNextActiveOp {
4177   SVEPredicateNextActiveFixed = 0x2519C400,
4178   SVEPredicateNextActiveFMask = 0xFF3FFE10,
4179   SVEPredicateNextActiveMask = 0xFF3FFE10,
4180   PNEXT_p_p_p = SVEPredicateNextActiveFixed
4181 };
4182 
4183 enum SVEPredicateReadFromFFR_PredicatedOp {
4184   SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000,
4185   SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10,
4186   SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10,
4187   RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed,
4188   RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000
4189 };
4190 
4191 enum SVEPredicateReadFromFFR_UnpredicatedOp {
4192   SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000,
4193   SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0,
4194   SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0,
4195   RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed
4196 };
4197 
4198 enum SVEPredicateTestOp {
4199   SVEPredicateTestFixed = 0x2510C000,
4200   SVEPredicateTestFMask = 0xFF3FC210,
4201   SVEPredicateTestMask = 0xFFFFC21F,
4202   PTEST_p_p = SVEPredicateTestFixed | 0x00400000
4203 };
4204 
4205 enum SVEPredicateZeroOp {
4206   SVEPredicateZeroFixed = 0x2518E400,
4207   SVEPredicateZeroFMask = 0xFF3FFFF0,
4208   SVEPredicateZeroMask = 0xFFFFFFF0,
4209   PFALSE_p = SVEPredicateZeroFixed
4210 };
4211 
4212 enum SVEPropagateBreakOp {
4213   SVEPropagateBreakFixed = 0x2500C000,
4214   SVEPropagateBreakFMask = 0xFF30C000,
4215   SVEPropagateBreakMask = 0xFFF0C210,
4216   BRKPA_p_p_pp = SVEPropagateBreakFixed,
4217   BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010,
4218   BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000,
4219   BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010
4220 };
4221 
4222 enum SVEPropagateBreakToNextPartitionOp {
4223   SVEPropagateBreakToNextPartitionFixed = 0x25184000,
4224   SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210,
4225   SVEPropagateBreakToNextPartitionMask = 0xFFFFC210,
4226   BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed,
4227   BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000
4228 };
4229 
4230 enum SVEReversePredicateElementsOp {
4231   SVEReversePredicateElementsFixed = 0x05344000,
4232   SVEReversePredicateElementsFMask = 0xFF3FFE10,
4233   SVEReversePredicateElementsMask = 0xFF3FFE10,
4234   REV_p_p = SVEReversePredicateElementsFixed
4235 };
4236 
4237 enum SVEReverseVectorElementsOp {
4238   SVEReverseVectorElementsFixed = 0x05383800,
4239   SVEReverseVectorElementsFMask = 0xFF3FFC00,
4240   SVEReverseVectorElementsMask = 0xFF3FFC00,
4241   REV_z_z = SVEReverseVectorElementsFixed
4242 };
4243 
4244 enum SVEReverseWithinElementsOp {
4245   SVEReverseWithinElementsFixed = 0x05248000,
4246   SVEReverseWithinElementsFMask = 0xFF3CE000,
4247   SVEReverseWithinElementsMask = 0xFF3FE000,
4248   REVB_z_z = SVEReverseWithinElementsFixed,
4249   REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000,
4250   REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000,
4251   RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000
4252 };
4253 
4254 enum SVESaturatingIncDecRegisterByElementCountOp {
4255   SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000,
4256   SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000,
4257   SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00,
4258   SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed,
4259   UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400,
4260   SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800,
4261   UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00,
4262   SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000,
4263   UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400,
4264   SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800,
4265   UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00,
4266   SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000,
4267   UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400,
4268   SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800,
4269   UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00,
4270   SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000,
4271   UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400,
4272   SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800,
4273   UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00,
4274   SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000,
4275   UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400,
4276   SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800,
4277   UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00,
4278   SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000,
4279   UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400,
4280   SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800,
4281   UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00,
4282   SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000,
4283   UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400,
4284   SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800,
4285   UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00,
4286   SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000,
4287   UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400,
4288   SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800,
4289   UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00
4290 };
4291 
4292 enum SVESaturatingIncDecVectorByElementCountOp {
4293   SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000,
4294   SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000,
4295   SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00,
4296   SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000,
4297   UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400,
4298   SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800,
4299   UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00,
4300   SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000,
4301   UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400,
4302   SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800,
4303   UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00,
4304   SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000,
4305   UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400,
4306   SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800,
4307   UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00
4308 };
4309 
4310 enum SVEStackFrameAdjustmentOp {
4311   SVEStackFrameAdjustmentFixed = 0x04205000,
4312   SVEStackFrameAdjustmentFMask = 0xFFA0F800,
4313   SVEStackFrameAdjustmentMask = 0xFFE0F800,
4314   ADDVL_r_ri = SVEStackFrameAdjustmentFixed,
4315   ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000
4316 };
4317 
4318 enum SVEStackFrameSizeOp {
4319   SVEStackFrameSizeFixed = 0x04BF5000,
4320   SVEStackFrameSizeFMask = 0xFFFFF800,
4321   SVEStackFrameSizeMask = 0xFFFFF800,
4322   RDVL_r_i = SVEStackFrameSizeFixed
4323 };
4324 
4325 enum SVEStoreMultipleStructures_ScalarPlusImmOp {
4326   SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000,
4327   SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
4328   SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
4329   ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000,
4330   ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000,
4331   ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000,
4332   ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
4333   ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
4334   ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
4335   ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000,
4336   ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000,
4337   ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000,
4338   ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
4339   ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
4340   ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000
4341 };
4342 
4343 enum SVEStoreMultipleStructures_ScalarPlusScalarOp {
4344   SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000,
4345   SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
4346   SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
4347   ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
4348   ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
4349   ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
4350   ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
4351   ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
4352   ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
4353   ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
4354   ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
4355   ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
4356   ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
4357   ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
4358   ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
4359 };
4360 
4361 enum SVEStorePredicateRegisterOp {
4362   SVEStorePredicateRegisterFixed = 0xE5800000,
4363   SVEStorePredicateRegisterFMask = 0xFFC0E010,
4364   SVEStorePredicateRegisterMask = 0xFFC0E010,
4365   STR_p_bi = SVEStorePredicateRegisterFixed
4366 };
4367 
4368 enum SVEStoreVectorRegisterOp {
4369   SVEStoreVectorRegisterFixed = 0xE5804000,
4370   SVEStoreVectorRegisterFMask = 0xFFC0E000,
4371   SVEStoreVectorRegisterMask = 0xFFC0E000,
4372   STR_z_bi = SVEStoreVectorRegisterFixed
4373 };
4374 
4375 enum SVETableLookupOp {
4376   SVETableLookupFixed = 0x05203000,
4377   SVETableLookupFMask = 0xFF20FC00,
4378   SVETableLookupMask = 0xFF20FC00,
4379   TBL_z_zz_1 = SVETableLookupFixed
4380 };
4381 
4382 enum SVEUnpackPredicateElementsOp {
4383   SVEUnpackPredicateElementsFixed = 0x05304000,
4384   SVEUnpackPredicateElementsFMask = 0xFFFEFE10,
4385   SVEUnpackPredicateElementsMask = 0xFFFFFE10,
4386   PUNPKLO_p_p = SVEUnpackPredicateElementsFixed,
4387   PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000
4388 };
4389 
4390 enum SVEUnpackVectorElementsOp {
4391   SVEUnpackVectorElementsFixed = 0x05303800,
4392   SVEUnpackVectorElementsFMask = 0xFF3CFC00,
4393   SVEUnpackVectorElementsMask = 0xFF3FFC00,
4394   SUNPKLO_z_z = SVEUnpackVectorElementsFixed,
4395   SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000,
4396   UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000,
4397   UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000
4398 };
4399 
4400 enum SVEVectorSelectOp {
4401   SVEVectorSelectFixed = 0x0520C000,
4402   SVEVectorSelectFMask = 0xFF20C000,
4403   SVEVectorSelectMask = 0xFF20C000,
4404   SEL_z_p_zz = SVEVectorSelectFixed
4405 };
4406 
4407 enum SVEVectorSplice_DestructiveOp {
4408   SVEVectorSplice_DestructiveFixed = 0x052C8000,
4409   SVEVectorSplice_DestructiveFMask = 0xFF3FE000,
4410   SVEVectorSplice_DestructiveMask = 0xFF3FE000,
4411   SPLICE_z_p_zz_des = SVEVectorSplice_DestructiveFixed
4412 };
4413 
4414 enum ReservedOp {
4415   ReservedFixed = 0x00000000,
4416   ReservedFMask = 0x1E000000,
4417   ReservedMask = 0xFFFF0000,
4418   UDF = ReservedFixed | 0x00000000
4419 };
4420 
4421 // Unimplemented and unallocated instructions. These are defined to make fixed
4422 // bit assertion easier.
4423 enum UnimplementedOp {
4424   UnimplementedFixed = 0x00000000,
4425   UnimplementedFMask = 0x00000000
4426 };
4427 
4428 enum UnallocatedOp {
4429   UnallocatedFixed = 0x00000000,
4430   UnallocatedFMask = 0x00000000
4431 };
4432 
4433 // Re-enable `clang-format` after the `enum`s.
4434 // clang-format on
4435 
4436 }  // namespace aarch64
4437 }  // namespace vixl
4438 
4439 #endif  // VIXL_AARCH64_CONSTANTS_AARCH64_H_
4440