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1525 "map": {"at": 33832, "to": "mm"}, 1526 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO", 1527 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_LO" 1528 }, 1529 { 1530 "chips": ["gfx6"], 1531 "map": {"at": 33836, "to": "mm"}, 1532 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI", 1533 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT0_HI" 1534 }, 1535 { 1536 "chips": ["gfx6"], 1537 "map": {"at": 33840, "to": "mm"}, 1538 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO", 1539 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_LO" 1540 }, 1541 { 1542 "chips": ["gfx6"], 1543 "map": {"at": 33844, "to": "mm"}, 1544 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI", 1545 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT1_HI" 1546 }, 1547 { 1548 "chips": ["gfx6"], 1549 "map": {"at": 33848, "to": "mm"}, 1550 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO", 1551 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_LO" 1552 }, 1553 { 1554 "chips": ["gfx6"], 1555 "map": {"at": 33852, "to": "mm"}, 1556 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI", 1557 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT1_HI" 1558 }, 1559 { 1560 "chips": ["gfx6"], 1561 "map": {"at": 33856, "to": "mm"}, 1562 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO", 1563 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_LO" 1564 }, 1565 { 1566 "chips": ["gfx6"], 1567 "map": {"at": 33860, "to": "mm"}, 1568 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI", 1569 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT2_HI" 1570 }, 1571 { 1572 "chips": ["gfx6"], 1573 "map": {"at": 33864, "to": "mm"}, 1574 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO", 1575 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_LO" 1576 }, 1577 { 1578 "chips": ["gfx6"], 1579 "map": {"at": 33868, "to": "mm"}, 1580 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI", 1581 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT2_HI" 1582 }, 1583 { 1584 "chips": ["gfx6"], 1585 "map": {"at": 33872, "to": "mm"}, 1586 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO", 1587 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_LO" 1588 }, 1589 { 1590 "chips": ["gfx6"], 1591 "map": {"at": 33876, "to": "mm"}, 1592 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI", 1593 "type_ref": "CP_NUM_PRIM_WRITTEN_COUNT3_HI" 1594 }, 1595 { 1596 "chips": ["gfx6"], 1597 "map": {"at": 33880, "to": "mm"}, 1598 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO", 1599 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_LO" 1600 }, 1601 { 1602 "chips": ["gfx6"], 1603 "map": {"at": 33884, "to": "mm"}, 1604 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI", 1605 "type_ref": "CP_NUM_PRIM_NEEDED_COUNT3_HI" 1606 }, 1607 { 1608 "chips": ["gfx6"], 1609 "map": {"at": 33888, "to": "mm"}, 1610 "name": "CP_PIPE_STATS_ADDR_LO", 1611 "type_ref": "CP_PIPE_STATS_ADDR_LO" 1612 }, 1613 { 1614 "chips": ["gfx6"], 1615 "map": {"at": 33892, "to": "mm"}, 1616 "name": "CP_PIPE_STATS_ADDR_HI", 1617 "type_ref": "CP_PIPE_STATS_ADDR_HI" 1618 }, 1619 { 1620 "chips": ["gfx6"], 1621 "map": {"at": 33896, "to": "mm"}, 1622 "name": "CP_VGT_IAVERT_COUNT_LO", 1623 "type_ref": "CP_VGT_IAVERT_COUNT_LO" 1624 }, 1625 { 1626 "chips": ["gfx6"], 1627 "map": {"at": 33900, "to": "mm"}, 1628 "name": "CP_VGT_IAVERT_COUNT_HI", 1629 "type_ref": "CP_VGT_IAVERT_COUNT_HI" 1630 }, 1631 { 1632 "chips": ["gfx6"], 1633 "map": {"at": 33904, "to": "mm"}, 1634 "name": "CP_VGT_IAPRIM_COUNT_LO", 1635 "type_ref": "CP_VGT_IAPRIM_COUNT_LO" 1636 }, 1637 { 1638 "chips": ["gfx6"], 1639 "map": {"at": 33908, "to": "mm"}, 1640 "name": "CP_VGT_IAPRIM_COUNT_HI", 1641 "type_ref": "CP_VGT_IAPRIM_COUNT_HI" 1642 }, 1643 { 1644 "chips": ["gfx6"], 1645 "map": {"at": 33912, "to": "mm"}, 1646 "name": "CP_VGT_GSPRIM_COUNT_LO", 1647 "type_ref": "CP_VGT_GSPRIM_COUNT_LO" 1648 }, 1649 { 1650 "chips": ["gfx6"], 1651 "map": {"at": 33916, "to": "mm"}, 1652 "name": "CP_VGT_GSPRIM_COUNT_HI", 1653 "type_ref": "CP_VGT_GSPRIM_COUNT_HI" 1654 }, 1655 { 1656 "chips": ["gfx6"], 1657 "map": {"at": 33920, "to": "mm"}, 1658 "name": "CP_VGT_VSINVOC_COUNT_LO", 1659 "type_ref": "CP_VGT_VSINVOC_COUNT_LO" 1660 }, 1661 { 1662 "chips": ["gfx6"], 1663 "map": {"at": 33924, "to": "mm"}, 1664 "name": "CP_VGT_VSINVOC_COUNT_HI", 1665 "type_ref": "CP_VGT_VSINVOC_COUNT_HI" 1666 }, 1667 { 1668 "chips": ["gfx6"], 1669 "map": {"at": 33928, "to": "mm"}, 1670 "name": "CP_VGT_GSINVOC_COUNT_LO", 1671 "type_ref": "CP_VGT_GSINVOC_COUNT_LO" 1672 }, 1673 { 1674 "chips": ["gfx6"], 1675 "map": {"at": 33932, "to": "mm"}, 1676 "name": "CP_VGT_GSINVOC_COUNT_HI", 1677 "type_ref": "CP_VGT_GSINVOC_COUNT_HI" 1678 }, 1679 { 1680 "chips": ["gfx6"], 1681 "map": {"at": 33936, "to": "mm"}, 1682 "name": "CP_VGT_HSINVOC_COUNT_LO", 1683 "type_ref": "CP_VGT_HSINVOC_COUNT_LO" 1684 }, 1685 { 1686 "chips": ["gfx6"], 1687 "map": {"at": 33940, "to": "mm"}, 1688 "name": "CP_VGT_HSINVOC_COUNT_HI", 1689 "type_ref": "CP_VGT_HSINVOC_COUNT_HI" 1690 }, 1691 { 1692 "chips": ["gfx6"], 1693 "map": {"at": 33944, "to": "mm"}, 1694 "name": "CP_VGT_DSINVOC_COUNT_LO", 1695 "type_ref": "CP_VGT_DSINVOC_COUNT_LO" 1696 }, 1697 { 1698 "chips": ["gfx6"], 1699 "map": {"at": 33948, "to": "mm"}, 1700 "name": "CP_VGT_DSINVOC_COUNT_HI", 1701 "type_ref": "CP_VGT_DSINVOC_COUNT_HI" 1702 }, 1703 { 1704 "chips": ["gfx6"], 1705 "map": {"at": 33952, "to": "mm"}, 1706 "name": "CP_PA_CINVOC_COUNT_LO", 1707 "type_ref": "CP_PA_CINVOC_COUNT_LO" 1708 }, 1709 { 1710 "chips": ["gfx6"], 1711 "map": {"at": 33956, "to": "mm"}, 1712 "name": "CP_PA_CINVOC_COUNT_HI", 1713 "type_ref": "CP_PA_CINVOC_COUNT_HI" 1714 }, 1715 { 1716 "chips": ["gfx6"], 1717 "map": {"at": 33960, "to": "mm"}, 1718 "name": "CP_PA_CPRIM_COUNT_LO", 1719 "type_ref": "CP_PA_CPRIM_COUNT_LO" 1720 }, 1721 { 1722 "chips": ["gfx6"], 1723 "map": {"at": 33964, "to": "mm"}, 1724 "name": "CP_PA_CPRIM_COUNT_HI", 1725 "type_ref": "CP_PA_CPRIM_COUNT_HI" 1726 }, 1727 { 1728 "chips": ["gfx6"], 1729 "map": {"at": 33968, "to": "mm"}, 1730 "name": "CP_SC_PSINVOC_COUNT0_LO", 1731 "type_ref": "CP_SC_PSINVOC_COUNT0_LO" 1732 }, 1733 { 1734 "chips": ["gfx6"], 1735 "map": {"at": 33972, "to": "mm"}, 1736 "name": "CP_SC_PSINVOC_COUNT0_HI", 1737 "type_ref": "CP_SC_PSINVOC_COUNT0_HI" 1738 }, 1739 { 1740 "chips": ["gfx6"], 1741 "map": {"at": 33976, "to": "mm"}, 1742 "name": "CP_SC_PSINVOC_COUNT1_LO", 1743 "type_ref": "CP_SC_PSINVOC_COUNT1_HI" 1744 }, 1745 { 1746 "chips": ["gfx6"], 1747 "map": {"at": 33980, "to": "mm"}, 1748 "name": "CP_SC_PSINVOC_COUNT1_HI", 1749 "type_ref": "CP_SC_PSINVOC_COUNT1_HI" 1750 }, 1751 { 1752 "chips": ["gfx6"], 1753 "map": {"at": 33984, "to": "mm"}, 1754 "name": "CP_VGT_CSINVOC_COUNT_LO", 1755 "type_ref": "CP_VGT_CSINVOC_COUNT_LO" 1756 }, 1757 { 1758 "chips": ["gfx6"], 1759 "map": {"at": 33988, "to": "mm"}, 1760 "name": "CP_VGT_CSINVOC_COUNT_HI", 1761 "type_ref": "CP_VGT_CSINVOC_COUNT_HI" 1762 }, 1763 { 1764 "chips": ["gfx6"], 1765 "map": {"at": 34044, "to": "mm"}, 1766 "name": "CP_STRMOUT_CNTL", 1767 "type_ref": "CP_STRMOUT_CNTL" 1768 }, 1769 { 1770 "chips": ["gfx6"], 1771 "map": {"at": 34048, "to": "mm"}, 1772 "name": "SCRATCH_REG0", 1773 "type_ref": "GRBM_SCRATCH_REG0" 1774 }, 1775 { 1776 "chips": ["gfx6"], 1777 "map": {"at": 34052, "to": "mm"}, 1778 "name": "SCRATCH_REG1", 1779 "type_ref": "GRBM_SCRATCH_REG1" 1780 }, 1781 { 1782 "chips": ["gfx6"], 1783 "map": {"at": 34056, "to": "mm"}, 1784 "name": "SCRATCH_REG2", 1785 "type_ref": "GRBM_SCRATCH_REG2" 1786 }, 1787 { 1788 "chips": ["gfx6"], 1789 "map": {"at": 34060, "to": "mm"}, 1790 "name": "SCRATCH_REG3", 1791 "type_ref": "GRBM_SCRATCH_REG3" 1792 }, 1793 { 1794 "chips": ["gfx6"], 1795 "map": {"at": 34064, "to": "mm"}, 1796 "name": "SCRATCH_REG4", 1797 "type_ref": "GRBM_SCRATCH_REG4" 1798 }, 1799 { 1800 "chips": ["gfx6"], 1801 "map": {"at": 34068, "to": "mm"}, 1802 "name": "SCRATCH_REG5", 1803 "type_ref": "GRBM_SCRATCH_REG5" 1804 }, 1805 { 1806 "chips": ["gfx6"], 1807 "map": {"at": 34072, "to": "mm"}, 1808 "name": "SCRATCH_REG6", 1809 "type_ref": "GRBM_SCRATCH_REG6" 1810 }, 1811 { 1812 "chips": ["gfx6"], 1813 "map": {"at": 34076, "to": "mm"}, 1814 "name": "SCRATCH_REG7", 1815 "type_ref": "GRBM_SCRATCH_REG7" 1816 }, 1817 { 1818 "chips": ["gfx6"], 1819 "map": {"at": 34112, "to": "mm"}, 1820 "name": "SCRATCH_UMSK", 1821 "type_ref": "SCRATCH_UMSK" 1822 }, 1823 { 1824 "chips": ["gfx6"], 1825 "map": {"at": 34116, "to": "mm"}, 1826 "name": "SCRATCH_ADDR", 1827 "type_ref": "SCRATCH_ADDR" 1828 }, 1829 { 1830 "chips": ["gfx6"], 1831 "map": {"at": 34144, "to": "mm"}, 1832 "name": "CP_APPEND_ADDR_LO", 1833 "type_ref": "CP_APPEND_ADDR_LO" 1834 }, 1835 { 1836 "chips": ["gfx6"], 1837 "map": {"at": 34148, "to": "mm"}, 1838 "name": "CP_APPEND_ADDR_HI", 1839 "type_ref": "CP_APPEND_ADDR_HI" 1840 }, 1841 { 1842 "chips": ["gfx6"], 1843 "map": {"at": 34152, "to": "mm"}, 1844 "name": "CP_APPEND_DATA", 1845 "type_ref": "SQ_WAVE_TTMP0" 1846 }, 1847 { 1848 "chips": ["gfx6"], 1849 "map": {"at": 34156, "to": "mm"}, 1850 "name": "CP_APPEND_LAST_CS_FENCE", 1851 "type_ref": "CP_APPEND_LAST_CS_FENCE" 1852 }, 1853 { 1854 "chips": ["gfx6"], 1855 "map": {"at": 34160, "to": "mm"}, 1856 "name": "CP_APPEND_LAST_PS_FENCE", 1857 "type_ref": "CP_APPEND_LAST_CS_FENCE" 1858 }, 1859 { 1860 "chips": ["gfx6"], 1861 "map": {"at": 34164, "to": "mm"}, 1862 "name": "CP_ATOMIC_PREOP_LO", 1863 "type_ref": "CP_ATOMIC_PREOP_LO" 1864 }, 1865 { 1866 "chips": ["gfx6"], 1867 "map": {"at": 34168, "to": "mm"}, 1868 "name": "CP_ATOMIC_PREOP_HI", 1869 "type_ref": "CP_ATOMIC_PREOP_HI" 1870 }, 1871 { 1872 "chips": ["gfx6"], 1873 "map": {"at": 34172, "to": "mm"}, 1874 "name": "CP_GDS_ATOMIC0_PREOP_LO", 1875 "type_ref": "CP_GDS_ATOMIC0_PREOP_LO" 1876 }, 1877 { 1878 "chips": ["gfx6"], 1879 "map": {"at": 34176, "to": "mm"}, 1880 "name": "CP_GDS_ATOMIC0_PREOP_HI", 1881 "type_ref": "CP_GDS_ATOMIC0_PREOP_HI" 1882 }, 1883 { 1884 "chips": ["gfx6"], 1885 "map": {"at": 34180, "to": "mm"}, 1886 "name": "CP_GDS_ATOMIC1_PREOP_LO", 1887 "type_ref": "CP_GDS_ATOMIC1_PREOP_LO" 1888 }, 1889 { 1890 "chips": ["gfx6"], 1891 "map": {"at": 34184, "to": "mm"}, 1892 "name": "CP_GDS_ATOMIC1_PREOP_HI", 1893 "type_ref": "CP_GDS_ATOMIC1_PREOP_HI" 1894 }, 1895 { 1896 "chips": ["gfx6"], 1897 "map": {"at": 34212, "to": "mm"}, 1898 "name": "CP_ME_MC_WADDR_LO", 1899 "type_ref": "CP_ME_MC_WADDR_LO" 1900 }, 1901 { 1902 "chips": ["gfx6"], 1903 "map": {"at": 34216, "to": "mm"}, 1904 "name": "CP_ME_MC_WADDR_HI", 1905 "type_ref": "CP_ME_MC_WADDR_HI" 1906 }, 1907 { 1908 "chips": ["gfx6"], 1909 "map": {"at": 34220, "to": "mm"}, 1910 "name": "CP_ME_MC_WDATA_LO", 1911 "type_ref": "CP_ME_MC_WDATA_LO" 1912 }, 1913 { 1914 "chips": ["gfx6"], 1915 "map": {"at": 34224, "to": "mm"}, 1916 "name": "CP_ME_MC_WDATA_HI", 1917 "type_ref": "CP_ME_MC_WDATA_HI" 1918 }, 1919 { 1920 "chips": ["gfx6"], 1921 "map": {"at": 34228, "to": "mm"}, 1922 "name": "CP_ME_MC_RADDR_LO", 1923 "type_ref": "CP_ME_MC_RADDR_LO" 1924 }, 1925 { 1926 "chips": ["gfx6"], 1927 "map": {"at": 34232, "to": "mm"}, 1928 "name": "CP_ME_MC_RADDR_HI", 1929 "type_ref": "CP_ME_MC_RADDR_HI" 1930 }, 1931 { 1932 "chips": ["gfx6"], 1933 "map": {"at": 34236, "to": "mm"}, 1934 "name": "CP_SEM_WAIT_TIMER", 1935 "type_ref": "CP_SEM_WAIT_TIMER" 1936 }, 1937 { 1938 "chips": ["gfx6"], 1939 "map": {"at": 34240, "to": "mm"}, 1940 "name": "CP_SIG_SEM_ADDR_LO", 1941 "type_ref": "CP_SIG_SEM_ADDR_LO" 1942 }, 1943 { 1944 "chips": ["gfx6"], 1945 "map": {"at": 34244, "to": "mm"}, 1946 "name": "CP_SIG_SEM_ADDR_HI", 1947 "type_ref": "CP_SIG_SEM_ADDR_HI" 1948 }, 1949 { 1950 "chips": ["gfx6"], 1951 "map": {"at": 34256, "to": "mm"}, 1952 "name": "CP_WAIT_REG_MEM_TIMEOUT", 1953 "type_ref": "CP_WAIT_REG_MEM_TIMEOUT" 1954 }, 1955 { 1956 "chips": ["gfx6"], 1957 "map": {"at": 34260, "to": "mm"}, 1958 "name": "CP_WAIT_SEM_ADDR_LO", 1959 "type_ref": "CP_SIG_SEM_ADDR_LO" 1960 }, 1961 { 1962 "chips": ["gfx6"], 1963 "map": {"at": 34264, "to": "mm"}, 1964 "name": "CP_WAIT_SEM_ADDR_HI", 1965 "type_ref": "CP_SIG_SEM_ADDR_HI" 1966 }, 1967 { 1968 "chips": ["gfx6"], 1969 "map": {"at": 34284, "to": "mm"}, 1970 "name": "CP_COHER_START_DELAY", 1971 "type_ref": "CP_COHER_START_DELAY" 1972 }, 1973 { 1974 "chips": ["gfx6"], 1975 "map": {"at": 34288, "to": "mm"}, 1976 "name": "CP_COHER_CNTL", 1977 "type_ref": "CP_COHER_CNTL" 1978 }, 1979 { 1980 "chips": ["gfx6"], 1981 "map": {"at": 34292, "to": "mm"}, 1982 "name": "CP_COHER_SIZE", 1983 "type_ref": "CP_COHER_SIZE" 1984 }, 1985 { 1986 "chips": ["gfx6"], 1987 "map": {"at": 34296, "to": "mm"}, 1988 "name": "CP_COHER_BASE", 1989 "type_ref": "CP_COHER_BASE" 1990 }, 1991 { 1992 "chips": ["gfx6"], 1993 "map": {"at": 34300, "to": "mm"}, 1994 "name": "CP_COHER_STATUS", 1995 "type_ref": "CP_COHER_STATUS" 1996 }, 1997 { 1998 "chips": ["gfx6"], 1999 "map": {"at": 34304, "to": "mm"}, 2000 "name": "CP_DMA_ME_SRC_ADDR", 2001 "type_ref": "CP_DMA_ME_SRC_ADDR" 2002 }, 2003 { 2004 "chips": ["gfx6"], 2005 "map": {"at": 34308, "to": "mm"}, 2006 "name": "CP_DMA_ME_SRC_ADDR_HI", 2007 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 2008 }, 2009 { 2010 "chips": ["gfx6"], 2011 "map": {"at": 34312, "to": "mm"}, 2012 "name": "CP_DMA_ME_DST_ADDR", 2013 "type_ref": "CP_DMA_ME_DST_ADDR" 2014 }, 2015 { 2016 "chips": ["gfx6"], 2017 "map": {"at": 34316, "to": "mm"}, 2018 "name": "CP_DMA_ME_DST_ADDR_HI", 2019 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 2020 }, 2021 { 2022 "chips": ["gfx6"], 2023 "map": {"at": 34320, "to": "mm"}, 2024 "name": "CP_DMA_ME_COMMAND", 2025 "type_ref": "CP_DMA_ME_COMMAND" 2026 }, 2027 { 2028 "chips": ["gfx6"], 2029 "map": {"at": 34324, "to": "mm"}, 2030 "name": "CP_DMA_PFP_SRC_ADDR", 2031 "type_ref": "CP_DMA_ME_SRC_ADDR" 2032 }, 2033 { 2034 "chips": ["gfx6"], 2035 "map": {"at": 34328, "to": "mm"}, 2036 "name": "CP_DMA_PFP_SRC_ADDR_HI", 2037 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 2038 }, 2039 { 2040 "chips": ["gfx6"], 2041 "map": {"at": 34332, "to": "mm"}, 2042 "name": "CP_DMA_PFP_DST_ADDR", 2043 "type_ref": "CP_DMA_ME_DST_ADDR" 2044 }, 2045 { 2046 "chips": ["gfx6"], 2047 "map": {"at": 34336, "to": "mm"}, 2048 "name": "CP_DMA_PFP_DST_ADDR_HI", 2049 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 2050 }, 2051 { 2052 "chips": ["gfx6"], 2053 "map": {"at": 34340, "to": "mm"}, 2054 "name": "CP_DMA_PFP_COMMAND", 2055 "type_ref": "CP_DMA_ME_COMMAND" 2056 }, 2057 { 2058 "chips": ["gfx6"], 2059 "map": {"at": 34344, "to": "mm"}, 2060 "name": "CP_DMA_CNTL", 2061 "type_ref": "CP_DMA_CNTL" 2062 }, 2063 { 2064 "chips": ["gfx6"], 2065 "map": {"at": 34348, "to": "mm"}, 2066 "name": "CP_DMA_READ_TAGS", 2067 "type_ref": "CP_DMA_READ_TAGS" 2068 }, 2069 { 2070 "chips": ["gfx6"], 2071 "map": {"at": 34356, "to": "mm"}, 2072 "name": "CP_PFP_IB_CONTROL", 2073 "type_ref": "CP_PFP_IB_CONTROL" 2074 }, 2075 { 2076 "chips": ["gfx6"], 2077 "map": {"at": 34360, "to": "mm"}, 2078 "name": "CP_PFP_LOAD_CONTROL", 2079 "type_ref": "CP_PFP_LOAD_CONTROL" 2080 }, 2081 { 2082 "chips": ["gfx6"], 2083 "map": {"at": 34364, "to": "mm"}, 2084 "name": "CP_SCRATCH_INDEX", 2085 "type_ref": "CP_SCRATCH_INDEX" 2086 }, 2087 { 2088 "chips": ["gfx6"], 2089 "map": {"at": 34368, "to": "mm"}, 2090 "name": "CP_SCRATCH_DATA", 2091 "type_ref": "CP_SCRATCH_DATA" 2092 }, 2093 { 2094 "chips": ["gfx6"], 2095 "map": {"at": 34372, "to": "mm"}, 2096 "name": "CP_RB_OFFSET", 2097 "type_ref": "CP_RB_OFFSET" 2098 }, 2099 { 2100 "chips": ["gfx6"], 2101 "map": {"at": 34376, "to": "mm"}, 2102 "name": "CP_IB1_OFFSET", 2103 "type_ref": "CP_IB1_OFFSET" 2104 }, 2105 { 2106 "chips": ["gfx6"], 2107 "map": {"at": 34380, "to": "mm"}, 2108 "name": "CP_IB2_OFFSET", 2109 "type_ref": "CP_IB2_OFFSET" 2110 }, 2111 { 2112 "chips": ["gfx6"], 2113 "map": {"at": 34384, "to": "mm"}, 2114 "name": "CP_IB1_PREAMBLE_BEGIN", 2115 "type_ref": "CP_IB1_PREAMBLE_BEGIN" 2116 }, 2117 { 2118 "chips": ["gfx6"], 2119 "map": {"at": 34388, "to": "mm"}, 2120 "name": "CP_IB1_PREAMBLE_END", 2121 "type_ref": "CP_IB1_PREAMBLE_END" 2122 }, 2123 { 2124 "chips": ["gfx6"], 2125 "map": {"at": 34392, "to": "mm"}, 2126 "name": "CP_IB2_PREAMBLE_BEGIN", 2127 "type_ref": "CP_IB2_PREAMBLE_BEGIN" 2128 }, 2129 { 2130 "chips": ["gfx6"], 2131 "map": {"at": 34396, "to": "mm"}, 2132 "name": "CP_IB2_PREAMBLE_END", 2133 "type_ref": "CP_IB2_PREAMBLE_END" 2134 }, 2135 { 2136 "chips": ["gfx6"], 2137 "map": {"at": 34416, "to": "mm"}, 2138 "name": "CP_STALLED_STAT3", 2139 "type_ref": "CP_STALLED_STAT3" 2140 }, 2141 { 2142 "chips": ["gfx6"], 2143 "map": {"at": 34420, "to": "mm"}, 2144 "name": "CP_STALLED_STAT1", 2145 "type_ref": "CP_STALLED_STAT1" 2146 }, 2147 { 2148 "chips": ["gfx6"], 2149 "map": {"at": 34424, "to": "mm"}, 2150 "name": "CP_STALLED_STAT2", 2151 "type_ref": "CP_STALLED_STAT2" 2152 }, 2153 { 2154 "chips": ["gfx6"], 2155 "map": {"at": 34428, "to": "mm"}, 2156 "name": "CP_BUSY_STAT", 2157 "type_ref": "CP_BUSY_STAT" 2158 }, 2159 { 2160 "chips": ["gfx6"], 2161 "map": {"at": 34432, "to": "mm"}, 2162 "name": "CP_STAT", 2163 "type_ref": "CP_STAT" 2164 }, 2165 { 2166 "chips": ["gfx6"], 2167 "map": {"at": 34436, "to": "mm"}, 2168 "name": "CP_ME_HEADER_DUMP", 2169 "type_ref": "CP_ME_HEADER_DUMP" 2170 }, 2171 { 2172 "chips": ["gfx6"], 2173 "map": {"at": 34440, "to": "mm"}, 2174 "name": "CP_PFP_HEADER_DUMP", 2175 "type_ref": "CP_PFP_HEADER_DUMP" 2176 }, 2177 { 2178 "chips": ["gfx6"], 2179 "map": {"at": 34444, "to": "mm"}, 2180 "name": "CP_GRBM_FREE_COUNT", 2181 "type_ref": "CP_GRBM_FREE_COUNT" 2182 }, 2183 { 2184 "chips": ["gfx6"], 2185 "map": {"at": 34448, "to": "mm"}, 2186 "name": "CP_CE_HEADER_DUMP", 2187 "type_ref": "CP_CE_HEADER_DUMP" 2188 }, 2189 { 2190 "chips": ["gfx6"], 2191 "map": {"at": 34460, "to": "mm"}, 2192 "name": "CP_MC_PACK_DELAY_CNT", 2193 "type_ref": "CP_MC_PACK_DELAY_CNT" 2194 }, 2195 { 2196 "chips": ["gfx6"], 2197 "map": {"at": 34512, "to": "mm"}, 2198 "name": "CP_CSF_STAT", 2199 "type_ref": "CP_CSF_STAT" 2200 }, 2201 { 2202 "chips": ["gfx6"], 2203 "map": {"at": 34516, "to": "mm"}, 2204 "name": "CP_CSF_CNTL", 2205 "type_ref": "CP_CSF_CNTL" 2206 }, 2207 { 2208 "chips": ["gfx6"], 2209 "map": {"at": 34520, "to": "mm"}, 2210 "name": "CP_ME_CNTL", 2211 "type_ref": "CP_ME_CNTL" 2212 }, 2213 { 2214 "chips": ["gfx6"], 2215 "map": {"at": 34528, "to": "mm"}, 2216 "name": "CP_CNTX_STAT", 2217 "type_ref": "CP_CNTX_STAT" 2218 }, 2219 { 2220 "chips": ["gfx6"], 2221 "map": {"at": 34532, "to": "mm"}, 2222 "name": "CP_ME_PREEMPTION", 2223 "type_ref": "CP_ME_PREEMPTION" 2224 }, 2225 { 2226 "chips": ["gfx6"], 2227 "map": {"at": 34552, "to": "mm"}, 2228 "name": "CP_RB2_RPTR", 2229 "type_ref": "CP_RB0_RPTR" 2230 }, 2231 { 2232 "chips": ["gfx6"], 2233 "map": {"at": 34556, "to": "mm"}, 2234 "name": "CP_RB1_RPTR", 2235 "type_ref": "CP_RB0_RPTR" 2236 }, 2237 { 2238 "chips": ["gfx6"], 2239 "map": {"at": 34560, "to": "mm"}, 2240 "name": "CP_RB0_RPTR", 2241 "type_ref": "CP_RB0_RPTR" 2242 }, 2243 { 2244 "chips": ["gfx6"], 2245 "map": {"at": 34564, "to": "mm"}, 2246 "name": "CP_RB_WPTR_DELAY", 2247 "type_ref": "CP_RB_WPTR_DELAY" 2248 }, 2249 { 2250 "chips": ["gfx6"], 2251 "map": {"at": 34568, "to": "mm"}, 2252 "name": "CP_RB_WPTR_POLL_CNTL", 2253 "type_ref": "CP_RB_WPTR_POLL_CNTL" 2254 }, 2255 { 2256 "chips": ["gfx6"], 2257 "map": {"at": 34572, "to": "mm"}, 2258 "name": "CP_CE_INIT_BASE_LO", 2259 "type_ref": "CP_CE_INIT_BASE_LO" 2260 }, 2261 { 2262 "chips": ["gfx6"], 2263 "map": {"at": 34576, "to": "mm"}, 2264 "name": "CP_CE_INIT_BASE_HI", 2265 "type_ref": "CP_CE_INIT_BASE_HI" 2266 }, 2267 { 2268 "chips": ["gfx6"], 2269 "map": {"at": 34580, "to": "mm"}, 2270 "name": "CP_CE_INIT_BUFSZ", 2271 "type_ref": "CP_CE_INIT_BUFSZ" 2272 }, 2273 { 2274 "chips": ["gfx6"], 2275 "map": {"at": 34584, "to": "mm"}, 2276 "name": "CP_CE_IB1_BASE_LO", 2277 "type_ref": "CP_CE_IB1_BASE_LO" 2278 }, 2279 { 2280 "chips": ["gfx6"], 2281 "map": {"at": 34588, "to": "mm"}, 2282 "name": "CP_CE_IB1_BASE_HI", 2283 "type_ref": "CP_CE_IB1_BASE_HI" 2284 }, 2285 { 2286 "chips": ["gfx6"], 2287 "map": {"at": 34592, "to": "mm"}, 2288 "name": "CP_CE_IB1_BUFSZ", 2289 "type_ref": "CP_CE_IB1_BUFSZ" 2290 }, 2291 { 2292 "chips": ["gfx6"], 2293 "map": {"at": 34596, "to": "mm"}, 2294 "name": "CP_CE_IB2_BASE_LO", 2295 "type_ref": "CP_CE_IB2_BASE_LO" 2296 }, 2297 { 2298 "chips": ["gfx6"], 2299 "map": {"at": 34600, "to": "mm"}, 2300 "name": "CP_CE_IB2_BASE_HI", 2301 "type_ref": "CP_CE_IB2_BASE_HI" 2302 }, 2303 { 2304 "chips": ["gfx6"], 2305 "map": {"at": 34604, "to": "mm"}, 2306 "name": "CP_CE_IB2_BUFSZ", 2307 "type_ref": "CP_CE_IB2_BUFSZ" 2308 }, 2309 { 2310 "chips": ["gfx6"], 2311 "map": {"at": 34608, "to": "mm"}, 2312 "name": "CP_IB1_BASE_LO", 2313 "type_ref": "CP_CE_IB1_BASE_LO" 2314 }, 2315 { 2316 "chips": ["gfx6"], 2317 "map": {"at": 34612, "to": "mm"}, 2318 "name": "CP_IB1_BASE_HI", 2319 "type_ref": "CP_CE_IB1_BASE_HI" 2320 }, 2321 { 2322 "chips": ["gfx6"], 2323 "map": {"at": 34616, "to": "mm"}, 2324 "name": "CP_IB1_BUFSZ", 2325 "type_ref": "CP_CE_IB1_BUFSZ" 2326 }, 2327 { 2328 "chips": ["gfx6"], 2329 "map": {"at": 34620, "to": "mm"}, 2330 "name": "CP_IB2_BASE_LO", 2331 "type_ref": "CP_CE_IB2_BASE_LO" 2332 }, 2333 { 2334 "chips": ["gfx6"], 2335 "map": {"at": 34624, "to": "mm"}, 2336 "name": "CP_IB2_BASE_HI", 2337 "type_ref": "CP_CE_IB2_BASE_HI" 2338 }, 2339 { 2340 "chips": ["gfx6"], 2341 "map": {"at": 34628, "to": "mm"}, 2342 "name": "CP_IB2_BUFSZ", 2343 "type_ref": "CP_CE_IB2_BUFSZ" 2344 }, 2345 { 2346 "chips": ["gfx6"], 2347 "map": {"at": 34632, "to": "mm"}, 2348 "name": "CP_ST_BASE_LO", 2349 "type_ref": "CP_ST_BASE_LO" 2350 }, 2351 { 2352 "chips": ["gfx6"], 2353 "map": {"at": 34636, "to": "mm"}, 2354 "name": "CP_ST_BASE_HI", 2355 "type_ref": "CP_ST_BASE_HI" 2356 }, 2357 { 2358 "chips": ["gfx6"], 2359 "map": {"at": 34640, "to": "mm"}, 2360 "name": "CP_ST_BUFSZ", 2361 "type_ref": "CP_ST_BUFSZ" 2362 }, 2363 { 2364 "chips": ["gfx6"], 2365 "map": {"at": 34644, "to": "mm"}, 2366 "name": "CP_ROQ1_THRESHOLDS", 2367 "type_ref": "CP_ROQ1_THRESHOLDS" 2368 }, 2369 { 2370 "chips": ["gfx6"], 2371 "map": {"at": 34648, "to": "mm"}, 2372 "name": "CP_ROQ2_THRESHOLDS", 2373 "type_ref": "CP_ROQ2_THRESHOLDS" 2374 }, 2375 { 2376 "chips": ["gfx6"], 2377 "map": {"at": 34652, "to": "mm"}, 2378 "name": "CP_STQ_THRESHOLDS", 2379 "type_ref": "CP_STQ_THRESHOLDS" 2380 }, 2381 { 2382 "chips": ["gfx6"], 2383 "map": {"at": 34656, "to": "mm"}, 2384 "name": "CP_QUEUE_THRESHOLDS", 2385 "type_ref": "CP_QUEUE_THRESHOLDS" 2386 }, 2387 { 2388 "chips": ["gfx6"], 2389 "map": {"at": 34660, "to": "mm"}, 2390 "name": "CP_MEQ_THRESHOLDS", 2391 "type_ref": "CP_MEQ_THRESHOLDS" 2392 }, 2393 { 2394 "chips": ["gfx6"], 2395 "map": {"at": 34664, "to": "mm"}, 2396 "name": "CP_ROQ_AVAIL", 2397 "type_ref": "CP_ROQ_AVAIL" 2398 }, 2399 { 2400 "chips": ["gfx6"], 2401 "map": {"at": 34668, "to": "mm"}, 2402 "name": "CP_STQ_AVAIL", 2403 "type_ref": "CP_STQ_AVAIL" 2404 }, 2405 { 2406 "chips": ["gfx6"], 2407 "map": {"at": 34672, "to": "mm"}, 2408 "name": "CP_ROQ2_AVAIL", 2409 "type_ref": "CP_ROQ2_AVAIL" 2410 }, 2411 { 2412 "chips": ["gfx6"], 2413 "map": {"at": 34676, "to": "mm"}, 2414 "name": "CP_MEQ_AVAIL", 2415 "type_ref": "CP_MEQ_AVAIL" 2416 }, 2417 { 2418 "chips": ["gfx6"], 2419 "map": {"at": 34680, "to": "mm"}, 2420 "name": "CP_CMD_INDEX", 2421 "type_ref": "CP_CMD_INDEX" 2422 }, 2423 { 2424 "chips": ["gfx6"], 2425 "map": {"at": 34684, "to": "mm"}, 2426 "name": "CP_CMD_DATA", 2427 "type_ref": "CP_CMD_DATA" 2428 }, 2429 { 2430 "chips": ["gfx6"], 2431 "map": {"at": 34688, "to": "mm"}, 2432 "name": "CP_ROQ_RB_STAT", 2433 "type_ref": "CP_ROQ_RB_STAT" 2434 }, 2435 { 2436 "chips": ["gfx6"], 2437 "map": {"at": 34692, "to": "mm"}, 2438 "name": "CP_ROQ_IB1_STAT", 2439 "type_ref": "CP_ROQ_IB1_STAT" 2440 }, 2441 { 2442 "chips": ["gfx6"], 2443 "map": {"at": 34696, "to": "mm"}, 2444 "name": "CP_ROQ_IB2_STAT", 2445 "type_ref": "CP_ROQ_IB2_STAT" 2446 }, 2447 { 2448 "chips": ["gfx6"], 2449 "map": {"at": 34700, "to": "mm"}, 2450 "name": "CP_STQ_STAT", 2451 "type_ref": "CP_STQ_STAT" 2452 }, 2453 { 2454 "chips": ["gfx6"], 2455 "map": {"at": 34708, "to": "mm"}, 2456 "name": "CP_MEQ_STAT", 2457 "type_ref": "CP_MEQ_STAT" 2458 }, 2459 { 2460 "chips": ["gfx6"], 2461 "map": {"at": 34712, "to": "mm"}, 2462 "name": "CP_CEQ1_AVAIL", 2463 "type_ref": "CP_CEQ1_AVAIL" 2464 }, 2465 { 2466 "chips": ["gfx6"], 2467 "map": {"at": 34716, "to": "mm"}, 2468 "name": "CP_CEQ2_AVAIL", 2469 "type_ref": "CP_CEQ2_AVAIL" 2470 }, 2471 { 2472 "chips": ["gfx6"], 2473 "map": {"at": 34720, "to": "mm"}, 2474 "name": "CP_CE_ROQ_RB_STAT", 2475 "type_ref": "CP_CE_ROQ_RB_STAT" 2476 }, 2477 { 2478 "chips": ["gfx6"], 2479 "map": {"at": 34724, "to": "mm"}, 2480 "name": "CP_CE_ROQ_IB1_STAT", 2481 "type_ref": "CP_CE_ROQ_IB1_STAT" 2482 }, 2483 { 2484 "chips": ["gfx6"], 2485 "map": {"at": 34728, "to": "mm"}, 2486 "name": "CP_CE_ROQ_IB2_STAT", 2487 "type_ref": "CP_CE_ROQ_IB2_STAT" 2488 }, 2489 { 2490 "chips": ["gfx6"], 2491 "map": {"at": 34780, "to": "mm"}, 2492 "name": "CP_INT_STAT_DEBUG", 2493 "type_ref": "CP_INT_STAT_DEBUG" 2494 }, 2495 { 2496 "chips": ["gfx6"], 2497 "map": {"at": 34812, "to": "mm"}, 2498 "name": "CP_PERFMON_CNTL", 2499 "type_ref": "CP_PERFMON_CNTL" 2500 }, 2501 { 2502 "chips": ["gfx6"], 2503 "map": {"at": 34944, "to": "mm"}, 2504 "name": "IA_PERFCOUNTER0_SELECT", 2505 "type_ref": "IA_PERFCOUNTER0_SELECT" 2506 }, 2507 { 2508 "chips": ["gfx6"], 2509 "map": {"at": 34948, "to": "mm"}, 2510 "name": "IA_PERFCOUNTER1_SELECT", 2511 "type_ref": "IA_PERFCOUNTER1_SELECT" 2512 }, 2513 { 2514 "chips": ["gfx6"], 2515 "map": {"at": 34952, "to": "mm"}, 2516 "name": "IA_PERFCOUNTER2_SELECT", 2517 "type_ref": "IA_PERFCOUNTER1_SELECT" 2518 }, 2519 { 2520 "chips": ["gfx6"], 2521 "map": {"at": 34956, "to": "mm"}, 2522 "name": "IA_PERFCOUNTER3_SELECT", 2523 "type_ref": "IA_PERFCOUNTER1_SELECT" 2524 }, 2525 { 2526 "chips": ["gfx6"], 2527 "map": {"at": 34960, "to": "mm"}, 2528 "name": "IA_PERFCOUNTER0_LO", 2529 "type_ref": "GRBM_PERFCOUNTER0_LO" 2530 }, 2531 { 2532 "chips": ["gfx6"], 2533 "map": {"at": 34964, "to": "mm"}, 2534 "name": "IA_PERFCOUNTER0_HI", 2535 "type_ref": "GRBM_PERFCOUNTER0_HI" 2536 }, 2537 { 2538 "chips": ["gfx6"], 2539 "map": {"at": 34968, "to": "mm"}, 2540 "name": "IA_PERFCOUNTER1_LO", 2541 "type_ref": "GRBM_PERFCOUNTER0_LO" 2542 }, 2543 { 2544 "chips": ["gfx6"], 2545 "map": {"at": 34972, "to": "mm"}, 2546 "name": "IA_PERFCOUNTER1_HI", 2547 "type_ref": "GRBM_PERFCOUNTER0_HI" 2548 }, 2549 { 2550 "chips": ["gfx6"], 2551 "map": {"at": 34976, "to": "mm"}, 2552 "name": "IA_PERFCOUNTER2_LO", 2553 "type_ref": "GRBM_PERFCOUNTER0_LO" 2554 }, 2555 { 2556 "chips": ["gfx6"], 2557 "map": {"at": 34980, "to": "mm"}, 2558 "name": "IA_PERFCOUNTER2_HI", 2559 "type_ref": "GRBM_PERFCOUNTER0_HI" 2560 }, 2561 { 2562 "chips": ["gfx6"], 2563 "map": {"at": 34984, "to": "mm"}, 2564 "name": "IA_PERFCOUNTER3_LO", 2565 "type_ref": "GRBM_PERFCOUNTER0_LO" 2566 }, 2567 { 2568 "chips": ["gfx6"], 2569 "map": {"at": 34988, "to": "mm"}, 2570 "name": "IA_PERFCOUNTER3_HI", 2571 "type_ref": "GRBM_PERFCOUNTER0_HI" 2572 }, 2573 { 2574 "chips": ["gfx6"], 2575 "map": {"at": 34992, "to": "mm"}, 2576 "name": "VGT_VTX_VECT_EJECT_REG", 2577 "type_ref": "VGT_VTX_VECT_EJECT_REG" 2578 }, 2579 { 2580 "chips": ["gfx6"], 2581 "map": {"at": 34996, "to": "mm"}, 2582 "name": "VGT_DMA_DATA_FIFO_DEPTH", 2583 "type_ref": "VGT_DMA_DATA_FIFO_DEPTH" 2584 }, 2585 { 2586 "chips": ["gfx6"], 2587 "map": {"at": 35000, "to": "mm"}, 2588 "name": "VGT_DMA_REQ_FIFO_DEPTH", 2589 "type_ref": "VGT_DMA_REQ_FIFO_DEPTH" 2590 }, 2591 { 2592 "chips": ["gfx6"], 2593 "map": {"at": 35004, "to": "mm"}, 2594 "name": "VGT_DRAW_INIT_FIFO_DEPTH", 2595 "type_ref": "VGT_DRAW_INIT_FIFO_DEPTH" 2596 }, 2597 { 2598 "chips": ["gfx6"], 2599 "map": {"at": 35008, "to": "mm"}, 2600 "name": "VGT_LAST_COPY_STATE", 2601 "type_ref": "VGT_LAST_COPY_STATE" 2602 }, 2603 { 2604 "chips": ["gfx6"], 2605 "map": {"at": 35012, "to": "mm"}, 2606 "name": "VGT_CACHE_INVALIDATION", 2607 "type_ref": "VGT_CACHE_INVALIDATION" 2608 }, 2609 { 2610 "chips": ["gfx6"], 2611 "map": {"at": 35016, "to": "mm"}, 2612 "name": "VGT_ESGS_RING_SIZE", 2613 "type_ref": "VGT_ESGS_RING_SIZE" 2614 }, 2615 { 2616 "chips": ["gfx6"], 2617 "map": {"at": 35020, "to": "mm"}, 2618 "name": "VGT_GSVS_RING_SIZE", 2619 "type_ref": "VGT_ESGS_RING_SIZE" 2620 }, 2621 { 2622 "chips": ["gfx6"], 2623 "map": {"at": 35024, "to": "mm"}, 2624 "name": "VGT_FIFO_DEPTHS", 2625 "type_ref": "VGT_FIFO_DEPTHS" 2626 }, 2627 { 2628 "chips": ["gfx6"], 2629 "map": {"at": 35028, "to": "mm"}, 2630 "name": "VGT_GS_VERTEX_REUSE", 2631 "type_ref": "VGT_GS_VERTEX_REUSE" 2632 }, 2633 { 2634 "chips": ["gfx6"], 2635 "map": {"at": 35032, "to": "mm"}, 2636 "name": "VGT_MC_LAT_CNTL", 2637 "type_ref": "VGT_MC_LAT_CNTL" 2638 }, 2639 { 2640 "chips": ["gfx6"], 2641 "map": {"at": 35036, "to": "mm"}, 2642 "name": "IA_CNTL_STATUS", 2643 "type_ref": "IA_CNTL_STATUS" 2644 }, 2645 { 2646 "chips": ["gfx6"], 2647 "map": {"at": 35040, "to": "mm"}, 2648 "name": "VGT_DEBUG_CNTL", 2649 "type_ref": "VGT_DEBUG_CNTL" 2650 }, 2651 { 2652 "chips": ["gfx6"], 2653 "map": {"at": 35044, "to": "mm"}, 2654 "name": "VGT_DEBUG_DATA", 2655 "type_ref": "SQ_WAVE_TTMP0" 2656 }, 2657 { 2658 "chips": ["gfx6"], 2659 "map": {"at": 35048, "to": "mm"}, 2660 "name": "IA_DEBUG_CNTL", 2661 "type_ref": "IA_DEBUG_CNTL" 2662 }, 2663 { 2664 "chips": ["gfx6"], 2665 "map": {"at": 35052, "to": "mm"}, 2666 "name": "IA_DEBUG_DATA", 2667 "type_ref": "SQ_WAVE_TTMP0" 2668 }, 2669 { 2670 "chips": ["gfx6"], 2671 "map": {"at": 35056, "to": "mm"}, 2672 "name": "VGT_CNTL_STATUS", 2673 "type_ref": "VGT_CNTL_STATUS" 2674 }, 2675 { 2676 "chips": ["gfx6"], 2677 "map": {"at": 35100, "to": "mm"}, 2678 "name": "VGT_PERFCOUNTER_SEID_MASK", 2679 "type_ref": "VGT_PERFCOUNTER_SEID_MASK" 2680 }, 2681 { 2682 "chips": ["gfx6"], 2683 "map": {"at": 35104, "to": "mm"}, 2684 "name": "VGT_PERFCOUNTER0_SELECT", 2685 "type_ref": "IA_PERFCOUNTER0_SELECT" 2686 }, 2687 { 2688 "chips": ["gfx6"], 2689 "map": {"at": 35108, "to": "mm"}, 2690 "name": "VGT_PERFCOUNTER1_SELECT", 2691 "type_ref": "IA_PERFCOUNTER0_SELECT" 2692 }, 2693 { 2694 "chips": ["gfx6"], 2695 "map": {"at": 35112, "to": "mm"}, 2696 "name": "VGT_PERFCOUNTER2_SELECT", 2697 "type_ref": "IA_PERFCOUNTER1_SELECT" 2698 }, 2699 { 2700 "chips": ["gfx6"], 2701 "map": {"at": 35116, "to": "mm"}, 2702 "name": "VGT_PERFCOUNTER3_SELECT", 2703 "type_ref": "IA_PERFCOUNTER1_SELECT" 2704 }, 2705 { 2706 "chips": ["gfx6"], 2707 "map": {"at": 35120, "to": "mm"}, 2708 "name": "VGT_PERFCOUNTER0_LO", 2709 "type_ref": "GRBM_PERFCOUNTER0_LO" 2710 }, 2711 { 2712 "chips": ["gfx6"], 2713 "map": {"at": 35124, "to": "mm"}, 2714 "name": "VGT_PERFCOUNTER0_HI", 2715 "type_ref": "GRBM_PERFCOUNTER0_HI" 2716 }, 2717 { 2718 "chips": ["gfx6"], 2719 "map": {"at": 35128, "to": "mm"}, 2720 "name": "VGT_PERFCOUNTER1_LO", 2721 "type_ref": "GRBM_PERFCOUNTER0_LO" 2722 }, 2723 { 2724 "chips": ["gfx6"], 2725 "map": {"at": 35132, "to": "mm"}, 2726 "name": "VGT_PERFCOUNTER1_HI", 2727 "type_ref": "GRBM_PERFCOUNTER0_HI" 2728 }, 2729 { 2730 "chips": ["gfx6"], 2731 "map": {"at": 35136, "to": "mm"}, 2732 "name": "VGT_PERFCOUNTER2_LO", 2733 "type_ref": "GRBM_PERFCOUNTER0_LO" 2734 }, 2735 { 2736 "chips": ["gfx6"], 2737 "map": {"at": 35140, "to": "mm"}, 2738 "name": "VGT_PERFCOUNTER2_HI", 2739 "type_ref": "GRBM_PERFCOUNTER0_HI" 2740 }, 2741 { 2742 "chips": ["gfx6"], 2743 "map": {"at": 35144, "to": "mm"}, 2744 "name": "VGT_PERFCOUNTER3_LO", 2745 "type_ref": "GRBM_PERFCOUNTER0_LO" 2746 }, 2747 { 2748 "chips": ["gfx6"], 2749 "map": {"at": 35148, "to": "mm"}, 2750 "name": "VGT_PERFCOUNTER3_HI", 2751 "type_ref": "GRBM_PERFCOUNTER0_HI" 2752 }, 2753 { 2754 "chips": ["gfx6"], 2755 "map": {"at": 35160, "to": "mm"}, 2756 "name": "VGT_PRIMITIVE_TYPE", 2757 "type_ref": "VGT_PRIMITIVE_TYPE" 2758 }, 2759 { 2760 "chips": ["gfx6"], 2761 "map": {"at": 35164, "to": "mm"}, 2762 "name": "VGT_INDEX_TYPE", 2763 "type_ref": "VGT_INDEX_TYPE" 2764 }, 2765 { 2766 "chips": ["gfx6"], 2767 "map": {"at": 35168, "to": "mm"}, 2768 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0", 2769 "type_ref": "COMPUTE_DIM_X" 2770 }, 2771 { 2772 "chips": ["gfx6"], 2773 "map": {"at": 35172, "to": "mm"}, 2774 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1", 2775 "type_ref": "COMPUTE_DIM_X" 2776 }, 2777 { 2778 "chips": ["gfx6"], 2779 "map": {"at": 35176, "to": "mm"}, 2780 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2", 2781 "type_ref": "COMPUTE_DIM_X" 2782 }, 2783 { 2784 "chips": ["gfx6"], 2785 "map": {"at": 35180, "to": "mm"}, 2786 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3", 2787 "type_ref": "COMPUTE_DIM_X" 2788 }, 2789 { 2790 "chips": ["gfx6"], 2791 "map": {"at": 35184, "to": "mm"}, 2792 "name": "VGT_NUM_INDICES", 2793 "type_ref": "VGT_DMA_SIZE" 2794 }, 2795 { 2796 "chips": ["gfx6"], 2797 "map": {"at": 35188, "to": "mm"}, 2798 "name": "VGT_NUM_INSTANCES", 2799 "type_ref": "VGT_DMA_NUM_INSTANCES" 2800 }, 2801 { 2802 "chips": ["gfx6"], 2803 "map": {"at": 35196, "to": "mm"}, 2804 "name": "CGTT_VGT_CLK_CTRL", 2805 "type_ref": "CGTT_VGT_CLK_CTRL" 2806 }, 2807 { 2808 "chips": ["gfx6"], 2809 "map": {"at": 35200, "to": "mm"}, 2810 "name": "IA_VMID_OVERRIDE", 2811 "type_ref": "IA_VMID_OVERRIDE" 2812 }, 2813 { 2814 "chips": ["gfx6"], 2815 "map": {"at": 35204, "to": "mm"}, 2816 "name": "CGTT_IA_CLK_CTRL", 2817 "type_ref": "CGTT_IA_CLK_CTRL" 2818 }, 2819 { 2820 "chips": ["gfx6"], 2821 "map": {"at": 35208, "to": "mm"}, 2822 "name": "VGT_TF_RING_SIZE", 2823 "type_ref": "VGT_TF_RING_SIZE" 2824 }, 2825 { 2826 "chips": ["gfx6"], 2827 "map": {"at": 35212, "to": "mm"}, 2828 "name": "VGT_SYS_CONFIG", 2829 "type_ref": "VGT_SYS_CONFIG" 2830 }, 2831 { 2832 "chips": ["gfx6"], 2833 "map": {"at": 35248, "to": "mm"}, 2834 "name": "VGT_HS_OFFCHIP_PARAM", 2835 "type_ref": "VGT_HS_OFFCHIP_PARAM" 2836 }, 2837 { 2838 "chips": ["gfx6"], 2839 "map": {"at": 35256, "to": "mm"}, 2840 "name": "VGT_TF_MEMORY_BASE", 2841 "type_ref": "VGT_TF_MEMORY_BASE" 2842 }, 2843 { 2844 "chips": ["gfx6"], 2845 "map": {"at": 35260, "to": "mm"}, 2846 "name": "CC_GC_SHADER_ARRAY_CONFIG", 2847 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2848 }, 2849 { 2850 "chips": ["gfx6"], 2851 "map": {"at": 35264, "to": "mm"}, 2852 "name": "GC_USER_SHADER_ARRAY_CONFIG", 2853 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2854 }, 2855 { 2856 "chips": ["gfx6"], 2857 "map": {"at": 35328, "to": "mm"}, 2858 "name": "PA_SU_DEBUG_CNTL", 2859 "type_ref": "PA_SU_DEBUG_CNTL" 2860 }, 2861 { 2862 "chips": ["gfx6"], 2863 "map": {"at": 35332, "to": "mm"}, 2864 "name": "PA_SU_DEBUG_DATA", 2865 "type_ref": "SQ_WAVE_TTMP0" 2866 }, 2867 { 2868 "chips": ["gfx6"], 2869 "map": {"at": 35344, "to": "mm"}, 2870 "name": "PA_CL_CNTL_STATUS", 2871 "type_ref": "PA_CL_CNTL_STATUS" 2872 }, 2873 { 2874 "chips": ["gfx6"], 2875 "map": {"at": 35348, "to": "mm"}, 2876 "name": "PA_CL_ENHANCE", 2877 "type_ref": "PA_CL_ENHANCE" 2878 }, 2879 { 2880 "chips": ["gfx6"], 2881 "map": {"at": 35352, "to": "mm"}, 2882 "name": "CGTT_PA_CLK_CTRL", 2883 "type_ref": "CGTT_PA_CLK_CTRL" 2884 }, 2885 { 2886 "chips": ["gfx6"], 2887 "map": {"at": 35360, "to": "mm"}, 2888 "name": "PA_SU_PERFCOUNTER0_SELECT", 2889 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2890 }, 2891 { 2892 "chips": ["gfx6"], 2893 "map": {"at": 35364, "to": "mm"}, 2894 "name": "PA_SU_PERFCOUNTER1_SELECT", 2895 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2896 }, 2897 { 2898 "chips": ["gfx6"], 2899 "map": {"at": 35368, "to": "mm"}, 2900 "name": "PA_SU_PERFCOUNTER2_SELECT", 2901 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2902 }, 2903 { 2904 "chips": ["gfx6"], 2905 "map": {"at": 35372, "to": "mm"}, 2906 "name": "PA_SU_PERFCOUNTER3_SELECT", 2907 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2908 }, 2909 { 2910 "chips": ["gfx6"], 2911 "map": {"at": 35376, "to": "mm"}, 2912 "name": "PA_SU_PERFCOUNTER0_LO", 2913 "type_ref": "GRBM_PERFCOUNTER0_LO" 2914 }, 2915 { 2916 "chips": ["gfx6"], 2917 "map": {"at": 35380, "to": "mm"}, 2918 "name": "PA_SU_PERFCOUNTER0_HI", 2919 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2920 }, 2921 { 2922 "chips": ["gfx6"], 2923 "map": {"at": 35384, "to": "mm"}, 2924 "name": "PA_SU_PERFCOUNTER1_LO", 2925 "type_ref": "GRBM_PERFCOUNTER0_LO" 2926 }, 2927 { 2928 "chips": ["gfx6"], 2929 "map": {"at": 35388, "to": "mm"}, 2930 "name": "PA_SU_PERFCOUNTER1_HI", 2931 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2932 }, 2933 { 2934 "chips": ["gfx6"], 2935 "map": {"at": 35392, "to": "mm"}, 2936 "name": "PA_SU_PERFCOUNTER2_LO", 2937 "type_ref": "GRBM_PERFCOUNTER0_LO" 2938 }, 2939 { 2940 "chips": ["gfx6"], 2941 "map": {"at": 35396, "to": "mm"}, 2942 "name": "PA_SU_PERFCOUNTER2_HI", 2943 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2944 }, 2945 { 2946 "chips": ["gfx6"], 2947 "map": {"at": 35400, "to": "mm"}, 2948 "name": "PA_SU_PERFCOUNTER3_LO", 2949 "type_ref": "GRBM_PERFCOUNTER0_LO" 2950 }, 2951 { 2952 "chips": ["gfx6"], 2953 "map": {"at": 35404, "to": "mm"}, 2954 "name": "PA_SU_PERFCOUNTER3_HI", 2955 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2956 }, 2957 { 2958 "chips": ["gfx6"], 2959 "map": {"at": 35408, "to": "mm"}, 2960 "name": "PA_SU_CNTL_STATUS", 2961 "type_ref": "PA_SU_CNTL_STATUS" 2962 }, 2963 { 2964 "chips": ["gfx6"], 2965 "map": {"at": 35412, "to": "mm"}, 2966 "name": "PA_SC_FIFO_DEPTH_CNTL", 2967 "type_ref": "PA_SC_FIFO_DEPTH_CNTL" 2968 }, 2969 { 2970 "chips": ["gfx6"], 2971 "map": {"at": 35424, "to": "mm"}, 2972 "name": "PA_SU_LINE_STIPPLE_VALUE", 2973 "type_ref": "PA_SU_LINE_STIPPLE_VALUE" 2974 }, 2975 { 2976 "chips": ["gfx6"], 2977 "map": {"at": 35456, "to": "mm"}, 2978 "name": "PA_SC_PERFCOUNTER0_SELECT", 2979 "type_ref": "PA_SC_PERFCOUNTER0_SELECT" 2980 }, 2981 { 2982 "chips": ["gfx6"], 2983 "map": {"at": 35460, "to": "mm"}, 2984 "name": "PA_SC_PERFCOUNTER1_SELECT", 2985 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2986 }, 2987 { 2988 "chips": ["gfx6"], 2989 "map": {"at": 35464, "to": "mm"}, 2990 "name": "PA_SC_PERFCOUNTER2_SELECT", 2991 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2992 }, 2993 { 2994 "chips": ["gfx6"], 2995 "map": {"at": 35468, "to": "mm"}, 2996 "name": "PA_SC_PERFCOUNTER3_SELECT", 2997 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2998 }, 2999 { 3000 "chips": ["gfx6"], 3001 "map": {"at": 35472, "to": "mm"}, 3002 "name": "PA_SC_PERFCOUNTER4_SELECT", 3003 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 3004 }, 3005 { 3006 "chips": ["gfx6"], 3007 "map": {"at": 35476, "to": "mm"}, 3008 "name": "PA_SC_PERFCOUNTER5_SELECT", 3009 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 3010 }, 3011 { 3012 "chips": ["gfx6"], 3013 "map": {"at": 35480, "to": "mm"}, 3014 "name": "PA_SC_PERFCOUNTER6_SELECT", 3015 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 3016 }, 3017 { 3018 "chips": ["gfx6"], 3019 "map": {"at": 35484, "to": "mm"}, 3020 "name": "PA_SC_PERFCOUNTER7_SELECT", 3021 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 3022 }, 3023 { 3024 "chips": ["gfx6"], 3025 "map": {"at": 35488, "to": "mm"}, 3026 "name": "PA_SC_PERFCOUNTER0_LO", 3027 "type_ref": "GRBM_PERFCOUNTER0_LO" 3028 }, 3029 { 3030 "chips": ["gfx6"], 3031 "map": {"at": 35492, "to": "mm"}, 3032 "name": "PA_SC_PERFCOUNTER0_HI", 3033 "type_ref": "GRBM_PERFCOUNTER0_HI" 3034 }, 3035 { 3036 "chips": ["gfx6"], 3037 "map": {"at": 35496, "to": "mm"}, 3038 "name": "PA_SC_PERFCOUNTER1_LO", 3039 "type_ref": "GRBM_PERFCOUNTER0_LO" 3040 }, 3041 { 3042 "chips": ["gfx6"], 3043 "map": {"at": 35500, "to": "mm"}, 3044 "name": "PA_SC_PERFCOUNTER1_HI", 3045 "type_ref": "GRBM_PERFCOUNTER0_HI" 3046 }, 3047 { 3048 "chips": ["gfx6"], 3049 "map": {"at": 35504, "to": "mm"}, 3050 "name": "PA_SC_PERFCOUNTER2_LO", 3051 "type_ref": "GRBM_PERFCOUNTER0_LO" 3052 }, 3053 { 3054 "chips": ["gfx6"], 3055 "map": {"at": 35508, "to": "mm"}, 3056 "name": "PA_SC_PERFCOUNTER2_HI", 3057 "type_ref": "GRBM_PERFCOUNTER0_HI" 3058 }, 3059 { 3060 "chips": ["gfx6"], 3061 "map": {"at": 35512, "to": "mm"}, 3062 "name": "PA_SC_PERFCOUNTER3_LO", 3063 "type_ref": "GRBM_PERFCOUNTER0_LO" 3064 }, 3065 { 3066 "chips": ["gfx6"], 3067 "map": {"at": 35516, "to": "mm"}, 3068 "name": "PA_SC_PERFCOUNTER3_HI", 3069 "type_ref": "GRBM_PERFCOUNTER0_HI" 3070 }, 3071 { 3072 "chips": ["gfx6"], 3073 "map": {"at": 35520, "to": "mm"}, 3074 "name": "PA_SC_PERFCOUNTER4_LO", 3075 "type_ref": "GRBM_PERFCOUNTER0_LO" 3076 }, 3077 { 3078 "chips": ["gfx6"], 3079 "map": {"at": 35524, "to": "mm"}, 3080 "name": "PA_SC_PERFCOUNTER4_HI", 3081 "type_ref": "GRBM_PERFCOUNTER0_HI" 3082 }, 3083 { 3084 "chips": ["gfx6"], 3085 "map": {"at": 35528, "to": "mm"}, 3086 "name": "PA_SC_PERFCOUNTER5_LO", 3087 "type_ref": "GRBM_PERFCOUNTER0_LO" 3088 }, 3089 { 3090 "chips": ["gfx6"], 3091 "map": {"at": 35532, "to": "mm"}, 3092 "name": "PA_SC_PERFCOUNTER5_HI", 3093 "type_ref": "GRBM_PERFCOUNTER0_HI" 3094 }, 3095 { 3096 "chips": ["gfx6"], 3097 "map": {"at": 35536, "to": "mm"}, 3098 "name": "PA_SC_PERFCOUNTER6_LO", 3099 "type_ref": "GRBM_PERFCOUNTER0_LO" 3100 }, 3101 { 3102 "chips": ["gfx6"], 3103 "map": {"at": 35540, "to": "mm"}, 3104 "name": "PA_SC_PERFCOUNTER6_HI", 3105 "type_ref": "GRBM_PERFCOUNTER0_HI" 3106 }, 3107 { 3108 "chips": ["gfx6"], 3109 "map": {"at": 35544, "to": "mm"}, 3110 "name": "PA_SC_PERFCOUNTER7_LO", 3111 "type_ref": "GRBM_PERFCOUNTER0_LO" 3112 }, 3113 { 3114 "chips": ["gfx6"], 3115 "map": {"at": 35548, "to": "mm"}, 3116 "name": "PA_SC_PERFCOUNTER7_HI", 3117 "type_ref": "GRBM_PERFCOUNTER0_HI" 3118 }, 3119 { 3120 "chips": ["gfx6"], 3121 "map": {"at": 35600, "to": "mm"}, 3122 "name": "PA_SC_LINE_STIPPLE_STATE", 3123 "type_ref": "PA_SC_LINE_STIPPLE_STATE" 3124 }, 3125 { 3126 "chips": ["gfx6"], 3127 "map": {"at": 35620, "to": "mm"}, 3128 "name": "PA_SC_FORCE_EOV_MAX_CNTS", 3129 "type_ref": "PA_SC_FORCE_EOV_MAX_CNTS" 3130 }, 3131 { 3132 "chips": ["gfx6"], 3133 "map": {"at": 35624, "to": "mm"}, 3134 "name": "CGTT_SC_CLK_CTRL", 3135 "type_ref": "CGTT_SC_CLK_CTRL" 3136 }, 3137 { 3138 "chips": ["gfx6"], 3139 "map": {"at": 35788, "to": "mm"}, 3140 "name": "PA_SC_FIFO_SIZE", 3141 "type_ref": "PA_SC_FIFO_SIZE" 3142 }, 3143 { 3144 "chips": ["gfx6"], 3145 "map": {"at": 35796, "to": "mm"}, 3146 "name": "PA_SC_IF_FIFO_SIZE", 3147 "type_ref": "PA_SC_IF_FIFO_SIZE" 3148 }, 3149 { 3150 "chips": ["gfx6"], 3151 "map": {"at": 35800, "to": "mm"}, 3152 "name": "PA_SC_DEBUG_CNTL", 3153 "type_ref": "PA_SC_DEBUG_CNTL" 3154 }, 3155 { 3156 "chips": ["gfx6"], 3157 "map": {"at": 35804, "to": "mm"}, 3158 "name": "PA_SC_DEBUG_DATA", 3159 "type_ref": "SQ_WAVE_TTMP0" 3160 }, 3161 { 3162 "chips": ["gfx6"], 3163 "map": {"at": 35824, "to": "mm"}, 3164 "name": "PA_SC_ENHANCE", 3165 "type_ref": "PA_SC_ENHANCE" 3166 }, 3167 { 3168 "chips": ["gfx6"], 3169 "map": {"at": 35840, "to": "mm"}, 3170 "name": "SQ_CONFIG", 3171 "type_ref": "SQ_CONFIG" 3172 }, 3173 { 3174 "chips": ["gfx6"], 3175 "map": {"at": 35844, "to": "mm"}, 3176 "name": "SQC_CONFIG", 3177 "type_ref": "SQC_CONFIG" 3178 }, 3179 { 3180 "chips": ["gfx6"], 3181 "map": {"at": 35848, "to": "mm"}, 3182 "name": "SQC_CACHES", 3183 "type_ref": "SQC_CACHES" 3184 }, 3185 { 3186 "chips": ["gfx6"], 3187 "map": {"at": 35852, "to": "mm"}, 3188 "name": "SQ_RANDOM_WAVE_PRI", 3189 "type_ref": "SQ_RANDOM_WAVE_PRI" 3190 }, 3191 { 3192 "chips": ["gfx6"], 3193 "map": {"at": 35856, "to": "mm"}, 3194 "name": "SQ_REG_CREDITS", 3195 "type_ref": "SQ_REG_CREDITS" 3196 }, 3197 { 3198 "chips": ["gfx6"], 3199 "map": {"at": 35860, "to": "mm"}, 3200 "name": "SQ_FIFO_SIZES", 3201 "type_ref": "SQ_FIFO_SIZES" 3202 }, 3203 { 3204 "chips": ["gfx6"], 3205 "map": {"at": 35864, "to": "mm"}, 3206 "name": "SQ_PERFCOUNTER_CTRL", 3207 "type_ref": "SQ_PERFCOUNTER_CTRL" 3208 }, 3209 { 3210 "chips": ["gfx6"], 3211 "map": {"at": 35868, "to": "mm"}, 3212 "name": "CC_SQC_BANK_DISABLE", 3213 "type_ref": "CC_SQC_BANK_DISABLE" 3214 }, 3215 { 3216 "chips": ["gfx6"], 3217 "map": {"at": 35872, "to": "mm"}, 3218 "name": "USER_SQC_BANK_DISABLE", 3219 "type_ref": "CC_SQC_BANK_DISABLE" 3220 }, 3221 { 3222 "chips": ["gfx6"], 3223 "map": {"at": 35876, "to": "mm"}, 3224 "name": "SQ_DEBUG_STS_GLOBAL", 3225 "type_ref": "SQ_DEBUG_STS_GLOBAL" 3226 }, 3227 { 3228 "chips": ["gfx6"], 3229 "map": {"at": 35968, "to": "mm"}, 3230 "name": "SQ_PERFCOUNTER0_LO", 3231 "type_ref": "GRBM_PERFCOUNTER0_LO" 3232 }, 3233 { 3234 "chips": ["gfx6"], 3235 "map": {"at": 35972, "to": "mm"}, 3236 "name": "SQ_PERFCOUNTER0_HI", 3237 "type_ref": "GRBM_PERFCOUNTER0_HI" 3238 }, 3239 { 3240 "chips": ["gfx6"], 3241 "map": {"at": 35976, "to": "mm"}, 3242 "name": "SQ_PERFCOUNTER1_LO", 3243 "type_ref": "GRBM_PERFCOUNTER0_LO" 3244 }, 3245 { 3246 "chips": ["gfx6"], 3247 "map": {"at": 35980, "to": "mm"}, 3248 "name": "SQ_PERFCOUNTER1_HI", 3249 "type_ref": "GRBM_PERFCOUNTER0_HI" 3250 }, 3251 { 3252 "chips": ["gfx6"], 3253 "map": {"at": 35984, "to": "mm"}, 3254 "name": "SQ_PERFCOUNTER2_LO", 3255 "type_ref": "GRBM_PERFCOUNTER0_LO" 3256 }, 3257 { 3258 "chips": ["gfx6"], 3259 "map": {"at": 35988, "to": "mm"}, 3260 "name": "SQ_PERFCOUNTER2_HI", 3261 "type_ref": "GRBM_PERFCOUNTER0_HI" 3262 }, 3263 { 3264 "chips": ["gfx6"], 3265 "map": {"at": 35992, "to": "mm"}, 3266 "name": "SQ_PERFCOUNTER3_LO", 3267 "type_ref": "GRBM_PERFCOUNTER0_LO" 3268 }, 3269 { 3270 "chips": ["gfx6"], 3271 "map": {"at": 35996, "to": "mm"}, 3272 "name": "SQ_PERFCOUNTER3_HI", 3273 "type_ref": "GRBM_PERFCOUNTER0_HI" 3274 }, 3275 { 3276 "chips": ["gfx6"], 3277 "map": {"at": 36000, "to": "mm"}, 3278 "name": "SQ_PERFCOUNTER4_LO", 3279 "type_ref": "GRBM_PERFCOUNTER0_LO" 3280 }, 3281 { 3282 "chips": ["gfx6"], 3283 "map": {"at": 36004, "to": "mm"}, 3284 "name": "SQ_PERFCOUNTER4_HI", 3285 "type_ref": "GRBM_PERFCOUNTER0_HI" 3286 }, 3287 { 3288 "chips": ["gfx6"], 3289 "map": {"at": 36008, "to": "mm"}, 3290 "name": "SQ_PERFCOUNTER5_LO", 3291 "type_ref": "GRBM_PERFCOUNTER0_LO" 3292 }, 3293 { 3294 "chips": ["gfx6"], 3295 "map": {"at": 36012, "to": "mm"}, 3296 "name": "SQ_PERFCOUNTER5_HI", 3297 "type_ref": "GRBM_PERFCOUNTER0_HI" 3298 }, 3299 { 3300 "chips": ["gfx6"], 3301 "map": {"at": 36016, "to": "mm"}, 3302 "name": "SQ_PERFCOUNTER6_LO", 3303 "type_ref": "GRBM_PERFCOUNTER0_LO" 3304 }, 3305 { 3306 "chips": ["gfx6"], 3307 "map": {"at": 36020, "to": "mm"}, 3308 "name": "SQ_PERFCOUNTER6_HI", 3309 "type_ref": "GRBM_PERFCOUNTER0_HI" 3310 }, 3311 { 3312 "chips": ["gfx6"], 3313 "map": {"at": 36024, "to": "mm"}, 3314 "name": "SQ_PERFCOUNTER7_LO", 3315 "type_ref": "GRBM_PERFCOUNTER0_LO" 3316 }, 3317 { 3318 "chips": ["gfx6"], 3319 "map": {"at": 36028, "to": "mm"}, 3320 "name": "SQ_PERFCOUNTER7_HI", 3321 "type_ref": "GRBM_PERFCOUNTER0_HI" 3322 }, 3323 { 3324 "chips": ["gfx6"], 3325 "map": {"at": 36032, "to": "mm"}, 3326 "name": "SQ_PERFCOUNTER8_LO", 3327 "type_ref": "GRBM_PERFCOUNTER0_LO" 3328 }, 3329 { 3330 "chips": ["gfx6"], 3331 "map": {"at": 36036, "to": "mm"}, 3332 "name": "SQ_PERFCOUNTER8_HI", 3333 "type_ref": "GRBM_PERFCOUNTER0_HI" 3334 }, 3335 { 3336 "chips": ["gfx6"], 3337 "map": {"at": 36040, "to": "mm"}, 3338 "name": "SQ_PERFCOUNTER9_LO", 3339 "type_ref": "GRBM_PERFCOUNTER0_LO" 3340 }, 3341 { 3342 "chips": ["gfx6"], 3343 "map": {"at": 36044, "to": "mm"}, 3344 "name": "SQ_PERFCOUNTER9_HI", 3345 "type_ref": "GRBM_PERFCOUNTER0_HI" 3346 }, 3347 { 3348 "chips": ["gfx6"], 3349 "map": {"at": 36048, "to": "mm"}, 3350 "name": "SQ_PERFCOUNTER10_LO", 3351 "type_ref": "GRBM_PERFCOUNTER0_LO" 3352 }, 3353 { 3354 "chips": ["gfx6"], 3355 "map": {"at": 36052, "to": "mm"}, 3356 "name": "SQ_PERFCOUNTER10_HI", 3357 "type_ref": "GRBM_PERFCOUNTER0_HI" 3358 }, 3359 { 3360 "chips": ["gfx6"], 3361 "map": {"at": 36056, "to": "mm"}, 3362 "name": "SQ_PERFCOUNTER11_LO", 3363 "type_ref": "GRBM_PERFCOUNTER0_LO" 3364 }, 3365 { 3366 "chips": ["gfx6"], 3367 "map": {"at": 36060, "to": "mm"}, 3368 "name": "SQ_PERFCOUNTER11_HI", 3369 "type_ref": "GRBM_PERFCOUNTER0_HI" 3370 }, 3371 { 3372 "chips": ["gfx6"], 3373 "map": {"at": 36064, "to": "mm"}, 3374 "name": "SQ_PERFCOUNTER12_LO", 3375 "type_ref": "GRBM_PERFCOUNTER0_LO" 3376 }, 3377 { 3378 "chips": ["gfx6"], 3379 "map": {"at": 36068, "to": "mm"}, 3380 "name": "SQ_PERFCOUNTER12_HI", 3381 "type_ref": "GRBM_PERFCOUNTER0_HI" 3382 }, 3383 { 3384 "chips": ["gfx6"], 3385 "map": {"at": 36072, "to": "mm"}, 3386 "name": "SQ_PERFCOUNTER13_LO", 3387 "type_ref": "GRBM_PERFCOUNTER0_LO" 3388 }, 3389 { 3390 "chips": ["gfx6"], 3391 "map": {"at": 36076, "to": "mm"}, 3392 "name": "SQ_PERFCOUNTER13_HI", 3393 "type_ref": "GRBM_PERFCOUNTER0_HI" 3394 }, 3395 { 3396 "chips": ["gfx6"], 3397 "map": {"at": 36080, "to": "mm"}, 3398 "name": "SQ_PERFCOUNTER14_LO", 3399 "type_ref": "GRBM_PERFCOUNTER0_LO" 3400 }, 3401 { 3402 "chips": ["gfx6"], 3403 "map": {"at": 36084, "to": "mm"}, 3404 "name": "SQ_PERFCOUNTER14_HI", 3405 "type_ref": "GRBM_PERFCOUNTER0_HI" 3406 }, 3407 { 3408 "chips": ["gfx6"], 3409 "map": {"at": 36088, "to": "mm"}, 3410 "name": "SQ_PERFCOUNTER15_LO", 3411 "type_ref": "GRBM_PERFCOUNTER0_LO" 3412 }, 3413 { 3414 "chips": ["gfx6"], 3415 "map": {"at": 36092, "to": "mm"}, 3416 "name": "SQ_PERFCOUNTER15_HI", 3417 "type_ref": "GRBM_PERFCOUNTER0_HI" 3418 }, 3419 { 3420 "chips": ["gfx6"], 3421 "map": {"at": 36096, "to": "mm"}, 3422 "name": "SQ_PERFCOUNTER0_SELECT", 3423 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3424 }, 3425 { 3426 "chips": ["gfx6"], 3427 "map": {"at": 36100, "to": "mm"}, 3428 "name": "SQ_PERFCOUNTER1_SELECT", 3429 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3430 }, 3431 { 3432 "chips": ["gfx6"], 3433 "map": {"at": 36104, "to": "mm"}, 3434 "name": "SQ_PERFCOUNTER2_SELECT", 3435 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3436 }, 3437 { 3438 "chips": ["gfx6"], 3439 "map": {"at": 36108, "to": "mm"}, 3440 "name": "SQ_PERFCOUNTER3_SELECT", 3441 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3442 }, 3443 { 3444 "chips": ["gfx6"], 3445 "map": {"at": 36112, "to": "mm"}, 3446 "name": "SQ_PERFCOUNTER4_SELECT", 3447 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3448 }, 3449 { 3450 "chips": ["gfx6"], 3451 "map": {"at": 36116, "to": "mm"}, 3452 "name": "SQ_PERFCOUNTER5_SELECT", 3453 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3454 }, 3455 { 3456 "chips": ["gfx6"], 3457 "map": {"at": 36120, "to": "mm"}, 3458 "name": "SQ_PERFCOUNTER6_SELECT", 3459 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3460 }, 3461 { 3462 "chips": ["gfx6"], 3463 "map": {"at": 36124, "to": "mm"}, 3464 "name": "SQ_PERFCOUNTER7_SELECT", 3465 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3466 }, 3467 { 3468 "chips": ["gfx6"], 3469 "map": {"at": 36128, "to": "mm"}, 3470 "name": "SQ_PERFCOUNTER8_SELECT", 3471 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3472 }, 3473 { 3474 "chips": ["gfx6"], 3475 "map": {"at": 36132, "to": "mm"}, 3476 "name": "SQ_PERFCOUNTER9_SELECT", 3477 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3478 }, 3479 { 3480 "chips": ["gfx6"], 3481 "map": {"at": 36136, "to": "mm"}, 3482 "name": "SQ_PERFCOUNTER10_SELECT", 3483 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3484 }, 3485 { 3486 "chips": ["gfx6"], 3487 "map": {"at": 36140, "to": "mm"}, 3488 "name": "SQ_PERFCOUNTER11_SELECT", 3489 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3490 }, 3491 { 3492 "chips": ["gfx6"], 3493 "map": {"at": 36144, "to": "mm"}, 3494 "name": "SQ_PERFCOUNTER12_SELECT", 3495 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3496 }, 3497 { 3498 "chips": ["gfx6"], 3499 "map": {"at": 36148, "to": "mm"}, 3500 "name": "SQ_PERFCOUNTER13_SELECT", 3501 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3502 }, 3503 { 3504 "chips": ["gfx6"], 3505 "map": {"at": 36152, "to": "mm"}, 3506 "name": "SQ_PERFCOUNTER14_SELECT", 3507 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3508 }, 3509 { 3510 "chips": ["gfx6"], 3511 "map": {"at": 36156, "to": "mm"}, 3512 "name": "SQ_PERFCOUNTER15_SELECT", 3513 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3514 }, 3515 { 3516 "chips": ["gfx6"], 3517 "map": {"at": 36224, "to": "mm"}, 3518 "name": "SQ_ALU_CLK_CTRL", 3519 "type_ref": "SQ_ALU_CLK_CTRL" 3520 }, 3521 { 3522 "chips": ["gfx6"], 3523 "map": {"at": 36228, "to": "mm"}, 3524 "name": "SQ_TEX_CLK_CTRL", 3525 "type_ref": "SQ_ALU_CLK_CTRL" 3526 }, 3527 { 3528 "chips": ["gfx6"], 3529 "map": {"at": 36232, "to": "mm"}, 3530 "name": "CGTT_SQ_CLK_CTRL", 3531 "type_ref": "CGTT_SQ_CLK_CTRL" 3532 }, 3533 { 3534 "chips": ["gfx6"], 3535 "map": {"at": 36236, "to": "mm"}, 3536 "name": "CGTT_SQG_CLK_CTRL", 3537 "type_ref": "CGTT_SQ_CLK_CTRL" 3538 }, 3539 { 3540 "chips": ["gfx6"], 3541 "map": {"at": 36320, "to": "mm"}, 3542 "name": "SQ_IND_INDEX", 3543 "type_ref": "SQ_IND_INDEX" 3544 }, 3545 { 3546 "chips": ["gfx6"], 3547 "map": {"at": 36324, "to": "mm"}, 3548 "name": "SQ_IND_DATA", 3549 "type_ref": "SQ_WAVE_TTMP0" 3550 }, 3551 { 3552 "chips": ["gfx6"], 3553 "map": {"at": 36336, "to": "mm"}, 3554 "name": "SQ_TIME_HI", 3555 "type_ref": "SQ_TIME_HI" 3556 }, 3557 { 3558 "chips": ["gfx6"], 3559 "map": {"at": 36340, "to": "mm"}, 3560 "name": "SQ_TIME_LO", 3561 "type_ref": "SQ_TIME_HI" 3562 }, 3563 { 3564 "chips": ["gfx6"], 3565 "map": {"at": 36352, "to": "mm"}, 3566 "name": "SQ_THREAD_TRACE_BASE", 3567 "type_ref": "SQ_THREAD_TRACE_BASE" 3568 }, 3569 { 3570 "chips": ["gfx6"], 3571 "map": {"at": 36356, "to": "mm"}, 3572 "name": "SQ_THREAD_TRACE_SIZE", 3573 "type_ref": "SQ_THREAD_TRACE_SIZE" 3574 }, 3575 { 3576 "chips": ["gfx6"], 3577 "map": {"at": 36360, "to": "mm"}, 3578 "name": "SQ_THREAD_TRACE_MASK", 3579 "type_ref": "SQ_THREAD_TRACE_MASK" 3580 }, 3581 { 3582 "chips": ["gfx6"], 3583 "map": {"at": 36364, "to": "mm"}, 3584 "name": "SQ_THREAD_TRACE_TOKEN_MASK", 3585 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK" 3586 }, 3587 { 3588 "chips": ["gfx6"], 3589 "map": {"at": 36368, "to": "mm"}, 3590 "name": "SQ_THREAD_TRACE_PERF_MASK", 3591 "type_ref": "SQ_THREAD_TRACE_PERF_MASK" 3592 }, 3593 { 3594 "chips": ["gfx6"], 3595 "map": {"at": 36384, "to": "mm"}, 3596 "name": "SQ_THREAD_TRACE_USERDATA_0", 3597 "type_ref": "SQ_WAVE_TTMP0" 3598 }, 3599 { 3600 "chips": ["gfx6"], 3601 "map": {"at": 36388, "to": "mm"}, 3602 "name": "SQ_THREAD_TRACE_USERDATA_1", 3603 "type_ref": "SQ_WAVE_TTMP0" 3604 }, 3605 { 3606 "chips": ["gfx6"], 3607 "map": {"at": 36392, "to": "mm"}, 3608 "name": "SQ_THREAD_TRACE_USERDATA_2", 3609 "type_ref": "SQ_WAVE_TTMP0" 3610 }, 3611 { 3612 "chips": ["gfx6"], 3613 "map": {"at": 36396, "to": "mm"}, 3614 "name": "SQ_THREAD_TRACE_USERDATA_3", 3615 "type_ref": "SQ_WAVE_TTMP0" 3616 }, 3617 { 3618 "chips": ["gfx6"], 3619 "map": {"at": 36400, "to": "mm"}, 3620 "name": "SQ_THREAD_TRACE_WPTR", 3621 "type_ref": "SQ_THREAD_TRACE_WPTR" 3622 }, 3623 { 3624 "chips": ["gfx6"], 3625 "map": {"at": 36404, "to": "mm"}, 3626 "name": "SQ_THREAD_TRACE_STATUS", 3627 "type_ref": "SQ_THREAD_TRACE_STATUS" 3628 }, 3629 { 3630 "chips": ["gfx6"], 3631 "map": {"at": 36408, "to": "mm"}, 3632 "name": "SQ_THREAD_TRACE_MODE", 3633 "type_ref": "SQ_THREAD_TRACE_MODE" 3634 }, 3635 { 3636 "chips": ["gfx6"], 3637 "map": {"at": 36412, "to": "mm"}, 3638 "name": "SQ_THREAD_TRACE_CTRL", 3639 "type_ref": "SQ_THREAD_TRACE_CTRL" 3640 }, 3641 { 3642 "chips": ["gfx6"], 3643 "map": {"at": 36416, "to": "mm"}, 3644 "name": "SQ_THREAD_TRACE_CNTR", 3645 "type_ref": "SQ_THREAD_TRACE_CNTR" 3646 }, 3647 { 3648 "chips": ["gfx6"], 3649 "map": {"at": 36424, "to": "mm"}, 3650 "name": "SQ_THREAD_TRACE_HIWATER", 3651 "type_ref": "SQ_THREAD_TRACE_HIWATER" 3652 }, 3653 { 3654 "chips": ["gfx6"], 3655 "map": {"at": 36440, "to": "mm"}, 3656 "name": "SQ_POWER_THROTTLE", 3657 "type_ref": "SQ_POWER_THROTTLE" 3658 }, 3659 { 3660 "chips": ["gfx6"], 3661 "map": {"at": 36444, "to": "mm"}, 3662 "name": "SQ_POWER_THROTTLE2", 3663 "type_ref": "SQ_POWER_THROTTLE2" 3664 }, 3665 { 3666 "chips": ["gfx6"], 3667 "map": {"at": 36448, "to": "mm"}, 3668 "name": "SQ_LB_CTR_CTRL", 3669 "type_ref": "SQ_LB_CTR_CTRL" 3670 }, 3671 { 3672 "chips": ["gfx6"], 3673 "map": {"at": 36452, "to": "mm"}, 3674 "name": "SQ_LB_DATA_ALU_CYCLES", 3675 "type_ref": "SQ_WAVE_TTMP0" 3676 }, 3677 { 3678 "chips": ["gfx6"], 3679 "map": {"at": 36456, "to": "mm"}, 3680 "name": "SQ_LB_DATA_TEX_CYCLES", 3681 "type_ref": "SQ_WAVE_TTMP0" 3682 }, 3683 { 3684 "chips": ["gfx6"], 3685 "map": {"at": 36460, "to": "mm"}, 3686 "name": "SQ_LB_DATA_ALU_STALLS", 3687 "type_ref": "SQ_WAVE_TTMP0" 3688 }, 3689 { 3690 "chips": ["gfx6"], 3691 "map": {"at": 36464, "to": "mm"}, 3692 "name": "SQ_LB_DATA_TEX_STALLS", 3693 "type_ref": "SQ_WAVE_TTMP0" 3694 }, 3695 { 3696 "chips": ["gfx6"], 3697 "map": {"at": 36480, "to": "mm"}, 3698 "name": "SQC_SECDED_CNT", 3699 "type_ref": "SQC_SECDED_CNT" 3700 }, 3701 { 3702 "chips": ["gfx6"], 3703 "map": {"at": 36484, "to": "mm"}, 3704 "name": "SQ_SEC_CNT", 3705 "type_ref": "SQ_SEC_CNT" 3706 }, 3707 { 3708 "chips": ["gfx6"], 3709 "map": {"at": 36488, "to": "mm"}, 3710 "name": "SQ_DED_CNT", 3711 "type_ref": "SQ_DED_CNT" 3712 }, 3713 { 3714 "chips": ["gfx6"], 3715 "map": {"at": 36492, "to": "mm"}, 3716 "name": "SQ_DED_INFO", 3717 "type_ref": "SQ_DED_INFO" 3718 }, 3719 { 3720 "chips": ["gfx6"], 3721 "map": {"at": 36608, "to": "mm"}, 3722 "name": "SQ_BUF_RSRC_WORD0", 3723 "type_ref": "SQ_BUF_RSRC_WORD0" 3724 }, 3725 { 3726 "chips": ["gfx6"], 3727 "map": {"at": 36612, "to": "mm"}, 3728 "name": "SQ_BUF_RSRC_WORD1", 3729 "type_ref": "SQ_BUF_RSRC_WORD1" 3730 }, 3731 { 3732 "chips": ["gfx6"], 3733 "map": {"at": 36616, "to": "mm"}, 3734 "name": "SQ_BUF_RSRC_WORD2", 3735 "type_ref": "SQ_BUF_RSRC_WORD2" 3736 }, 3737 { 3738 "chips": ["gfx6"], 3739 "map": {"at": 36620, "to": "mm"}, 3740 "name": "SQ_BUF_RSRC_WORD3", 3741 "type_ref": "SQ_BUF_RSRC_WORD3" 3742 }, 3743 { 3744 "chips": ["gfx6"], 3745 "map": {"at": 36624, "to": "mm"}, 3746 "name": "SQ_IMG_RSRC_WORD0", 3747 "type_ref": "SQ_BUF_RSRC_WORD0" 3748 }, 3749 { 3750 "chips": ["gfx6"], 3751 "map": {"at": 36628, "to": "mm"}, 3752 "name": "SQ_IMG_RSRC_WORD1", 3753 "type_ref": "SQ_IMG_RSRC_WORD1" 3754 }, 3755 { 3756 "chips": ["gfx6"], 3757 "map": {"at": 36632, "to": "mm"}, 3758 "name": "SQ_IMG_RSRC_WORD2", 3759 "type_ref": "SQ_IMG_RSRC_WORD2" 3760 }, 3761 { 3762 "chips": ["gfx6"], 3763 "map": {"at": 36636, "to": "mm"}, 3764 "name": "SQ_IMG_RSRC_WORD3", 3765 "type_ref": "SQ_IMG_RSRC_WORD3" 3766 }, 3767 { 3768 "chips": ["gfx6"], 3769 "map": {"at": 36640, "to": "mm"}, 3770 "name": "SQ_IMG_RSRC_WORD4", 3771 "type_ref": "SQ_IMG_RSRC_WORD4" 3772 }, 3773 { 3774 "chips": ["gfx6"], 3775 "map": {"at": 36644, "to": "mm"}, 3776 "name": "SQ_IMG_RSRC_WORD5", 3777 "type_ref": "SQ_IMG_RSRC_WORD5" 3778 }, 3779 { 3780 "chips": ["gfx6"], 3781 "map": {"at": 36648, "to": "mm"}, 3782 "name": "SQ_IMG_RSRC_WORD6", 3783 "type_ref": "SQ_IMG_RSRC_WORD6" 3784 }, 3785 { 3786 "chips": ["gfx6"], 3787 "map": {"at": 36652, "to": "mm"}, 3788 "name": "SQ_IMG_RSRC_WORD7", 3789 "type_ref": "SQ_IMG_RSRC_WORD7" 3790 }, 3791 { 3792 "chips": ["gfx6"], 3793 "map": {"at": 36656, "to": "mm"}, 3794 "name": "SQ_IMG_SAMP_WORD0", 3795 "type_ref": "SQ_IMG_SAMP_WORD0" 3796 }, 3797 { 3798 "chips": ["gfx6"], 3799 "map": {"at": 36660, "to": "mm"}, 3800 "name": "SQ_IMG_SAMP_WORD1", 3801 "type_ref": "SQ_IMG_SAMP_WORD1" 3802 }, 3803 { 3804 "chips": ["gfx6"], 3805 "map": {"at": 36664, "to": "mm"}, 3806 "name": "SQ_IMG_SAMP_WORD2", 3807 "type_ref": "SQ_IMG_SAMP_WORD2" 3808 }, 3809 { 3810 "chips": ["gfx6"], 3811 "map": {"at": 36668, "to": "mm"}, 3812 "name": "SQ_IMG_SAMP_WORD3", 3813 "type_ref": "SQ_IMG_SAMP_WORD3" 3814 }, 3815 { 3816 "chips": ["gfx6"], 3817 "map": {"at": 37120, "to": "mm"}, 3818 "name": "SPI_CONFIG_CNTL", 3819 "type_ref": "SPI_CONFIG_CNTL" 3820 }, 3821 { 3822 "chips": ["gfx6"], 3823 "map": {"at": 38156, "to": "mm"}, 3824 "name": "TA_CS_BC_BASE_ADDR", 3825 "type_ref": "TA_BC_BASE_ADDR" 3826 }, 3827 { 3828 "chips": ["gfx6"], 3829 "map": {"at": 39160, "to": "mm"}, 3830 "name": "GB_ADDR_CONFIG", 3831 "type_ref": "GB_ADDR_CONFIG" 3832 }, 3833 { 3834 "chips": ["gfx6"], 3835 "map": {"at": 39184, "to": "mm"}, 3836 "name": "GB_TILE_MODE0", 3837 "type_ref": "GB_TILE_MODE0" 3838 }, 3839 { 3840 "chips": ["gfx6"], 3841 "map": {"at": 39188, "to": "mm"}, 3842 "name": "GB_TILE_MODE1", 3843 "type_ref": "GB_TILE_MODE10" 3844 }, 3845 { 3846 "chips": ["gfx6"], 3847 "map": {"at": 39192, "to": "mm"}, 3848 "name": "GB_TILE_MODE2", 3849 "type_ref": "GB_TILE_MODE10" 3850 }, 3851 { 3852 "chips": ["gfx6"], 3853 "map": {"at": 39196, "to": "mm"}, 3854 "name": "GB_TILE_MODE3", 3855 "type_ref": "GB_TILE_MODE10" 3856 }, 3857 { 3858 "chips": ["gfx6"], 3859 "map": {"at": 39200, "to": "mm"}, 3860 "name": "GB_TILE_MODE4", 3861 "type_ref": "GB_TILE_MODE10" 3862 }, 3863 { 3864 "chips": ["gfx6"], 3865 "map": {"at": 39204, "to": "mm"}, 3866 "name": "GB_TILE_MODE5", 3867 "type_ref": "GB_TILE_MODE10" 3868 }, 3869 { 3870 "chips": ["gfx6"], 3871 "map": {"at": 39208, "to": "mm"}, 3872 "name": "GB_TILE_MODE6", 3873 "type_ref": "GB_TILE_MODE10" 3874 }, 3875 { 3876 "chips": ["gfx6"], 3877 "map": {"at": 39212, "to": "mm"}, 3878 "name": "GB_TILE_MODE7", 3879 "type_ref": "GB_TILE_MODE10" 3880 }, 3881 { 3882 "chips": ["gfx6"], 3883 "map": {"at": 39216, "to": "mm"}, 3884 "name": "GB_TILE_MODE8", 3885 "type_ref": "GB_TILE_MODE10" 3886 }, 3887 { 3888 "chips": ["gfx6"], 3889 "map": {"at": 39220, "to": "mm"}, 3890 "name": "GB_TILE_MODE9", 3891 "type_ref": "GB_TILE_MODE10" 3892 }, 3893 { 3894 "chips": ["gfx6"], 3895 "map": {"at": 39224, "to": "mm"}, 3896 "name": "GB_TILE_MODE10", 3897 "type_ref": "GB_TILE_MODE10" 3898 }, 3899 { 3900 "chips": ["gfx6"], 3901 "map": {"at": 39228, "to": "mm"}, 3902 "name": "GB_TILE_MODE11", 3903 "type_ref": "GB_TILE_MODE10" 3904 }, 3905 { 3906 "chips": ["gfx6"], 3907 "map": {"at": 39232, "to": "mm"}, 3908 "name": "GB_TILE_MODE12", 3909 "type_ref": "GB_TILE_MODE10" 3910 }, 3911 { 3912 "chips": ["gfx6"], 3913 "map": {"at": 39236, "to": "mm"}, 3914 "name": "GB_TILE_MODE13", 3915 "type_ref": "GB_TILE_MODE10" 3916 }, 3917 { 3918 "chips": ["gfx6"], 3919 "map": {"at": 39240, "to": "mm"}, 3920 "name": "GB_TILE_MODE14", 3921 "type_ref": "GB_TILE_MODE10" 3922 }, 3923 { 3924 "chips": ["gfx6"], 3925 "map": {"at": 39244, "to": "mm"}, 3926 "name": "GB_TILE_MODE15", 3927 "type_ref": "GB_TILE_MODE10" 3928 }, 3929 { 3930 "chips": ["gfx6"], 3931 "map": {"at": 39248, "to": "mm"}, 3932 "name": "GB_TILE_MODE16", 3933 "type_ref": "GB_TILE_MODE10" 3934 }, 3935 { 3936 "chips": ["gfx6"], 3937 "map": {"at": 39252, "to": "mm"}, 3938 "name": "GB_TILE_MODE17", 3939 "type_ref": "GB_TILE_MODE10" 3940 }, 3941 { 3942 "chips": ["gfx6"], 3943 "map": {"at": 39256, "to": "mm"}, 3944 "name": "GB_TILE_MODE18", 3945 "type_ref": "GB_TILE_MODE10" 3946 }, 3947 { 3948 "chips": ["gfx6"], 3949 "map": {"at": 39260, "to": "mm"}, 3950 "name": "GB_TILE_MODE19", 3951 "type_ref": "GB_TILE_MODE10" 3952 }, 3953 { 3954 "chips": ["gfx6"], 3955 "map": {"at": 39264, "to": "mm"}, 3956 "name": "GB_TILE_MODE20", 3957 "type_ref": "GB_TILE_MODE10" 3958 }, 3959 { 3960 "chips": ["gfx6"], 3961 "map": {"at": 39268, "to": "mm"}, 3962 "name": "GB_TILE_MODE21", 3963 "type_ref": "GB_TILE_MODE10" 3964 }, 3965 { 3966 "chips": ["gfx6"], 3967 "map": {"at": 39272, "to": "mm"}, 3968 "name": "GB_TILE_MODE22", 3969 "type_ref": "GB_TILE_MODE10" 3970 }, 3971 { 3972 "chips": ["gfx6"], 3973 "map": {"at": 39276, "to": "mm"}, 3974 "name": "GB_TILE_MODE23", 3975 "type_ref": "GB_TILE_MODE10" 3976 }, 3977 { 3978 "chips": ["gfx6"], 3979 "map": {"at": 39280, "to": "mm"}, 3980 "name": "GB_TILE_MODE24", 3981 "type_ref": "GB_TILE_MODE10" 3982 }, 3983 { 3984 "chips": ["gfx6"], 3985 "map": {"at": 39284, "to": "mm"}, 3986 "name": "GB_TILE_MODE25", 3987 "type_ref": "GB_TILE_MODE10" 3988 }, 3989 { 3990 "chips": ["gfx6"], 3991 "map": {"at": 39288, "to": "mm"}, 3992 "name": "GB_TILE_MODE26", 3993 "type_ref": "GB_TILE_MODE10" 3994 }, 3995 { 3996 "chips": ["gfx6"], 3997 "map": {"at": 39292, "to": "mm"}, 3998 "name": "GB_TILE_MODE27", 3999 "type_ref": "GB_TILE_MODE10" 4000 }, 4001 { 4002 "chips": ["gfx6"], 4003 "map": {"at": 39296, "to": "mm"}, 4004 "name": "GB_TILE_MODE28", 4005 "type_ref": "GB_TILE_MODE10" 4006 }, 4007 { 4008 "chips": ["gfx6"], 4009 "map": {"at": 39300, "to": "mm"}, 4010 "name": "GB_TILE_MODE29", 4011 "type_ref": "GB_TILE_MODE10" 4012 }, 4013 { 4014 "chips": ["gfx6"], 4015 "map": {"at": 39304, "to": "mm"}, 4016 "name": "GB_TILE_MODE30", 4017 "type_ref": "GB_TILE_MODE10" 4018 }, 4019 { 4020 "chips": ["gfx6"], 4021 "map": {"at": 39308, "to": "mm"}, 4022 "name": "GB_TILE_MODE31", 4023 "type_ref": "GB_TILE_MODE10" 4024 }, 4025 { 4026 "chips": ["gfx6"], 4027 "map": {"at": 45056, "to": "mm"}, 4028 "name": "SPI_SHADER_TBA_LO_PS", 4029 "type_ref": "SPI_SHADER_PGM_LO_ES" 4030 }, 4031 { 4032 "chips": ["gfx6"], 4033 "map": {"at": 45060, "to": "mm"}, 4034 "name": "SPI_SHADER_TBA_HI_PS", 4035 "type_ref": "SPI_SHADER_PGM_HI_ES" 4036 }, 4037 { 4038 "chips": ["gfx6"], 4039 "map": {"at": 45064, "to": "mm"}, 4040 "name": "SPI_SHADER_TMA_LO_PS", 4041 "type_ref": "SPI_SHADER_PGM_LO_ES" 4042 }, 4043 { 4044 "chips": ["gfx6"], 4045 "map": {"at": 45068, "to": "mm"}, 4046 "name": "SPI_SHADER_TMA_HI_PS", 4047 "type_ref": "SPI_SHADER_PGM_HI_ES" 4048 }, 4049 { 4050 "chips": ["gfx6"], 4051 "map": {"at": 45088, "to": "mm"}, 4052 "name": "SPI_SHADER_PGM_LO_PS", 4053 "type_ref": "SPI_SHADER_PGM_LO_ES" 4054 }, 4055 { 4056 "chips": ["gfx6"], 4057 "map": {"at": 45092, "to": "mm"}, 4058 "name": "SPI_SHADER_PGM_HI_PS", 4059 "type_ref": "SPI_SHADER_PGM_HI_ES" 4060 }, 4061 { 4062 "chips": ["gfx6"], 4063 "map": {"at": 45096, "to": "mm"}, 4064 "name": "SPI_SHADER_PGM_RSRC1_PS", 4065 "type_ref": "SPI_SHADER_PGM_RSRC1_PS" 4066 }, 4067 { 4068 "chips": ["gfx6"], 4069 "map": {"at": 45100, "to": "mm"}, 4070 "name": "SPI_SHADER_PGM_RSRC2_PS", 4071 "type_ref": "SPI_SHADER_PGM_RSRC2_PS" 4072 }, 4073 { 4074 "chips": ["gfx6"], 4075 "map": {"at": 45104, "to": "mm"}, 4076 "name": "SPI_SHADER_USER_DATA_PS_0", 4077 "type_ref": "SQ_WAVE_TTMP0" 4078 }, 4079 { 4080 "chips": ["gfx6"], 4081 "map": {"at": 45108, "to": "mm"}, 4082 "name": "SPI_SHADER_USER_DATA_PS_1", 4083 "type_ref": "SQ_WAVE_TTMP0" 4084 }, 4085 { 4086 "chips": ["gfx6"], 4087 "map": {"at": 45112, "to": "mm"}, 4088 "name": "SPI_SHADER_USER_DATA_PS_2", 4089 "type_ref": "SQ_WAVE_TTMP0" 4090 }, 4091 { 4092 "chips": ["gfx6"], 4093 "map": {"at": 45116, "to": "mm"}, 4094 "name": "SPI_SHADER_USER_DATA_PS_3", 4095 "type_ref": "SQ_WAVE_TTMP0" 4096 }, 4097 { 4098 "chips": ["gfx6"], 4099 "map": {"at": 45120, "to": "mm"}, 4100 "name": "SPI_SHADER_USER_DATA_PS_4", 4101 "type_ref": "SQ_WAVE_TTMP0" 4102 }, 4103 { 4104 "chips": ["gfx6"], 4105 "map": {"at": 45124, "to": "mm"}, 4106 "name": "SPI_SHADER_USER_DATA_PS_5", 4107 "type_ref": "SQ_WAVE_TTMP0" 4108 }, 4109 { 4110 "chips": ["gfx6"], 4111 "map": {"at": 45128, "to": "mm"}, 4112 "name": "SPI_SHADER_USER_DATA_PS_6", 4113 "type_ref": "SQ_WAVE_TTMP0" 4114 }, 4115 { 4116 "chips": ["gfx6"], 4117 "map": {"at": 45132, "to": "mm"}, 4118 "name": "SPI_SHADER_USER_DATA_PS_7", 4119 "type_ref": "SQ_WAVE_TTMP0" 4120 }, 4121 { 4122 "chips": ["gfx6"], 4123 "map": {"at": 45136, "to": "mm"}, 4124 "name": "SPI_SHADER_USER_DATA_PS_8", 4125 "type_ref": "SQ_WAVE_TTMP0" 4126 }, 4127 { 4128 "chips": ["gfx6"], 4129 "map": {"at": 45140, "to": "mm"}, 4130 "name": "SPI_SHADER_USER_DATA_PS_9", 4131 "type_ref": "SQ_WAVE_TTMP0" 4132 }, 4133 { 4134 "chips": ["gfx6"], 4135 "map": {"at": 45144, "to": "mm"}, 4136 "name": "SPI_SHADER_USER_DATA_PS_10", 4137 "type_ref": "SQ_WAVE_TTMP0" 4138 }, 4139 { 4140 "chips": ["gfx6"], 4141 "map": {"at": 45148, "to": "mm"}, 4142 "name": "SPI_SHADER_USER_DATA_PS_11", 4143 "type_ref": "SQ_WAVE_TTMP0" 4144 }, 4145 { 4146 "chips": ["gfx6"], 4147 "map": {"at": 45152, "to": "mm"}, 4148 "name": "SPI_SHADER_USER_DATA_PS_12", 4149 "type_ref": "SQ_WAVE_TTMP0" 4150 }, 4151 { 4152 "chips": ["gfx6"], 4153 "map": {"at": 45156, "to": "mm"}, 4154 "name": "SPI_SHADER_USER_DATA_PS_13", 4155 "type_ref": "SQ_WAVE_TTMP0" 4156 }, 4157 { 4158 "chips": ["gfx6"], 4159 "map": {"at": 45160, "to": "mm"}, 4160 "name": "SPI_SHADER_USER_DATA_PS_14", 4161 "type_ref": "SQ_WAVE_TTMP0" 4162 }, 4163 { 4164 "chips": ["gfx6"], 4165 "map": {"at": 45164, "to": "mm"}, 4166 "name": "SPI_SHADER_USER_DATA_PS_15", 4167 "type_ref": "SQ_WAVE_TTMP0" 4168 }, 4169 { 4170 "chips": ["gfx6"], 4171 "map": {"at": 45312, "to": "mm"}, 4172 "name": "SPI_SHADER_TBA_LO_VS", 4173 "type_ref": "SPI_SHADER_PGM_LO_ES" 4174 }, 4175 { 4176 "chips": ["gfx6"], 4177 "map": {"at": 45316, "to": "mm"}, 4178 "name": "SPI_SHADER_TBA_HI_VS", 4179 "type_ref": "SPI_SHADER_PGM_HI_ES" 4180 }, 4181 { 4182 "chips": ["gfx6"], 4183 "map": {"at": 45320, "to": "mm"}, 4184 "name": "SPI_SHADER_TMA_LO_VS", 4185 "type_ref": "SPI_SHADER_PGM_LO_ES" 4186 }, 4187 { 4188 "chips": ["gfx6"], 4189 "map": {"at": 45324, "to": "mm"}, 4190 "name": "SPI_SHADER_TMA_HI_VS", 4191 "type_ref": "SPI_SHADER_PGM_HI_ES" 4192 }, 4193 { 4194 "chips": ["gfx6"], 4195 "map": {"at": 45344, "to": "mm"}, 4196 "name": "SPI_SHADER_PGM_LO_VS", 4197 "type_ref": "SPI_SHADER_PGM_LO_ES" 4198 }, 4199 { 4200 "chips": ["gfx6"], 4201 "map": {"at": 45348, "to": "mm"}, 4202 "name": "SPI_SHADER_PGM_HI_VS", 4203 "type_ref": "SPI_SHADER_PGM_HI_ES" 4204 }, 4205 { 4206 "chips": ["gfx6"], 4207 "map": {"at": 45352, "to": "mm"}, 4208 "name": "SPI_SHADER_PGM_RSRC1_VS", 4209 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 4210 }, 4211 { 4212 "chips": ["gfx6"], 4213 "map": {"at": 45356, "to": "mm"}, 4214 "name": "SPI_SHADER_PGM_RSRC2_VS", 4215 "type_ref": "SPI_SHADER_PGM_RSRC2_VS" 4216 }, 4217 { 4218 "chips": ["gfx6"], 4219 "map": {"at": 45360, "to": "mm"}, 4220 "name": "SPI_SHADER_USER_DATA_VS_0", 4221 "type_ref": "SQ_WAVE_TTMP0" 4222 }, 4223 { 4224 "chips": ["gfx6"], 4225 "map": {"at": 45364, "to": "mm"}, 4226 "name": "SPI_SHADER_USER_DATA_VS_1", 4227 "type_ref": "SQ_WAVE_TTMP0" 4228 }, 4229 { 4230 "chips": ["gfx6"], 4231 "map": {"at": 45368, "to": "mm"}, 4232 "name": "SPI_SHADER_USER_DATA_VS_2", 4233 "type_ref": "SQ_WAVE_TTMP0" 4234 }, 4235 { 4236 "chips": ["gfx6"], 4237 "map": {"at": 45372, "to": "mm"}, 4238 "name": "SPI_SHADER_USER_DATA_VS_3", 4239 "type_ref": "SQ_WAVE_TTMP0" 4240 }, 4241 { 4242 "chips": ["gfx6"], 4243 "map": {"at": 45376, "to": "mm"}, 4244 "name": "SPI_SHADER_USER_DATA_VS_4", 4245 "type_ref": "SQ_WAVE_TTMP0" 4246 }, 4247 { 4248 "chips": ["gfx6"], 4249 "map": {"at": 45380, "to": "mm"}, 4250 "name": "SPI_SHADER_USER_DATA_VS_5", 4251 "type_ref": "SQ_WAVE_TTMP0" 4252 }, 4253 { 4254 "chips": ["gfx6"], 4255 "map": {"at": 45384, "to": "mm"}, 4256 "name": "SPI_SHADER_USER_DATA_VS_6", 4257 "type_ref": "SQ_WAVE_TTMP0" 4258 }, 4259 { 4260 "chips": ["gfx6"], 4261 "map": {"at": 45388, "to": "mm"}, 4262 "name": "SPI_SHADER_USER_DATA_VS_7", 4263 "type_ref": "SQ_WAVE_TTMP0" 4264 }, 4265 { 4266 "chips": ["gfx6"], 4267 "map": {"at": 45392, "to": "mm"}, 4268 "name": "SPI_SHADER_USER_DATA_VS_8", 4269 "type_ref": "SQ_WAVE_TTMP0" 4270 }, 4271 { 4272 "chips": ["gfx6"], 4273 "map": {"at": 45396, "to": "mm"}, 4274 "name": "SPI_SHADER_USER_DATA_VS_9", 4275 "type_ref": "SQ_WAVE_TTMP0" 4276 }, 4277 { 4278 "chips": ["gfx6"], 4279 "map": {"at": 45400, "to": "mm"}, 4280 "name": "SPI_SHADER_USER_DATA_VS_10", 4281 "type_ref": "SQ_WAVE_TTMP0" 4282 }, 4283 { 4284 "chips": ["gfx6"], 4285 "map": {"at": 45404, "to": "mm"}, 4286 "name": "SPI_SHADER_USER_DATA_VS_11", 4287 "type_ref": "SQ_WAVE_TTMP0" 4288 }, 4289 { 4290 "chips": ["gfx6"], 4291 "map": {"at": 45408, "to": "mm"}, 4292 "name": "SPI_SHADER_USER_DATA_VS_12", 4293 "type_ref": "SQ_WAVE_TTMP0" 4294 }, 4295 { 4296 "chips": ["gfx6"], 4297 "map": {"at": 45412, "to": "mm"}, 4298 "name": "SPI_SHADER_USER_DATA_VS_13", 4299 "type_ref": "SQ_WAVE_TTMP0" 4300 }, 4301 { 4302 "chips": ["gfx6"], 4303 "map": {"at": 45416, "to": "mm"}, 4304 "name": "SPI_SHADER_USER_DATA_VS_14", 4305 "type_ref": "SQ_WAVE_TTMP0" 4306 }, 4307 { 4308 "chips": ["gfx6"], 4309 "map": {"at": 45420, "to": "mm"}, 4310 "name": "SPI_SHADER_USER_DATA_VS_15", 4311 "type_ref": "SQ_WAVE_TTMP0" 4312 }, 4313 { 4314 "chips": ["gfx6"], 4315 "map": {"at": 45568, "to": "mm"}, 4316 "name": "SPI_SHADER_TBA_LO_GS", 4317 "type_ref": "SPI_SHADER_PGM_LO_ES" 4318 }, 4319 { 4320 "chips": ["gfx6"], 4321 "map": {"at": 45572, "to": "mm"}, 4322 "name": "SPI_SHADER_TBA_HI_GS", 4323 "type_ref": "SPI_SHADER_PGM_HI_ES" 4324 }, 4325 { 4326 "chips": ["gfx6"], 4327 "map": {"at": 45576, "to": "mm"}, 4328 "name": "SPI_SHADER_TMA_LO_GS", 4329 "type_ref": "SPI_SHADER_PGM_LO_ES" 4330 }, 4331 { 4332 "chips": ["gfx6"], 4333 "map": {"at": 45580, "to": "mm"}, 4334 "name": "SPI_SHADER_TMA_HI_GS", 4335 "type_ref": "SPI_SHADER_PGM_HI_ES" 4336 }, 4337 { 4338 "chips": ["gfx6"], 4339 "map": {"at": 45600, "to": "mm"}, 4340 "name": "SPI_SHADER_PGM_LO_GS", 4341 "type_ref": "SPI_SHADER_PGM_LO_ES" 4342 }, 4343 { 4344 "chips": ["gfx6"], 4345 "map": {"at": 45604, "to": "mm"}, 4346 "name": "SPI_SHADER_PGM_HI_GS", 4347 "type_ref": "SPI_SHADER_PGM_HI_ES" 4348 }, 4349 { 4350 "chips": ["gfx6"], 4351 "map": {"at": 45608, "to": "mm"}, 4352 "name": "SPI_SHADER_PGM_RSRC1_GS", 4353 "type_ref": "SPI_SHADER_PGM_RSRC1_GS" 4354 }, 4355 { 4356 "chips": ["gfx6"], 4357 "map": {"at": 45612, "to": "mm"}, 4358 "name": "SPI_SHADER_PGM_RSRC2_GS", 4359 "type_ref": "SPI_SHADER_PGM_RSRC2_GS" 4360 }, 4361 { 4362 "chips": ["gfx6"], 4363 "map": {"at": 45616, "to": "mm"}, 4364 "name": "SPI_SHADER_USER_DATA_GS_0", 4365 "type_ref": "SQ_WAVE_TTMP0" 4366 }, 4367 { 4368 "chips": ["gfx6"], 4369 "map": {"at": 45620, "to": "mm"}, 4370 "name": "SPI_SHADER_USER_DATA_GS_1", 4371 "type_ref": "SQ_WAVE_TTMP0" 4372 }, 4373 { 4374 "chips": ["gfx6"], 4375 "map": {"at": 45624, "to": "mm"}, 4376 "name": "SPI_SHADER_USER_DATA_GS_2", 4377 "type_ref": "SQ_WAVE_TTMP0" 4378 }, 4379 { 4380 "chips": ["gfx6"], 4381 "map": {"at": 45628, "to": "mm"}, 4382 "name": "SPI_SHADER_USER_DATA_GS_3", 4383 "type_ref": "SQ_WAVE_TTMP0" 4384 }, 4385 { 4386 "chips": ["gfx6"], 4387 "map": {"at": 45632, "to": "mm"}, 4388 "name": "SPI_SHADER_USER_DATA_GS_4", 4389 "type_ref": "SQ_WAVE_TTMP0" 4390 }, 4391 { 4392 "chips": ["gfx6"], 4393 "map": {"at": 45636, "to": "mm"}, 4394 "name": "SPI_SHADER_USER_DATA_GS_5", 4395 "type_ref": "SQ_WAVE_TTMP0" 4396 }, 4397 { 4398 "chips": ["gfx6"], 4399 "map": {"at": 45640, "to": "mm"}, 4400 "name": "SPI_SHADER_USER_DATA_GS_6", 4401 "type_ref": "SQ_WAVE_TTMP0" 4402 }, 4403 { 4404 "chips": ["gfx6"], 4405 "map": {"at": 45644, "to": "mm"}, 4406 "name": "SPI_SHADER_USER_DATA_GS_7", 4407 "type_ref": "SQ_WAVE_TTMP0" 4408 }, 4409 { 4410 "chips": ["gfx6"], 4411 "map": {"at": 45648, "to": "mm"}, 4412 "name": "SPI_SHADER_USER_DATA_GS_8", 4413 "type_ref": "SQ_WAVE_TTMP0" 4414 }, 4415 { 4416 "chips": ["gfx6"], 4417 "map": {"at": 45652, "to": "mm"}, 4418 "name": "SPI_SHADER_USER_DATA_GS_9", 4419 "type_ref": "SQ_WAVE_TTMP0" 4420 }, 4421 { 4422 "chips": ["gfx6"], 4423 "map": {"at": 45656, "to": "mm"}, 4424 "name": "SPI_SHADER_USER_DATA_GS_10", 4425 "type_ref": "SQ_WAVE_TTMP0" 4426 }, 4427 { 4428 "chips": ["gfx6"], 4429 "map": {"at": 45660, "to": "mm"}, 4430 "name": "SPI_SHADER_USER_DATA_GS_11", 4431 "type_ref": "SQ_WAVE_TTMP0" 4432 }, 4433 { 4434 "chips": ["gfx6"], 4435 "map": {"at": 45664, "to": "mm"}, 4436 "name": "SPI_SHADER_USER_DATA_GS_12", 4437 "type_ref": "SQ_WAVE_TTMP0" 4438 }, 4439 { 4440 "chips": ["gfx6"], 4441 "map": {"at": 45668, "to": "mm"}, 4442 "name": "SPI_SHADER_USER_DATA_GS_13", 4443 "type_ref": "SQ_WAVE_TTMP0" 4444 }, 4445 { 4446 "chips": ["gfx6"], 4447 "map": {"at": 45672, "to": "mm"}, 4448 "name": "SPI_SHADER_USER_DATA_GS_14", 4449 "type_ref": "SQ_WAVE_TTMP0" 4450 }, 4451 { 4452 "chips": ["gfx6"], 4453 "map": {"at": 45676, "to": "mm"}, 4454 "name": "SPI_SHADER_USER_DATA_GS_15", 4455 "type_ref": "SQ_WAVE_TTMP0" 4456 }, 4457 { 4458 "chips": ["gfx6"], 4459 "map": {"at": 45824, "to": "mm"}, 4460 "name": "SPI_SHADER_TBA_LO_ES", 4461 "type_ref": "SPI_SHADER_PGM_LO_ES" 4462 }, 4463 { 4464 "chips": ["gfx6"], 4465 "map": {"at": 45828, "to": "mm"}, 4466 "name": "SPI_SHADER_TBA_HI_ES", 4467 "type_ref": "SPI_SHADER_PGM_HI_ES" 4468 }, 4469 { 4470 "chips": ["gfx6"], 4471 "map": {"at": 45832, "to": "mm"}, 4472 "name": "SPI_SHADER_TMA_LO_ES", 4473 "type_ref": "SPI_SHADER_PGM_LO_ES" 4474 }, 4475 { 4476 "chips": ["gfx6"], 4477 "map": {"at": 45836, "to": "mm"}, 4478 "name": "SPI_SHADER_TMA_HI_ES", 4479 "type_ref": "SPI_SHADER_PGM_HI_ES" 4480 }, 4481 { 4482 "chips": ["gfx6"], 4483 "map": {"at": 45856, "to": "mm"}, 4484 "name": "SPI_SHADER_PGM_LO_ES", 4485 "type_ref": "SPI_SHADER_PGM_LO_ES" 4486 }, 4487 { 4488 "chips": ["gfx6"], 4489 "map": {"at": 45860, "to": "mm"}, 4490 "name": "SPI_SHADER_PGM_HI_ES", 4491 "type_ref": "SPI_SHADER_PGM_HI_ES" 4492 }, 4493 { 4494 "chips": ["gfx6"], 4495 "map": {"at": 45864, "to": "mm"}, 4496 "name": "SPI_SHADER_PGM_RSRC1_ES", 4497 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 4498 }, 4499 { 4500 "chips": ["gfx6"], 4501 "map": {"at": 45868, "to": "mm"}, 4502 "name": "SPI_SHADER_PGM_RSRC2_ES", 4503 "type_ref": "SPI_SHADER_PGM_RSRC2_ES" 4504 }, 4505 { 4506 "chips": ["gfx6"], 4507 "map": {"at": 45872, "to": "mm"}, 4508 "name": "SPI_SHADER_USER_DATA_ES_0", 4509 "type_ref": "SQ_WAVE_TTMP0" 4510 }, 4511 { 4512 "chips": ["gfx6"], 4513 "map": {"at": 45876, "to": "mm"}, 4514 "name": "SPI_SHADER_USER_DATA_ES_1", 4515 "type_ref": "SQ_WAVE_TTMP0" 4516 }, 4517 { 4518 "chips": ["gfx6"], 4519 "map": {"at": 45880, "to": "mm"}, 4520 "name": "SPI_SHADER_USER_DATA_ES_2", 4521 "type_ref": "SQ_WAVE_TTMP0" 4522 }, 4523 { 4524 "chips": ["gfx6"], 4525 "map": {"at": 45884, "to": "mm"}, 4526 "name": "SPI_SHADER_USER_DATA_ES_3", 4527 "type_ref": "SQ_WAVE_TTMP0" 4528 }, 4529 { 4530 "chips": ["gfx6"], 4531 "map": {"at": 45888, "to": "mm"}, 4532 "name": "SPI_SHADER_USER_DATA_ES_4", 4533 "type_ref": "SQ_WAVE_TTMP0" 4534 }, 4535 { 4536 "chips": ["gfx6"], 4537 "map": {"at": 45892, "to": "mm"}, 4538 "name": "SPI_SHADER_USER_DATA_ES_5", 4539 "type_ref": "SQ_WAVE_TTMP0" 4540 }, 4541 { 4542 "chips": ["gfx6"], 4543 "map": {"at": 45896, "to": "mm"}, 4544 "name": "SPI_SHADER_USER_DATA_ES_6", 4545 "type_ref": "SQ_WAVE_TTMP0" 4546 }, 4547 { 4548 "chips": ["gfx6"], 4549 "map": {"at": 45900, "to": "mm"}, 4550 "name": "SPI_SHADER_USER_DATA_ES_7", 4551 "type_ref": "SQ_WAVE_TTMP0" 4552 }, 4553 { 4554 "chips": ["gfx6"], 4555 "map": {"at": 45904, "to": "mm"}, 4556 "name": "SPI_SHADER_USER_DATA_ES_8", 4557 "type_ref": "SQ_WAVE_TTMP0" 4558 }, 4559 { 4560 "chips": ["gfx6"], 4561 "map": {"at": 45908, "to": "mm"}, 4562 "name": "SPI_SHADER_USER_DATA_ES_9", 4563 "type_ref": "SQ_WAVE_TTMP0" 4564 }, 4565 { 4566 "chips": ["gfx6"], 4567 "map": {"at": 45912, "to": "mm"}, 4568 "name": "SPI_SHADER_USER_DATA_ES_10", 4569 "type_ref": "SQ_WAVE_TTMP0" 4570 }, 4571 { 4572 "chips": ["gfx6"], 4573 "map": {"at": 45916, "to": "mm"}, 4574 "name": "SPI_SHADER_USER_DATA_ES_11", 4575 "type_ref": "SQ_WAVE_TTMP0" 4576 }, 4577 { 4578 "chips": ["gfx6"], 4579 "map": {"at": 45920, "to": "mm"}, 4580 "name": "SPI_SHADER_USER_DATA_ES_12", 4581 "type_ref": "SQ_WAVE_TTMP0" 4582 }, 4583 { 4584 "chips": ["gfx6"], 4585 "map": {"at": 45924, "to": "mm"}, 4586 "name": "SPI_SHADER_USER_DATA_ES_13", 4587 "type_ref": "SQ_WAVE_TTMP0" 4588 }, 4589 { 4590 "chips": ["gfx6"], 4591 "map": {"at": 45928, "to": "mm"}, 4592 "name": "SPI_SHADER_USER_DATA_ES_14", 4593 "type_ref": "SQ_WAVE_TTMP0" 4594 }, 4595 { 4596 "chips": ["gfx6"], 4597 "map": {"at": 45932, "to": "mm"}, 4598 "name": "SPI_SHADER_USER_DATA_ES_15", 4599 "type_ref": "SQ_WAVE_TTMP0" 4600 }, 4601 { 4602 "chips": ["gfx6"], 4603 "map": {"at": 46080, "to": "mm"}, 4604 "name": "SPI_SHADER_TBA_LO_HS", 4605 "type_ref": "SPI_SHADER_PGM_LO_ES" 4606 }, 4607 { 4608 "chips": ["gfx6"], 4609 "map": {"at": 46084, "to": "mm"}, 4610 "name": "SPI_SHADER_TBA_HI_HS", 4611 "type_ref": "SPI_SHADER_PGM_HI_ES" 4612 }, 4613 { 4614 "chips": ["gfx6"], 4615 "map": {"at": 46088, "to": "mm"}, 4616 "name": "SPI_SHADER_TMA_LO_HS", 4617 "type_ref": "SPI_SHADER_PGM_LO_ES" 4618 }, 4619 { 4620 "chips": ["gfx6"], 4621 "map": {"at": 46092, "to": "mm"}, 4622 "name": "SPI_SHADER_TMA_HI_HS", 4623 "type_ref": "SPI_SHADER_PGM_HI_ES" 4624 }, 4625 { 4626 "chips": ["gfx6"], 4627 "map": {"at": 46112, "to": "mm"}, 4628 "name": "SPI_SHADER_PGM_LO_HS", 4629 "type_ref": "SPI_SHADER_PGM_LO_ES" 4630 }, 4631 { 4632 "chips": ["gfx6"], 4633 "map": {"at": 46116, "to": "mm"}, 4634 "name": "SPI_SHADER_PGM_HI_HS", 4635 "type_ref": "SPI_SHADER_PGM_HI_ES" 4636 }, 4637 { 4638 "chips": ["gfx6"], 4639 "map": {"at": 46120, "to": "mm"}, 4640 "name": "SPI_SHADER_PGM_RSRC1_HS", 4641 "type_ref": "SPI_SHADER_PGM_RSRC1_HS" 4642 }, 4643 { 4644 "chips": ["gfx6"], 4645 "map": {"at": 46124, "to": "mm"}, 4646 "name": "SPI_SHADER_PGM_RSRC2_HS", 4647 "type_ref": "SPI_SHADER_PGM_RSRC2_HS" 4648 }, 4649 { 4650 "chips": ["gfx6"], 4651 "map": {"at": 46128, "to": "mm"}, 4652 "name": "SPI_SHADER_USER_DATA_HS_0", 4653 "type_ref": "SQ_WAVE_TTMP0" 4654 }, 4655 { 4656 "chips": ["gfx6"], 4657 "map": {"at": 46132, "to": "mm"}, 4658 "name": "SPI_SHADER_USER_DATA_HS_1", 4659 "type_ref": "SQ_WAVE_TTMP0" 4660 }, 4661 { 4662 "chips": ["gfx6"], 4663 "map": {"at": 46136, "to": "mm"}, 4664 "name": "SPI_SHADER_USER_DATA_HS_2", 4665 "type_ref": "SQ_WAVE_TTMP0" 4666 }, 4667 { 4668 "chips": ["gfx6"], 4669 "map": {"at": 46140, "to": "mm"}, 4670 "name": "SPI_SHADER_USER_DATA_HS_3", 4671 "type_ref": "SQ_WAVE_TTMP0" 4672 }, 4673 { 4674 "chips": ["gfx6"], 4675 "map": {"at": 46144, "to": "mm"}, 4676 "name": "SPI_SHADER_USER_DATA_HS_4", 4677 "type_ref": "SQ_WAVE_TTMP0" 4678 }, 4679 { 4680 "chips": ["gfx6"], 4681 "map": {"at": 46148, "to": "mm"}, 4682 "name": "SPI_SHADER_USER_DATA_HS_5", 4683 "type_ref": "SQ_WAVE_TTMP0" 4684 }, 4685 { 4686 "chips": ["gfx6"], 4687 "map": {"at": 46152, "to": "mm"}, 4688 "name": "SPI_SHADER_USER_DATA_HS_6", 4689 "type_ref": "SQ_WAVE_TTMP0" 4690 }, 4691 { 4692 "chips": ["gfx6"], 4693 "map": {"at": 46156, "to": "mm"}, 4694 "name": "SPI_SHADER_USER_DATA_HS_7", 4695 "type_ref": "SQ_WAVE_TTMP0" 4696 }, 4697 { 4698 "chips": ["gfx6"], 4699 "map": {"at": 46160, "to": "mm"}, 4700 "name": "SPI_SHADER_USER_DATA_HS_8", 4701 "type_ref": "SQ_WAVE_TTMP0" 4702 }, 4703 { 4704 "chips": ["gfx6"], 4705 "map": {"at": 46164, "to": "mm"}, 4706 "name": "SPI_SHADER_USER_DATA_HS_9", 4707 "type_ref": "SQ_WAVE_TTMP0" 4708 }, 4709 { 4710 "chips": ["gfx6"], 4711 "map": {"at": 46168, "to": "mm"}, 4712 "name": "SPI_SHADER_USER_DATA_HS_10", 4713 "type_ref": "SQ_WAVE_TTMP0" 4714 }, 4715 { 4716 "chips": ["gfx6"], 4717 "map": {"at": 46172, "to": "mm"}, 4718 "name": "SPI_SHADER_USER_DATA_HS_11", 4719 "type_ref": "SQ_WAVE_TTMP0" 4720 }, 4721 { 4722 "chips": ["gfx6"], 4723 "map": {"at": 46176, "to": "mm"}, 4724 "name": "SPI_SHADER_USER_DATA_HS_12", 4725 "type_ref": "SQ_WAVE_TTMP0" 4726 }, 4727 { 4728 "chips": ["gfx6"], 4729 "map": {"at": 46180, "to": "mm"}, 4730 "name": "SPI_SHADER_USER_DATA_HS_13", 4731 "type_ref": "SQ_WAVE_TTMP0" 4732 }, 4733 { 4734 "chips": ["gfx6"], 4735 "map": {"at": 46184, "to": "mm"}, 4736 "name": "SPI_SHADER_USER_DATA_HS_14", 4737 "type_ref": "SQ_WAVE_TTMP0" 4738 }, 4739 { 4740 "chips": ["gfx6"], 4741 "map": {"at": 46188, "to": "mm"}, 4742 "name": "SPI_SHADER_USER_DATA_HS_15", 4743 "type_ref": "SQ_WAVE_TTMP0" 4744 }, 4745 { 4746 "chips": ["gfx6"], 4747 "map": {"at": 46336, "to": "mm"}, 4748 "name": "SPI_SHADER_TBA_LO_LS", 4749 "type_ref": "SPI_SHADER_PGM_LO_ES" 4750 }, 4751 { 4752 "chips": ["gfx6"], 4753 "map": {"at": 46340, "to": "mm"}, 4754 "name": "SPI_SHADER_TBA_HI_LS", 4755 "type_ref": "SPI_SHADER_PGM_HI_ES" 4756 }, 4757 { 4758 "chips": ["gfx6"], 4759 "map": {"at": 46344, "to": "mm"}, 4760 "name": "SPI_SHADER_TMA_LO_LS", 4761 "type_ref": "SPI_SHADER_PGM_LO_ES" 4762 }, 4763 { 4764 "chips": ["gfx6"], 4765 "map": {"at": 46348, "to": "mm"}, 4766 "name": "SPI_SHADER_TMA_HI_LS", 4767 "type_ref": "SPI_SHADER_PGM_HI_ES" 4768 }, 4769 { 4770 "chips": ["gfx6"], 4771 "map": {"at": 46368, "to": "mm"}, 4772 "name": "SPI_SHADER_PGM_LO_LS", 4773 "type_ref": "SPI_SHADER_PGM_LO_ES" 4774 }, 4775 { 4776 "chips": ["gfx6"], 4777 "map": {"at": 46372, "to": "mm"}, 4778 "name": "SPI_SHADER_PGM_HI_LS", 4779 "type_ref": "SPI_SHADER_PGM_HI_ES" 4780 }, 4781 { 4782 "chips": ["gfx6"], 4783 "map": {"at": 46376, "to": "mm"}, 4784 "name": "SPI_SHADER_PGM_RSRC1_LS", 4785 "type_ref": "SPI_SHADER_PGM_RSRC1_LS" 4786 }, 4787 { 4788 "chips": ["gfx6"], 4789 "map": {"at": 46380, "to": "mm"}, 4790 "name": "SPI_SHADER_PGM_RSRC2_LS", 4791 "type_ref": "SPI_SHADER_PGM_RSRC2_LS" 4792 }, 4793 { 4794 "chips": ["gfx6"], 4795 "map": {"at": 46384, "to": "mm"}, 4796 "name": "SPI_SHADER_USER_DATA_LS_0", 4797 "type_ref": "SQ_WAVE_TTMP0" 4798 }, 4799 { 4800 "chips": ["gfx6"], 4801 "map": {"at": 46388, "to": "mm"}, 4802 "name": "SPI_SHADER_USER_DATA_LS_1", 4803 "type_ref": "SQ_WAVE_TTMP0" 4804 }, 4805 { 4806 "chips": ["gfx6"], 4807 "map": {"at": 46392, "to": "mm"}, 4808 "name": "SPI_SHADER_USER_DATA_LS_2", 4809 "type_ref": "SQ_WAVE_TTMP0" 4810 }, 4811 { 4812 "chips": ["gfx6"], 4813 "map": {"at": 46396, "to": "mm"}, 4814 "name": "SPI_SHADER_USER_DATA_LS_3", 4815 "type_ref": "SQ_WAVE_TTMP0" 4816 }, 4817 { 4818 "chips": ["gfx6"], 4819 "map": {"at": 46400, "to": "mm"}, 4820 "name": "SPI_SHADER_USER_DATA_LS_4", 4821 "type_ref": "SQ_WAVE_TTMP0" 4822 }, 4823 { 4824 "chips": ["gfx6"], 4825 "map": {"at": 46404, "to": "mm"}, 4826 "name": "SPI_SHADER_USER_DATA_LS_5", 4827 "type_ref": "SQ_WAVE_TTMP0" 4828 }, 4829 { 4830 "chips": ["gfx6"], 4831 "map": {"at": 46408, "to": "mm"}, 4832 "name": "SPI_SHADER_USER_DATA_LS_6", 4833 "type_ref": "SQ_WAVE_TTMP0" 4834 }, 4835 { 4836 "chips": ["gfx6"], 4837 "map": {"at": 46412, "to": "mm"}, 4838 "name": "SPI_SHADER_USER_DATA_LS_7", 4839 "type_ref": "SQ_WAVE_TTMP0" 4840 }, 4841 { 4842 "chips": ["gfx6"], 4843 "map": {"at": 46416, "to": "mm"}, 4844 "name": "SPI_SHADER_USER_DATA_LS_8", 4845 "type_ref": "SQ_WAVE_TTMP0" 4846 }, 4847 { 4848 "chips": ["gfx6"], 4849 "map": {"at": 46420, "to": "mm"}, 4850 "name": "SPI_SHADER_USER_DATA_LS_9", 4851 "type_ref": "SQ_WAVE_TTMP0" 4852 }, 4853 { 4854 "chips": ["gfx6"], 4855 "map": {"at": 46424, "to": "mm"}, 4856 "name": "SPI_SHADER_USER_DATA_LS_10", 4857 "type_ref": "SQ_WAVE_TTMP0" 4858 }, 4859 { 4860 "chips": ["gfx6"], 4861 "map": {"at": 46428, "to": "mm"}, 4862 "name": "SPI_SHADER_USER_DATA_LS_11", 4863 "type_ref": "SQ_WAVE_TTMP0" 4864 }, 4865 { 4866 "chips": ["gfx6"], 4867 "map": {"at": 46432, "to": "mm"}, 4868 "name": "SPI_SHADER_USER_DATA_LS_12", 4869 "type_ref": "SQ_WAVE_TTMP0" 4870 }, 4871 { 4872 "chips": ["gfx6"], 4873 "map": {"at": 46436, "to": "mm"}, 4874 "name": "SPI_SHADER_USER_DATA_LS_13", 4875 "type_ref": "SQ_WAVE_TTMP0" 4876 }, 4877 { 4878 "chips": ["gfx6"], 4879 "map": {"at": 46440, "to": "mm"}, 4880 "name": "SPI_SHADER_USER_DATA_LS_14", 4881 "type_ref": "SQ_WAVE_TTMP0" 4882 }, 4883 { 4884 "chips": ["gfx6"], 4885 "map": {"at": 46444, "to": "mm"}, 4886 "name": "SPI_SHADER_USER_DATA_LS_15", 4887 "type_ref": "SQ_WAVE_TTMP0" 4888 }, 4889 { 4890 "chips": ["gfx6"], 4891 "map": {"at": 47104, "to": "mm"}, 4892 "name": "COMPUTE_DISPATCH_INITIATOR", 4893 "type_ref": "COMPUTE_DISPATCH_INITIATOR" 4894 }, 4895 { 4896 "chips": ["gfx6"], 4897 "map": {"at": 47108, "to": "mm"}, 4898 "name": "COMPUTE_DIM_X", 4899 "type_ref": "COMPUTE_DIM_X" 4900 }, 4901 { 4902 "chips": ["gfx6"], 4903 "map": {"at": 47112, "to": "mm"}, 4904 "name": "COMPUTE_DIM_Y", 4905 "type_ref": "COMPUTE_DIM_X" 4906 }, 4907 { 4908 "chips": ["gfx6"], 4909 "map": {"at": 47116, "to": "mm"}, 4910 "name": "COMPUTE_DIM_Z", 4911 "type_ref": "COMPUTE_DIM_X" 4912 }, 4913 { 4914 "chips": ["gfx6"], 4915 "map": {"at": 47120, "to": "mm"}, 4916 "name": "COMPUTE_START_X", 4917 "type_ref": "COMPUTE_START_X" 4918 }, 4919 { 4920 "chips": ["gfx6"], 4921 "map": {"at": 47124, "to": "mm"}, 4922 "name": "COMPUTE_START_Y", 4923 "type_ref": "COMPUTE_START_X" 4924 }, 4925 { 4926 "chips": ["gfx6"], 4927 "map": {"at": 47128, "to": "mm"}, 4928 "name": "COMPUTE_START_Z", 4929 "type_ref": "COMPUTE_START_X" 4930 }, 4931 { 4932 "chips": ["gfx6"], 4933 "map": {"at": 47132, "to": "mm"}, 4934 "name": "COMPUTE_NUM_THREAD_X", 4935 "type_ref": "COMPUTE_NUM_THREAD_X" 4936 }, 4937 { 4938 "chips": ["gfx6"], 4939 "map": {"at": 47136, "to": "mm"}, 4940 "name": "COMPUTE_NUM_THREAD_Y", 4941 "type_ref": "COMPUTE_NUM_THREAD_X" 4942 }, 4943 { 4944 "chips": ["gfx6"], 4945 "map": {"at": 47140, "to": "mm"}, 4946 "name": "COMPUTE_NUM_THREAD_Z", 4947 "type_ref": "COMPUTE_NUM_THREAD_X" 4948 }, 4949 { 4950 "chips": ["gfx6"], 4951 "map": {"at": 47152, "to": "mm"}, 4952 "name": "COMPUTE_PGM_LO", 4953 "type_ref": "SQ_WAVE_TTMP0" 4954 }, 4955 { 4956 "chips": ["gfx6"], 4957 "map": {"at": 47156, "to": "mm"}, 4958 "name": "COMPUTE_PGM_HI", 4959 "type_ref": "COMPUTE_PGM_HI" 4960 }, 4961 { 4962 "chips": ["gfx6"], 4963 "map": {"at": 47160, "to": "mm"}, 4964 "name": "COMPUTE_TBA_LO", 4965 "type_ref": "SQ_WAVE_TTMP0" 4966 }, 4967 { 4968 "chips": ["gfx6"], 4969 "map": {"at": 47164, "to": "mm"}, 4970 "name": "COMPUTE_TBA_HI", 4971 "type_ref": "COMPUTE_TBA_HI" 4972 }, 4973 { 4974 "chips": ["gfx6"], 4975 "map": {"at": 47168, "to": "mm"}, 4976 "name": "COMPUTE_TMA_LO", 4977 "type_ref": "SQ_WAVE_TTMP0" 4978 }, 4979 { 4980 "chips": ["gfx6"], 4981 "map": {"at": 47172, "to": "mm"}, 4982 "name": "COMPUTE_TMA_HI", 4983 "type_ref": "COMPUTE_TBA_HI" 4984 }, 4985 { 4986 "chips": ["gfx6"], 4987 "map": {"at": 47176, "to": "mm"}, 4988 "name": "COMPUTE_PGM_RSRC1", 4989 "type_ref": "COMPUTE_PGM_RSRC1" 4990 }, 4991 { 4992 "chips": ["gfx6"], 4993 "map": {"at": 47180, "to": "mm"}, 4994 "name": "COMPUTE_PGM_RSRC2", 4995 "type_ref": "COMPUTE_PGM_RSRC2" 4996 }, 4997 { 4998 "chips": ["gfx6"], 4999 "map": {"at": 47184, "to": "mm"}, 5000 "name": "COMPUTE_VMID", 5001 "type_ref": "COMPUTE_VMID" 5002 }, 5003 { 5004 "chips": ["gfx6"], 5005 "map": {"at": 47188, "to": "mm"}, 5006 "name": "COMPUTE_RESOURCE_LIMITS", 5007 "type_ref": "COMPUTE_RESOURCE_LIMITS" 5008 }, 5009 { 5010 "chips": ["gfx6"], 5011 "map": {"at": 47192, "to": "mm"}, 5012 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0", 5013 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 5014 }, 5015 { 5016 "chips": ["gfx6"], 5017 "map": {"at": 47196, "to": "mm"}, 5018 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1", 5019 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 5020 }, 5021 { 5022 "chips": ["gfx6"], 5023 "map": {"at": 47200, "to": "mm"}, 5024 "name": "COMPUTE_TMPRING_SIZE", 5025 "type_ref": "COMPUTE_TMPRING_SIZE" 5026 }, 5027 { 5028 "chips": ["gfx6"], 5029 "map": {"at": 47360, "to": "mm"}, 5030 "name": "COMPUTE_USER_DATA_0", 5031 "type_ref": "SQ_WAVE_TTMP0" 5032 }, 5033 { 5034 "chips": ["gfx6"], 5035 "map": {"at": 47364, "to": "mm"}, 5036 "name": "COMPUTE_USER_DATA_1", 5037 "type_ref": "SQ_WAVE_TTMP0" 5038 }, 5039 { 5040 "chips": ["gfx6"], 5041 "map": {"at": 47368, "to": "mm"}, 5042 "name": "COMPUTE_USER_DATA_2", 5043 "type_ref": "SQ_WAVE_TTMP0" 5044 }, 5045 { 5046 "chips": ["gfx6"], 5047 "map": {"at": 47372, "to": "mm"}, 5048 "name": "COMPUTE_USER_DATA_3", 5049 "type_ref": "SQ_WAVE_TTMP0" 5050 }, 5051 { 5052 "chips": ["gfx6"], 5053 "map": {"at": 47376, "to": "mm"}, 5054 "name": "COMPUTE_USER_DATA_4", 5055 "type_ref": "SQ_WAVE_TTMP0" 5056 }, 5057 { 5058 "chips": ["gfx6"], 5059 "map": {"at": 47380, "to": "mm"}, 5060 "name": "COMPUTE_USER_DATA_5", 5061 "type_ref": "SQ_WAVE_TTMP0" 5062 }, 5063 { 5064 "chips": ["gfx6"], 5065 "map": {"at": 47384, "to": "mm"}, 5066 "name": "COMPUTE_USER_DATA_6", 5067 "type_ref": "SQ_WAVE_TTMP0" 5068 }, 5069 { 5070 "chips": ["gfx6"], 5071 "map": {"at": 47388, "to": "mm"}, 5072 "name": "COMPUTE_USER_DATA_7", 5073 "type_ref": "SQ_WAVE_TTMP0" 5074 }, 5075 { 5076 "chips": ["gfx6"], 5077 "map": {"at": 47392, "to": "mm"}, 5078 "name": "COMPUTE_USER_DATA_8", 5079 "type_ref": "SQ_WAVE_TTMP0" 5080 }, 5081 { 5082 "chips": ["gfx6"], 5083 "map": {"at": 47396, "to": "mm"}, 5084 "name": "COMPUTE_USER_DATA_9", 5085 "type_ref": "SQ_WAVE_TTMP0" 5086 }, 5087 { 5088 "chips": ["gfx6"], 5089 "map": {"at": 47400, "to": "mm"}, 5090 "name": "COMPUTE_USER_DATA_10", 5091 "type_ref": "SQ_WAVE_TTMP0" 5092 }, 5093 { 5094 "chips": ["gfx6"], 5095 "map": {"at": 47404, "to": "mm"}, 5096 "name": "COMPUTE_USER_DATA_11", 5097 "type_ref": "SQ_WAVE_TTMP0" 5098 }, 5099 { 5100 "chips": ["gfx6"], 5101 "map": {"at": 47408, "to": "mm"}, 5102 "name": "COMPUTE_USER_DATA_12", 5103 "type_ref": "SQ_WAVE_TTMP0" 5104 }, 5105 { 5106 "chips": ["gfx6"], 5107 "map": {"at": 47412, "to": "mm"}, 5108 "name": "COMPUTE_USER_DATA_13", 5109 "type_ref": "SQ_WAVE_TTMP0" 5110 }, 5111 { 5112 "chips": ["gfx6"], 5113 "map": {"at": 47416, "to": "mm"}, 5114 "name": "COMPUTE_USER_DATA_14", 5115 "type_ref": "SQ_WAVE_TTMP0" 5116 }, 5117 { 5118 "chips": ["gfx6"], 5119 "map": {"at": 47420, "to": "mm"}, 5120 "name": "COMPUTE_USER_DATA_15", 5121 "type_ref": "SQ_WAVE_TTMP0" 5122 }, 5123 { 5124 "chips": ["gfx6"], 5125 "map": {"at": 163840, "to": "mm"}, 5126 "name": "DB_RENDER_CONTROL", 5127 "type_ref": "DB_RENDER_CONTROL" 5128 }, 5129 { 5130 "chips": ["gfx6"], 5131 "map": {"at": 163844, "to": "mm"}, 5132 "name": "DB_COUNT_CONTROL", 5133 "type_ref": "DB_COUNT_CONTROL" 5134 }, 5135 { 5136 "chips": ["gfx6"], 5137 "map": {"at": 163848, "to": "mm"}, 5138 "name": "DB_DEPTH_VIEW", 5139 "type_ref": "DB_DEPTH_VIEW" 5140 }, 5141 { 5142 "chips": ["gfx6"], 5143 "map": {"at": 163852, "to": "mm"}, 5144 "name": "DB_RENDER_OVERRIDE", 5145 "type_ref": "DB_RENDER_OVERRIDE" 5146 }, 5147 { 5148 "chips": ["gfx6"], 5149 "map": {"at": 163856, "to": "mm"}, 5150 "name": "DB_RENDER_OVERRIDE2", 5151 "type_ref": "DB_RENDER_OVERRIDE2" 5152 }, 5153 { 5154 "chips": ["gfx6"], 5155 "map": {"at": 163860, "to": "mm"}, 5156 "name": "DB_HTILE_DATA_BASE", 5157 "type_ref": "CB_COLOR0_BASE" 5158 }, 5159 { 5160 "chips": ["gfx6"], 5161 "map": {"at": 163872, "to": "mm"}, 5162 "name": "DB_DEPTH_BOUNDS_MIN", 5163 "type_ref": "DB_DEPTH_BOUNDS_MIN" 5164 }, 5165 { 5166 "chips": ["gfx6"], 5167 "map": {"at": 163876, "to": "mm"}, 5168 "name": "DB_DEPTH_BOUNDS_MAX", 5169 "type_ref": "DB_DEPTH_BOUNDS_MAX" 5170 }, 5171 { 5172 "chips": ["gfx6"], 5173 "map": {"at": 163880, "to": "mm"}, 5174 "name": "DB_STENCIL_CLEAR", 5175 "type_ref": "DB_STENCIL_CLEAR" 5176 }, 5177 { 5178 "chips": ["gfx6"], 5179 "map": {"at": 163884, "to": "mm"}, 5180 "name": "DB_DEPTH_CLEAR", 5181 "type_ref": "DB_DEPTH_CLEAR" 5182 }, 5183 { 5184 "chips": ["gfx6"], 5185 "map": {"at": 163888, "to": "mm"}, 5186 "name": "PA_SC_SCREEN_SCISSOR_TL", 5187 "type_ref": "PA_SC_SCREEN_SCISSOR_TL" 5188 }, 5189 { 5190 "chips": ["gfx6"], 5191 "map": {"at": 163892, "to": "mm"}, 5192 "name": "PA_SC_SCREEN_SCISSOR_BR", 5193 "type_ref": "PA_SC_SCREEN_SCISSOR_BR" 5194 }, 5195 { 5196 "chips": ["gfx6"], 5197 "map": {"at": 163900, "to": "mm"}, 5198 "name": "DB_DEPTH_INFO", 5199 "type_ref": "DB_DEPTH_INFO" 5200 }, 5201 { 5202 "chips": ["gfx6"], 5203 "map": {"at": 163904, "to": "mm"}, 5204 "name": "DB_Z_INFO", 5205 "type_ref": "DB_Z_INFO" 5206 }, 5207 { 5208 "chips": ["gfx6"], 5209 "map": {"at": 163908, "to": "mm"}, 5210 "name": "DB_STENCIL_INFO", 5211 "type_ref": "DB_STENCIL_INFO" 5212 }, 5213 { 5214 "chips": ["gfx6"], 5215 "map": {"at": 163912, "to": "mm"}, 5216 "name": "DB_Z_READ_BASE", 5217 "type_ref": "CB_COLOR0_BASE" 5218 }, 5219 { 5220 "chips": ["gfx6"], 5221 "map": {"at": 163916, "to": "mm"}, 5222 "name": "DB_STENCIL_READ_BASE", 5223 "type_ref": "CB_COLOR0_BASE" 5224 }, 5225 { 5226 "chips": ["gfx6"], 5227 "map": {"at": 163920, "to": "mm"}, 5228 "name": "DB_Z_WRITE_BASE", 5229 "type_ref": "CB_COLOR0_BASE" 5230 }, 5231 { 5232 "chips": ["gfx6"], 5233 "map": {"at": 163924, "to": "mm"}, 5234 "name": "DB_STENCIL_WRITE_BASE", 5235 "type_ref": "CB_COLOR0_BASE" 5236 }, 5237 { 5238 "chips": ["gfx6"], 5239 "map": {"at": 163928, "to": "mm"}, 5240 "name": "DB_DEPTH_SIZE", 5241 "type_ref": "DB_DEPTH_SIZE" 5242 }, 5243 { 5244 "chips": ["gfx6"], 5245 "map": {"at": 163932, "to": "mm"}, 5246 "name": "DB_DEPTH_SLICE", 5247 "type_ref": "DB_DEPTH_SLICE" 5248 }, 5249 { 5250 "chips": ["gfx6"], 5251 "map": {"at": 163968, "to": "mm"}, 5252 "name": "TA_BC_BASE_ADDR", 5253 "type_ref": "TA_BC_BASE_ADDR" 5254 }, 5255 { 5256 "chips": ["gfx6"], 5257 "map": {"at": 164344, "to": "mm"}, 5258 "name": "COHER_DEST_BASE_2", 5259 "type_ref": "COHER_DEST_BASE_0" 5260 }, 5261 { 5262 "chips": ["gfx6"], 5263 "map": {"at": 164348, "to": "mm"}, 5264 "name": "COHER_DEST_BASE_3", 5265 "type_ref": "COHER_DEST_BASE_0" 5266 }, 5267 { 5268 "chips": ["gfx6"], 5269 "map": {"at": 164352, "to": "mm"}, 5270 "name": "PA_SC_WINDOW_OFFSET", 5271 "type_ref": "PA_SC_WINDOW_OFFSET" 5272 }, 5273 { 5274 "chips": ["gfx6"], 5275 "map": {"at": 164356, "to": "mm"}, 5276 "name": "PA_SC_WINDOW_SCISSOR_TL", 5277 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5278 }, 5279 { 5280 "chips": ["gfx6"], 5281 "map": {"at": 164360, "to": "mm"}, 5282 "name": "PA_SC_WINDOW_SCISSOR_BR", 5283 "type_ref": "PA_SC_CLIPRECT_0_BR" 5284 }, 5285 { 5286 "chips": ["gfx6"], 5287 "map": {"at": 164364, "to": "mm"}, 5288 "name": "PA_SC_CLIPRECT_RULE", 5289 "type_ref": "PA_SC_CLIPRECT_RULE" 5290 }, 5291 { 5292 "chips": ["gfx6"], 5293 "map": {"at": 164368, "to": "mm"}, 5294 "name": "PA_SC_CLIPRECT_0_TL", 5295 "type_ref": "PA_SC_CLIPRECT_0_TL" 5296 }, 5297 { 5298 "chips": ["gfx6"], 5299 "map": {"at": 164372, "to": "mm"}, 5300 "name": "PA_SC_CLIPRECT_0_BR", 5301 "type_ref": "PA_SC_CLIPRECT_0_BR" 5302 }, 5303 { 5304 "chips": ["gfx6"], 5305 "map": {"at": 164376, "to": "mm"}, 5306 "name": "PA_SC_CLIPRECT_1_TL", 5307 "type_ref": "PA_SC_CLIPRECT_0_TL" 5308 }, 5309 { 5310 "chips": ["gfx6"], 5311 "map": {"at": 164380, "to": "mm"}, 5312 "name": "PA_SC_CLIPRECT_1_BR", 5313 "type_ref": "PA_SC_CLIPRECT_0_BR" 5314 }, 5315 { 5316 "chips": ["gfx6"], 5317 "map": {"at": 164384, "to": "mm"}, 5318 "name": "PA_SC_CLIPRECT_2_TL", 5319 "type_ref": "PA_SC_CLIPRECT_0_TL" 5320 }, 5321 { 5322 "chips": ["gfx6"], 5323 "map": {"at": 164388, "to": "mm"}, 5324 "name": "PA_SC_CLIPRECT_2_BR", 5325 "type_ref": "PA_SC_CLIPRECT_0_BR" 5326 }, 5327 { 5328 "chips": ["gfx6"], 5329 "map": {"at": 164392, "to": "mm"}, 5330 "name": "PA_SC_CLIPRECT_3_TL", 5331 "type_ref": "PA_SC_CLIPRECT_0_TL" 5332 }, 5333 { 5334 "chips": ["gfx6"], 5335 "map": {"at": 164396, "to": "mm"}, 5336 "name": "PA_SC_CLIPRECT_3_BR", 5337 "type_ref": "PA_SC_CLIPRECT_0_BR" 5338 }, 5339 { 5340 "chips": ["gfx6"], 5341 "map": {"at": 164400, "to": "mm"}, 5342 "name": "PA_SC_EDGERULE", 5343 "type_ref": "PA_SC_EDGERULE" 5344 }, 5345 { 5346 "chips": ["gfx6"], 5347 "map": {"at": 164404, "to": "mm"}, 5348 "name": "PA_SU_HARDWARE_SCREEN_OFFSET", 5349 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET" 5350 }, 5351 { 5352 "chips": ["gfx6"], 5353 "map": {"at": 164408, "to": "mm"}, 5354 "name": "CB_TARGET_MASK", 5355 "type_ref": "CB_TARGET_MASK" 5356 }, 5357 { 5358 "chips": ["gfx6"], 5359 "map": {"at": 164412, "to": "mm"}, 5360 "name": "CB_SHADER_MASK", 5361 "type_ref": "CB_SHADER_MASK" 5362 }, 5363 { 5364 "chips": ["gfx6"], 5365 "map": {"at": 164416, "to": "mm"}, 5366 "name": "PA_SC_GENERIC_SCISSOR_TL", 5367 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5368 }, 5369 { 5370 "chips": ["gfx6"], 5371 "map": {"at": 164420, "to": "mm"}, 5372 "name": "PA_SC_GENERIC_SCISSOR_BR", 5373 "type_ref": "PA_SC_CLIPRECT_0_BR" 5374 }, 5375 { 5376 "chips": ["gfx6"], 5377 "map": {"at": 164424, "to": "mm"}, 5378 "name": "COHER_DEST_BASE_0", 5379 "type_ref": "COHER_DEST_BASE_0" 5380 }, 5381 { 5382 "chips": ["gfx6"], 5383 "map": {"at": 164428, "to": "mm"}, 5384 "name": "COHER_DEST_BASE_1", 5385 "type_ref": "COHER_DEST_BASE_0" 5386 }, 5387 { 5388 "chips": ["gfx6"], 5389 "map": {"at": 164432, "to": "mm"}, 5390 "name": "PA_SC_VPORT_SCISSOR_0_TL", 5391 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5392 }, 5393 { 5394 "chips": ["gfx6"], 5395 "map": {"at": 164436, "to": "mm"}, 5396 "name": "PA_SC_VPORT_SCISSOR_0_BR", 5397 "type_ref": "PA_SC_CLIPRECT_0_BR" 5398 }, 5399 { 5400 "chips": ["gfx6"], 5401 "map": {"at": 164440, "to": "mm"}, 5402 "name": "PA_SC_VPORT_SCISSOR_1_TL", 5403 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5404 }, 5405 { 5406 "chips": ["gfx6"], 5407 "map": {"at": 164444, "to": "mm"}, 5408 "name": "PA_SC_VPORT_SCISSOR_1_BR", 5409 "type_ref": "PA_SC_CLIPRECT_0_BR" 5410 }, 5411 { 5412 "chips": ["gfx6"], 5413 "map": {"at": 164448, "to": "mm"}, 5414 "name": "PA_SC_VPORT_SCISSOR_2_TL", 5415 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5416 }, 5417 { 5418 "chips": ["gfx6"], 5419 "map": {"at": 164452, "to": "mm"}, 5420 "name": "PA_SC_VPORT_SCISSOR_2_BR", 5421 "type_ref": "PA_SC_CLIPRECT_0_BR" 5422 }, 5423 { 5424 "chips": ["gfx6"], 5425 "map": {"at": 164456, "to": "mm"}, 5426 "name": "PA_SC_VPORT_SCISSOR_3_TL", 5427 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5428 }, 5429 { 5430 "chips": ["gfx6"], 5431 "map": {"at": 164460, "to": "mm"}, 5432 "name": "PA_SC_VPORT_SCISSOR_3_BR", 5433 "type_ref": "PA_SC_CLIPRECT_0_BR" 5434 }, 5435 { 5436 "chips": ["gfx6"], 5437 "map": {"at": 164464, "to": "mm"}, 5438 "name": "PA_SC_VPORT_SCISSOR_4_TL", 5439 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5440 }, 5441 { 5442 "chips": ["gfx6"], 5443 "map": {"at": 164468, "to": "mm"}, 5444 "name": "PA_SC_VPORT_SCISSOR_4_BR", 5445 "type_ref": "PA_SC_CLIPRECT_0_BR" 5446 }, 5447 { 5448 "chips": ["gfx6"], 5449 "map": {"at": 164472, "to": "mm"}, 5450 "name": "PA_SC_VPORT_SCISSOR_5_TL", 5451 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5452 }, 5453 { 5454 "chips": ["gfx6"], 5455 "map": {"at": 164476, "to": "mm"}, 5456 "name": "PA_SC_VPORT_SCISSOR_5_BR", 5457 "type_ref": "PA_SC_CLIPRECT_0_BR" 5458 }, 5459 { 5460 "chips": ["gfx6"], 5461 "map": {"at": 164480, "to": "mm"}, 5462 "name": "PA_SC_VPORT_SCISSOR_6_TL", 5463 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5464 }, 5465 { 5466 "chips": ["gfx6"], 5467 "map": {"at": 164484, "to": "mm"}, 5468 "name": "PA_SC_VPORT_SCISSOR_6_BR", 5469 "type_ref": "PA_SC_CLIPRECT_0_BR" 5470 }, 5471 { 5472 "chips": ["gfx6"], 5473 "map": {"at": 164488, "to": "mm"}, 5474 "name": "PA_SC_VPORT_SCISSOR_7_TL", 5475 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5476 }, 5477 { 5478 "chips": ["gfx6"], 5479 "map": {"at": 164492, "to": "mm"}, 5480 "name": "PA_SC_VPORT_SCISSOR_7_BR", 5481 "type_ref": "PA_SC_CLIPRECT_0_BR" 5482 }, 5483 { 5484 "chips": ["gfx6"], 5485 "map": {"at": 164496, "to": "mm"}, 5486 "name": "PA_SC_VPORT_SCISSOR_8_TL", 5487 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5488 }, 5489 { 5490 "chips": ["gfx6"], 5491 "map": {"at": 164500, "to": "mm"}, 5492 "name": "PA_SC_VPORT_SCISSOR_8_BR", 5493 "type_ref": "PA_SC_CLIPRECT_0_BR" 5494 }, 5495 { 5496 "chips": ["gfx6"], 5497 "map": {"at": 164504, "to": "mm"}, 5498 "name": "PA_SC_VPORT_SCISSOR_9_TL", 5499 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5500 }, 5501 { 5502 "chips": ["gfx6"], 5503 "map": {"at": 164508, "to": "mm"}, 5504 "name": "PA_SC_VPORT_SCISSOR_9_BR", 5505 "type_ref": "PA_SC_CLIPRECT_0_BR" 5506 }, 5507 { 5508 "chips": ["gfx6"], 5509 "map": {"at": 164512, "to": "mm"}, 5510 "name": "PA_SC_VPORT_SCISSOR_10_TL", 5511 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5512 }, 5513 { 5514 "chips": ["gfx6"], 5515 "map": {"at": 164516, "to": "mm"}, 5516 "name": "PA_SC_VPORT_SCISSOR_10_BR", 5517 "type_ref": "PA_SC_CLIPRECT_0_BR" 5518 }, 5519 { 5520 "chips": ["gfx6"], 5521 "map": {"at": 164520, "to": "mm"}, 5522 "name": "PA_SC_VPORT_SCISSOR_11_TL", 5523 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5524 }, 5525 { 5526 "chips": ["gfx6"], 5527 "map": {"at": 164524, "to": "mm"}, 5528 "name": "PA_SC_VPORT_SCISSOR_11_BR", 5529 "type_ref": "PA_SC_CLIPRECT_0_BR" 5530 }, 5531 { 5532 "chips": ["gfx6"], 5533 "map": {"at": 164528, "to": "mm"}, 5534 "name": "PA_SC_VPORT_SCISSOR_12_TL", 5535 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5536 }, 5537 { 5538 "chips": ["gfx6"], 5539 "map": {"at": 164532, "to": "mm"}, 5540 "name": "PA_SC_VPORT_SCISSOR_12_BR", 5541 "type_ref": "PA_SC_CLIPRECT_0_BR" 5542 }, 5543 { 5544 "chips": ["gfx6"], 5545 "map": {"at": 164536, "to": "mm"}, 5546 "name": "PA_SC_VPORT_SCISSOR_13_TL", 5547 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5548 }, 5549 { 5550 "chips": ["gfx6"], 5551 "map": {"at": 164540, "to": "mm"}, 5552 "name": "PA_SC_VPORT_SCISSOR_13_BR", 5553 "type_ref": "PA_SC_CLIPRECT_0_BR" 5554 }, 5555 { 5556 "chips": ["gfx6"], 5557 "map": {"at": 164544, "to": "mm"}, 5558 "name": "PA_SC_VPORT_SCISSOR_14_TL", 5559 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5560 }, 5561 { 5562 "chips": ["gfx6"], 5563 "map": {"at": 164548, "to": "mm"}, 5564 "name": "PA_SC_VPORT_SCISSOR_14_BR", 5565 "type_ref": "PA_SC_CLIPRECT_0_BR" 5566 }, 5567 { 5568 "chips": ["gfx6"], 5569 "map": {"at": 164552, "to": "mm"}, 5570 "name": "PA_SC_VPORT_SCISSOR_15_TL", 5571 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5572 }, 5573 { 5574 "chips": ["gfx6"], 5575 "map": {"at": 164556, "to": "mm"}, 5576 "name": "PA_SC_VPORT_SCISSOR_15_BR", 5577 "type_ref": "PA_SC_CLIPRECT_0_BR" 5578 }, 5579 { 5580 "chips": ["gfx6"], 5581 "map": {"at": 164560, "to": "mm"}, 5582 "name": "PA_SC_VPORT_ZMIN_0", 5583 "type_ref": "PA_SC_VPORT_ZMIN_0" 5584 }, 5585 { 5586 "chips": ["gfx6"], 5587 "map": {"at": 164564, "to": "mm"}, 5588 "name": "PA_SC_VPORT_ZMAX_0", 5589 "type_ref": "PA_SC_VPORT_ZMAX_0" 5590 }, 5591 { 5592 "chips": ["gfx6"], 5593 "map": {"at": 164568, "to": "mm"}, 5594 "name": "PA_SC_VPORT_ZMIN_1", 5595 "type_ref": "PA_SC_VPORT_ZMIN_0" 5596 }, 5597 { 5598 "chips": ["gfx6"], 5599 "map": {"at": 164572, "to": "mm"}, 5600 "name": "PA_SC_VPORT_ZMAX_1", 5601 "type_ref": "PA_SC_VPORT_ZMAX_0" 5602 }, 5603 { 5604 "chips": ["gfx6"], 5605 "map": {"at": 164576, "to": "mm"}, 5606 "name": "PA_SC_VPORT_ZMIN_2", 5607 "type_ref": "PA_SC_VPORT_ZMIN_0" 5608 }, 5609 { 5610 "chips": ["gfx6"], 5611 "map": {"at": 164580, "to": "mm"}, 5612 "name": "PA_SC_VPORT_ZMAX_2", 5613 "type_ref": "PA_SC_VPORT_ZMAX_0" 5614 }, 5615 { 5616 "chips": ["gfx6"], 5617 "map": {"at": 164584, "to": "mm"}, 5618 "name": "PA_SC_VPORT_ZMIN_3", 5619 "type_ref": "PA_SC_VPORT_ZMIN_0" 5620 }, 5621 { 5622 "chips": ["gfx6"], 5623 "map": {"at": 164588, "to": "mm"}, 5624 "name": "PA_SC_VPORT_ZMAX_3", 5625 "type_ref": "PA_SC_VPORT_ZMAX_0" 5626 }, 5627 { 5628 "chips": ["gfx6"], 5629 "map": {"at": 164592, "to": "mm"}, 5630 "name": "PA_SC_VPORT_ZMIN_4", 5631 "type_ref": "PA_SC_VPORT_ZMIN_0" 5632 }, 5633 { 5634 "chips": ["gfx6"], 5635 "map": {"at": 164596, "to": "mm"}, 5636 "name": "PA_SC_VPORT_ZMAX_4", 5637 "type_ref": "PA_SC_VPORT_ZMAX_0" 5638 }, 5639 { 5640 "chips": ["gfx6"], 5641 "map": {"at": 164600, "to": "mm"}, 5642 "name": "PA_SC_VPORT_ZMIN_5", 5643 "type_ref": "PA_SC_VPORT_ZMIN_0" 5644 }, 5645 { 5646 "chips": ["gfx6"], 5647 "map": {"at": 164604, "to": "mm"}, 5648 "name": "PA_SC_VPORT_ZMAX_5", 5649 "type_ref": "PA_SC_VPORT_ZMAX_0" 5650 }, 5651 { 5652 "chips": ["gfx6"], 5653 "map": {"at": 164608, "to": "mm"}, 5654 "name": "PA_SC_VPORT_ZMIN_6", 5655 "type_ref": "PA_SC_VPORT_ZMIN_0" 5656 }, 5657 { 5658 "chips": ["gfx6"], 5659 "map": {"at": 164612, "to": "mm"}, 5660 "name": "PA_SC_VPORT_ZMAX_6", 5661 "type_ref": "PA_SC_VPORT_ZMAX_0" 5662 }, 5663 { 5664 "chips": ["gfx6"], 5665 "map": {"at": 164616, "to": "mm"}, 5666 "name": "PA_SC_VPORT_ZMIN_7", 5667 "type_ref": "PA_SC_VPORT_ZMIN_0" 5668 }, 5669 { 5670 "chips": ["gfx6"], 5671 "map": {"at": 164620, "to": "mm"}, 5672 "name": "PA_SC_VPORT_ZMAX_7", 5673 "type_ref": "PA_SC_VPORT_ZMAX_0" 5674 }, 5675 { 5676 "chips": ["gfx6"], 5677 "map": {"at": 164624, "to": "mm"}, 5678 "name": "PA_SC_VPORT_ZMIN_8", 5679 "type_ref": "PA_SC_VPORT_ZMIN_0" 5680 }, 5681 { 5682 "chips": ["gfx6"], 5683 "map": {"at": 164628, "to": "mm"}, 5684 "name": "PA_SC_VPORT_ZMAX_8", 5685 "type_ref": "PA_SC_VPORT_ZMAX_0" 5686 }, 5687 { 5688 "chips": ["gfx6"], 5689 "map": {"at": 164632, "to": "mm"}, 5690 "name": "PA_SC_VPORT_ZMIN_9", 5691 "type_ref": "PA_SC_VPORT_ZMIN_0" 5692 }, 5693 { 5694 "chips": ["gfx6"], 5695 "map": {"at": 164636, "to": "mm"}, 5696 "name": "PA_SC_VPORT_ZMAX_9", 5697 "type_ref": "PA_SC_VPORT_ZMAX_0" 5698 }, 5699 { 5700 "chips": ["gfx6"], 5701 "map": {"at": 164640, "to": "mm"}, 5702 "name": "PA_SC_VPORT_ZMIN_10", 5703 "type_ref": "PA_SC_VPORT_ZMIN_0" 5704 }, 5705 { 5706 "chips": ["gfx6"], 5707 "map": {"at": 164644, "to": "mm"}, 5708 "name": "PA_SC_VPORT_ZMAX_10", 5709 "type_ref": "PA_SC_VPORT_ZMAX_0" 5710 }, 5711 { 5712 "chips": ["gfx6"], 5713 "map": {"at": 164648, "to": "mm"}, 5714 "name": "PA_SC_VPORT_ZMIN_11", 5715 "type_ref": "PA_SC_VPORT_ZMIN_0" 5716 }, 5717 { 5718 "chips": ["gfx6"], 5719 "map": {"at": 164652, "to": "mm"}, 5720 "name": "PA_SC_VPORT_ZMAX_11", 5721 "type_ref": "PA_SC_VPORT_ZMAX_0" 5722 }, 5723 { 5724 "chips": ["gfx6"], 5725 "map": {"at": 164656, "to": "mm"}, 5726 "name": "PA_SC_VPORT_ZMIN_12", 5727 "type_ref": "PA_SC_VPORT_ZMIN_0" 5728 }, 5729 { 5730 "chips": ["gfx6"], 5731 "map": {"at": 164660, "to": "mm"}, 5732 "name": "PA_SC_VPORT_ZMAX_12", 5733 "type_ref": "PA_SC_VPORT_ZMAX_0" 5734 }, 5735 { 5736 "chips": ["gfx6"], 5737 "map": {"at": 164664, "to": "mm"}, 5738 "name": "PA_SC_VPORT_ZMIN_13", 5739 "type_ref": "PA_SC_VPORT_ZMIN_0" 5740 }, 5741 { 5742 "chips": ["gfx6"], 5743 "map": {"at": 164668, "to": "mm"}, 5744 "name": "PA_SC_VPORT_ZMAX_13", 5745 "type_ref": "PA_SC_VPORT_ZMAX_0" 5746 }, 5747 { 5748 "chips": ["gfx6"], 5749 "map": {"at": 164672, "to": "mm"}, 5750 "name": "PA_SC_VPORT_ZMIN_14", 5751 "type_ref": "PA_SC_VPORT_ZMIN_0" 5752 }, 5753 { 5754 "chips": ["gfx6"], 5755 "map": {"at": 164676, "to": "mm"}, 5756 "name": "PA_SC_VPORT_ZMAX_14", 5757 "type_ref": "PA_SC_VPORT_ZMAX_0" 5758 }, 5759 { 5760 "chips": ["gfx6"], 5761 "map": {"at": 164680, "to": "mm"}, 5762 "name": "PA_SC_VPORT_ZMIN_15", 5763 "type_ref": "PA_SC_VPORT_ZMIN_0" 5764 }, 5765 { 5766 "chips": ["gfx6"], 5767 "map": {"at": 164684, "to": "mm"}, 5768 "name": "PA_SC_VPORT_ZMAX_15", 5769 "type_ref": "PA_SC_VPORT_ZMAX_0" 5770 }, 5771 { 5772 "chips": ["gfx6"], 5773 "map": {"at": 164688, "to": "mm"}, 5774 "name": "PA_SC_RASTER_CONFIG", 5775 "type_ref": "PA_SC_RASTER_CONFIG" 5776 }, 5777 { 5778 "chips": ["gfx6"], 5779 "map": {"at": 164704, "to": "mm"}, 5780 "name": "CP_PERFMON_CNTX_CNTL", 5781 "type_ref": "CP_PERFMON_CNTX_CNTL" 5782 }, 5783 { 5784 "chips": ["gfx6"], 5785 "map": {"at": 164708, "to": "mm"}, 5786 "name": "CP_RINGID", 5787 "type_ref": "CP_RINGID" 5788 }, 5789 { 5790 "chips": ["gfx6"], 5791 "map": {"at": 164712, "to": "mm"}, 5792 "name": "CP_VMID", 5793 "type_ref": "CP_VMID" 5794 }, 5795 { 5796 "chips": ["gfx6"], 5797 "map": {"at": 164864, "to": "mm"}, 5798 "name": "VGT_MAX_VTX_INDX", 5799 "type_ref": "VGT_MAX_VTX_INDX" 5800 }, 5801 { 5802 "chips": ["gfx6"], 5803 "map": {"at": 164868, "to": "mm"}, 5804 "name": "VGT_MIN_VTX_INDX", 5805 "type_ref": "VGT_MIN_VTX_INDX" 5806 }, 5807 { 5808 "chips": ["gfx6"], 5809 "map": {"at": 164872, "to": "mm"}, 5810 "name": "VGT_INDX_OFFSET", 5811 "type_ref": "VGT_INDX_OFFSET" 5812 }, 5813 { 5814 "chips": ["gfx6"], 5815 "map": {"at": 164876, "to": "mm"}, 5816 "name": "VGT_MULTI_PRIM_IB_RESET_INDX", 5817 "type_ref": "VGT_MULTI_PRIM_IB_RESET_INDX" 5818 }, 5819 { 5820 "chips": ["gfx6"], 5821 "map": {"at": 164884, "to": "mm"}, 5822 "name": "CB_BLEND_RED", 5823 "type_ref": "CB_BLEND_RED" 5824 }, 5825 { 5826 "chips": ["gfx6"], 5827 "map": {"at": 164888, "to": "mm"}, 5828 "name": "CB_BLEND_GREEN", 5829 "type_ref": "CB_BLEND_GREEN" 5830 }, 5831 { 5832 "chips": ["gfx6"], 5833 "map": {"at": 164892, "to": "mm"}, 5834 "name": "CB_BLEND_BLUE", 5835 "type_ref": "CB_BLEND_BLUE" 5836 }, 5837 { 5838 "chips": ["gfx6"], 5839 "map": {"at": 164896, "to": "mm"}, 5840 "name": "CB_BLEND_ALPHA", 5841 "type_ref": "CB_BLEND_ALPHA" 5842 }, 5843 { 5844 "chips": ["gfx6"], 5845 "map": {"at": 164908, "to": "mm"}, 5846 "name": "DB_STENCIL_CONTROL", 5847 "type_ref": "DB_STENCIL_CONTROL" 5848 }, 5849 { 5850 "chips": ["gfx6"], 5851 "map": {"at": 164912, "to": "mm"}, 5852 "name": "DB_STENCILREFMASK", 5853 "type_ref": "DB_STENCILREFMASK" 5854 }, 5855 { 5856 "chips": ["gfx6"], 5857 "map": {"at": 164916, "to": "mm"}, 5858 "name": "DB_STENCILREFMASK_BF", 5859 "type_ref": "DB_STENCILREFMASK_BF" 5860 }, 5861 { 5862 "chips": ["gfx6"], 5863 "map": {"at": 164924, "to": "mm"}, 5864 "name": "PA_CL_VPORT_XSCALE", 5865 "type_ref": "PA_CL_VPORT_XSCALE" 5866 }, 5867 { 5868 "chips": ["gfx6"], 5869 "map": {"at": 164928, "to": "mm"}, 5870 "name": "PA_CL_VPORT_XOFFSET", 5871 "type_ref": "PA_CL_VPORT_XOFFSET" 5872 }, 5873 { 5874 "chips": ["gfx6"], 5875 "map": {"at": 164932, "to": "mm"}, 5876 "name": "PA_CL_VPORT_YSCALE", 5877 "type_ref": "PA_CL_VPORT_YSCALE" 5878 }, 5879 { 5880 "chips": ["gfx6"], 5881 "map": {"at": 164936, "to": "mm"}, 5882 "name": "PA_CL_VPORT_YOFFSET", 5883 "type_ref": "PA_CL_VPORT_YOFFSET" 5884 }, 5885 { 5886 "chips": ["gfx6"], 5887 "map": {"at": 164940, "to": "mm"}, 5888 "name": "PA_CL_VPORT_ZSCALE", 5889 "type_ref": "PA_CL_VPORT_ZSCALE" 5890 }, 5891 { 5892 "chips": ["gfx6"], 5893 "map": {"at": 164944, "to": "mm"}, 5894 "name": "PA_CL_VPORT_ZOFFSET", 5895 "type_ref": "PA_CL_VPORT_ZOFFSET" 5896 }, 5897 { 5898 "chips": ["gfx6"], 5899 "map": {"at": 164948, "to": "mm"}, 5900 "name": "PA_CL_VPORT_XSCALE_1", 5901 "type_ref": "PA_CL_VPORT_XSCALE" 5902 }, 5903 { 5904 "chips": ["gfx6"], 5905 "map": {"at": 164952, "to": "mm"}, 5906 "name": "PA_CL_VPORT_XOFFSET_1", 5907 "type_ref": "PA_CL_VPORT_XOFFSET" 5908 }, 5909 { 5910 "chips": ["gfx6"], 5911 "map": {"at": 164956, "to": "mm"}, 5912 "name": "PA_CL_VPORT_YSCALE_1", 5913 "type_ref": "PA_CL_VPORT_YSCALE" 5914 }, 5915 { 5916 "chips": ["gfx6"], 5917 "map": {"at": 164960, "to": "mm"}, 5918 "name": "PA_CL_VPORT_YOFFSET_1", 5919 "type_ref": "PA_CL_VPORT_YOFFSET" 5920 }, 5921 { 5922 "chips": ["gfx6"], 5923 "map": {"at": 164964, "to": "mm"}, 5924 "name": "PA_CL_VPORT_ZSCALE_1", 5925 "type_ref": "PA_CL_VPORT_ZSCALE" 5926 }, 5927 { 5928 "chips": ["gfx6"], 5929 "map": {"at": 164968, "to": "mm"}, 5930 "name": "PA_CL_VPORT_ZOFFSET_1", 5931 "type_ref": "PA_CL_VPORT_ZOFFSET" 5932 }, 5933 { 5934 "chips": ["gfx6"], 5935 "map": {"at": 164972, "to": "mm"}, 5936 "name": "PA_CL_VPORT_XSCALE_2", 5937 "type_ref": "PA_CL_VPORT_XSCALE" 5938 }, 5939 { 5940 "chips": ["gfx6"], 5941 "map": {"at": 164976, "to": "mm"}, 5942 "name": "PA_CL_VPORT_XOFFSET_2", 5943 "type_ref": "PA_CL_VPORT_XOFFSET" 5944 }, 5945 { 5946 "chips": ["gfx6"], 5947 "map": {"at": 164980, "to": "mm"}, 5948 "name": "PA_CL_VPORT_YSCALE_2", 5949 "type_ref": "PA_CL_VPORT_YSCALE" 5950 }, 5951 { 5952 "chips": ["gfx6"], 5953 "map": {"at": 164984, "to": "mm"}, 5954 "name": "PA_CL_VPORT_YOFFSET_2", 5955 "type_ref": "PA_CL_VPORT_YOFFSET" 5956 }, 5957 { 5958 "chips": ["gfx6"], 5959 "map": {"at": 164988, "to": "mm"}, 5960 "name": "PA_CL_VPORT_ZSCALE_2", 5961 "type_ref": "PA_CL_VPORT_ZSCALE" 5962 }, 5963 { 5964 "chips": ["gfx6"], 5965 "map": {"at": 164992, "to": "mm"}, 5966 "name": "PA_CL_VPORT_ZOFFSET_2", 5967 "type_ref": "PA_CL_VPORT_ZOFFSET" 5968 }, 5969 { 5970 "chips": ["gfx6"], 5971 "map": {"at": 164996, "to": "mm"}, 5972 "name": "PA_CL_VPORT_XSCALE_3", 5973 "type_ref": "PA_CL_VPORT_XSCALE" 5974 }, 5975 { 5976 "chips": ["gfx6"], 5977 "map": {"at": 165000, "to": "mm"}, 5978 "name": "PA_CL_VPORT_XOFFSET_3", 5979 "type_ref": "PA_CL_VPORT_XOFFSET" 5980 }, 5981 { 5982 "chips": ["gfx6"], 5983 "map": {"at": 165004, "to": "mm"}, 5984 "name": "PA_CL_VPORT_YSCALE_3", 5985 "type_ref": "PA_CL_VPORT_YSCALE" 5986 }, 5987 { 5988 "chips": ["gfx6"], 5989 "map": {"at": 165008, "to": "mm"}, 5990 "name": "PA_CL_VPORT_YOFFSET_3", 5991 "type_ref": "PA_CL_VPORT_YOFFSET" 5992 }, 5993 { 5994 "chips": ["gfx6"], 5995 "map": {"at": 165012, "to": "mm"}, 5996 "name": "PA_CL_VPORT_ZSCALE_3", 5997 "type_ref": "PA_CL_VPORT_ZSCALE" 5998 }, 5999 { 6000 "chips": ["gfx6"], 6001 "map": {"at": 165016, "to": "mm"}, 6002 "name": "PA_CL_VPORT_ZOFFSET_3", 6003 "type_ref": "PA_CL_VPORT_ZOFFSET" 6004 }, 6005 { 6006 "chips": ["gfx6"], 6007 "map": {"at": 165020, "to": "mm"}, 6008 "name": "PA_CL_VPORT_XSCALE_4", 6009 "type_ref": "PA_CL_VPORT_XSCALE" 6010 }, 6011 { 6012 "chips": ["gfx6"], 6013 "map": {"at": 165024, "to": "mm"}, 6014 "name": "PA_CL_VPORT_XOFFSET_4", 6015 "type_ref": "PA_CL_VPORT_XOFFSET" 6016 }, 6017 { 6018 "chips": ["gfx6"], 6019 "map": {"at": 165028, "to": "mm"}, 6020 "name": "PA_CL_VPORT_YSCALE_4", 6021 "type_ref": "PA_CL_VPORT_YSCALE" 6022 }, 6023 { 6024 "chips": ["gfx6"], 6025 "map": {"at": 165032, "to": "mm"}, 6026 "name": "PA_CL_VPORT_YOFFSET_4", 6027 "type_ref": "PA_CL_VPORT_YOFFSET" 6028 }, 6029 { 6030 "chips": ["gfx6"], 6031 "map": {"at": 165036, "to": "mm"}, 6032 "name": "PA_CL_VPORT_ZSCALE_4", 6033 "type_ref": "PA_CL_VPORT_ZSCALE" 6034 }, 6035 { 6036 "chips": ["gfx6"], 6037 "map": {"at": 165040, "to": "mm"}, 6038 "name": "PA_CL_VPORT_ZOFFSET_4", 6039 "type_ref": "PA_CL_VPORT_ZOFFSET" 6040 }, 6041 { 6042 "chips": ["gfx6"], 6043 "map": {"at": 165044, "to": "mm"}, 6044 "name": "PA_CL_VPORT_XSCALE_5", 6045 "type_ref": "PA_CL_VPORT_XSCALE" 6046 }, 6047 { 6048 "chips": ["gfx6"], 6049 "map": {"at": 165048, "to": "mm"}, 6050 "name": "PA_CL_VPORT_XOFFSET_5", 6051 "type_ref": "PA_CL_VPORT_XOFFSET" 6052 }, 6053 { 6054 "chips": ["gfx6"], 6055 "map": {"at": 165052, "to": "mm"}, 6056 "name": "PA_CL_VPORT_YSCALE_5", 6057 "type_ref": "PA_CL_VPORT_YSCALE" 6058 }, 6059 { 6060 "chips": ["gfx6"], 6061 "map": {"at": 165056, "to": "mm"}, 6062 "name": "PA_CL_VPORT_YOFFSET_5", 6063 "type_ref": "PA_CL_VPORT_YOFFSET" 6064 }, 6065 { 6066 "chips": ["gfx6"], 6067 "map": {"at": 165060, "to": "mm"}, 6068 "name": "PA_CL_VPORT_ZSCALE_5", 6069 "type_ref": "PA_CL_VPORT_ZSCALE" 6070 }, 6071 { 6072 "chips": ["gfx6"], 6073 "map": {"at": 165064, "to": "mm"}, 6074 "name": "PA_CL_VPORT_ZOFFSET_5", 6075 "type_ref": "PA_CL_VPORT_ZOFFSET" 6076 }, 6077 { 6078 "chips": ["gfx6"], 6079 "map": {"at": 165068, "to": "mm"}, 6080 "name": "PA_CL_VPORT_XSCALE_6", 6081 "type_ref": "PA_CL_VPORT_XSCALE" 6082 }, 6083 { 6084 "chips": ["gfx6"], 6085 "map": {"at": 165072, "to": "mm"}, 6086 "name": "PA_CL_VPORT_XOFFSET_6", 6087 "type_ref": "PA_CL_VPORT_XOFFSET" 6088 }, 6089 { 6090 "chips": ["gfx6"], 6091 "map": {"at": 165076, "to": "mm"}, 6092 "name": "PA_CL_VPORT_YSCALE_6", 6093 "type_ref": "PA_CL_VPORT_YSCALE" 6094 }, 6095 { 6096 "chips": ["gfx6"], 6097 "map": {"at": 165080, "to": "mm"}, 6098 "name": "PA_CL_VPORT_YOFFSET_6", 6099 "type_ref": "PA_CL_VPORT_YOFFSET" 6100 }, 6101 { 6102 "chips": ["gfx6"], 6103 "map": {"at": 165084, "to": "mm"}, 6104 "name": "PA_CL_VPORT_ZSCALE_6", 6105 "type_ref": "PA_CL_VPORT_ZSCALE" 6106 }, 6107 { 6108 "chips": ["gfx6"], 6109 "map": {"at": 165088, "to": "mm"}, 6110 "name": "PA_CL_VPORT_ZOFFSET_6", 6111 "type_ref": "PA_CL_VPORT_ZOFFSET" 6112 }, 6113 { 6114 "chips": ["gfx6"], 6115 "map": {"at": 165092, "to": "mm"}, 6116 "name": "PA_CL_VPORT_XSCALE_7", 6117 "type_ref": "PA_CL_VPORT_XSCALE" 6118 }, 6119 { 6120 "chips": ["gfx6"], 6121 "map": {"at": 165096, "to": "mm"}, 6122 "name": "PA_CL_VPORT_XOFFSET_7", 6123 "type_ref": "PA_CL_VPORT_XOFFSET" 6124 }, 6125 { 6126 "chips": ["gfx6"], 6127 "map": {"at": 165100, "to": "mm"}, 6128 "name": "PA_CL_VPORT_YSCALE_7", 6129 "type_ref": "PA_CL_VPORT_YSCALE" 6130 }, 6131 { 6132 "chips": ["gfx6"], 6133 "map": {"at": 165104, "to": "mm"}, 6134 "name": "PA_CL_VPORT_YOFFSET_7", 6135 "type_ref": "PA_CL_VPORT_YOFFSET" 6136 }, 6137 { 6138 "chips": ["gfx6"], 6139 "map": {"at": 165108, "to": "mm"}, 6140 "name": "PA_CL_VPORT_ZSCALE_7", 6141 "type_ref": "PA_CL_VPORT_ZSCALE" 6142 }, 6143 { 6144 "chips": ["gfx6"], 6145 "map": {"at": 165112, "to": "mm"}, 6146 "name": "PA_CL_VPORT_ZOFFSET_7", 6147 "type_ref": "PA_CL_VPORT_ZOFFSET" 6148 }, 6149 { 6150 "chips": ["gfx6"], 6151 "map": {"at": 165116, "to": "mm"}, 6152 "name": "PA_CL_VPORT_XSCALE_8", 6153 "type_ref": "PA_CL_VPORT_XSCALE" 6154 }, 6155 { 6156 "chips": ["gfx6"], 6157 "map": {"at": 165120, "to": "mm"}, 6158 "name": "PA_CL_VPORT_XOFFSET_8", 6159 "type_ref": "PA_CL_VPORT_XOFFSET" 6160 }, 6161 { 6162 "chips": ["gfx6"], 6163 "map": {"at": 165124, "to": "mm"}, 6164 "name": "PA_CL_VPORT_YSCALE_8", 6165 "type_ref": "PA_CL_VPORT_YSCALE" 6166 }, 6167 { 6168 "chips": ["gfx6"], 6169 "map": {"at": 165128, "to": "mm"}, 6170 "name": "PA_CL_VPORT_YOFFSET_8", 6171 "type_ref": "PA_CL_VPORT_YOFFSET" 6172 }, 6173 { 6174 "chips": ["gfx6"], 6175 "map": {"at": 165132, "to": "mm"}, 6176 "name": "PA_CL_VPORT_ZSCALE_8", 6177 "type_ref": "PA_CL_VPORT_ZSCALE" 6178 }, 6179 { 6180 "chips": ["gfx6"], 6181 "map": {"at": 165136, "to": "mm"}, 6182 "name": "PA_CL_VPORT_ZOFFSET_8", 6183 "type_ref": "PA_CL_VPORT_ZOFFSET" 6184 }, 6185 { 6186 "chips": ["gfx6"], 6187 "map": {"at": 165140, "to": "mm"}, 6188 "name": "PA_CL_VPORT_XSCALE_9", 6189 "type_ref": "PA_CL_VPORT_XSCALE" 6190 }, 6191 { 6192 "chips": ["gfx6"], 6193 "map": {"at": 165144, "to": "mm"}, 6194 "name": "PA_CL_VPORT_XOFFSET_9", 6195 "type_ref": "PA_CL_VPORT_XOFFSET" 6196 }, 6197 { 6198 "chips": ["gfx6"], 6199 "map": {"at": 165148, "to": "mm"}, 6200 "name": "PA_CL_VPORT_YSCALE_9", 6201 "type_ref": "PA_CL_VPORT_YSCALE" 6202 }, 6203 { 6204 "chips": ["gfx6"], 6205 "map": {"at": 165152, "to": "mm"}, 6206 "name": "PA_CL_VPORT_YOFFSET_9", 6207 "type_ref": "PA_CL_VPORT_YOFFSET" 6208 }, 6209 { 6210 "chips": ["gfx6"], 6211 "map": {"at": 165156, "to": "mm"}, 6212 "name": "PA_CL_VPORT_ZSCALE_9", 6213 "type_ref": "PA_CL_VPORT_ZSCALE" 6214 }, 6215 { 6216 "chips": ["gfx6"], 6217 "map": {"at": 165160, "to": "mm"}, 6218 "name": "PA_CL_VPORT_ZOFFSET_9", 6219 "type_ref": "PA_CL_VPORT_ZOFFSET" 6220 }, 6221 { 6222 "chips": ["gfx6"], 6223 "map": {"at": 165164, "to": "mm"}, 6224 "name": "PA_CL_VPORT_XSCALE_10", 6225 "type_ref": "PA_CL_VPORT_XSCALE" 6226 }, 6227 { 6228 "chips": ["gfx6"], 6229 "map": {"at": 165168, "to": "mm"}, 6230 "name": "PA_CL_VPORT_XOFFSET_10", 6231 "type_ref": "PA_CL_VPORT_XOFFSET" 6232 }, 6233 { 6234 "chips": ["gfx6"], 6235 "map": {"at": 165172, "to": "mm"}, 6236 "name": "PA_CL_VPORT_YSCALE_10", 6237 "type_ref": "PA_CL_VPORT_YSCALE" 6238 }, 6239 { 6240 "chips": ["gfx6"], 6241 "map": {"at": 165176, "to": "mm"}, 6242 "name": "PA_CL_VPORT_YOFFSET_10", 6243 "type_ref": "PA_CL_VPORT_YOFFSET" 6244 }, 6245 { 6246 "chips": ["gfx6"], 6247 "map": {"at": 165180, "to": "mm"}, 6248 "name": "PA_CL_VPORT_ZSCALE_10", 6249 "type_ref": "PA_CL_VPORT_ZSCALE" 6250 }, 6251 { 6252 "chips": ["gfx6"], 6253 "map": {"at": 165184, "to": "mm"}, 6254 "name": "PA_CL_VPORT_ZOFFSET_10", 6255 "type_ref": "PA_CL_VPORT_ZOFFSET" 6256 }, 6257 { 6258 "chips": ["gfx6"], 6259 "map": {"at": 165188, "to": "mm"}, 6260 "name": "PA_CL_VPORT_XSCALE_11", 6261 "type_ref": "PA_CL_VPORT_XSCALE" 6262 }, 6263 { 6264 "chips": ["gfx6"], 6265 "map": {"at": 165192, "to": "mm"}, 6266 "name": "PA_CL_VPORT_XOFFSET_11", 6267 "type_ref": "PA_CL_VPORT_XOFFSET" 6268 }, 6269 { 6270 "chips": ["gfx6"], 6271 "map": {"at": 165196, "to": "mm"}, 6272 "name": "PA_CL_VPORT_YSCALE_11", 6273 "type_ref": "PA_CL_VPORT_YSCALE" 6274 }, 6275 { 6276 "chips": ["gfx6"], 6277 "map": {"at": 165200, "to": "mm"}, 6278 "name": "PA_CL_VPORT_YOFFSET_11", 6279 "type_ref": "PA_CL_VPORT_YOFFSET" 6280 }, 6281 { 6282 "chips": ["gfx6"], 6283 "map": {"at": 165204, "to": "mm"}, 6284 "name": "PA_CL_VPORT_ZSCALE_11", 6285 "type_ref": "PA_CL_VPORT_ZSCALE" 6286 }, 6287 { 6288 "chips": ["gfx6"], 6289 "map": {"at": 165208, "to": "mm"}, 6290 "name": "PA_CL_VPORT_ZOFFSET_11", 6291 "type_ref": "PA_CL_VPORT_ZOFFSET" 6292 }, 6293 { 6294 "chips": ["gfx6"], 6295 "map": {"at": 165212, "to": "mm"}, 6296 "name": "PA_CL_VPORT_XSCALE_12", 6297 "type_ref": "PA_CL_VPORT_XSCALE" 6298 }, 6299 { 6300 "chips": ["gfx6"], 6301 "map": {"at": 165216, "to": "mm"}, 6302 "name": "PA_CL_VPORT_XOFFSET_12", 6303 "type_ref": "PA_CL_VPORT_XOFFSET" 6304 }, 6305 { 6306 "chips": ["gfx6"], 6307 "map": {"at": 165220, "to": "mm"}, 6308 "name": "PA_CL_VPORT_YSCALE_12", 6309 "type_ref": "PA_CL_VPORT_YSCALE" 6310 }, 6311 { 6312 "chips": ["gfx6"], 6313 "map": {"at": 165224, "to": "mm"}, 6314 "name": "PA_CL_VPORT_YOFFSET_12", 6315 "type_ref": "PA_CL_VPORT_YOFFSET" 6316 }, 6317 { 6318 "chips": ["gfx6"], 6319 "map": {"at": 165228, "to": "mm"}, 6320 "name": "PA_CL_VPORT_ZSCALE_12", 6321 "type_ref": "PA_CL_VPORT_ZSCALE" 6322 }, 6323 { 6324 "chips": ["gfx6"], 6325 "map": {"at": 165232, "to": "mm"}, 6326 "name": "PA_CL_VPORT_ZOFFSET_12", 6327 "type_ref": "PA_CL_VPORT_ZOFFSET" 6328 }, 6329 { 6330 "chips": ["gfx6"], 6331 "map": {"at": 165236, "to": "mm"}, 6332 "name": "PA_CL_VPORT_XSCALE_13", 6333 "type_ref": "PA_CL_VPORT_XSCALE" 6334 }, 6335 { 6336 "chips": ["gfx6"], 6337 "map": {"at": 165240, "to": "mm"}, 6338 "name": "PA_CL_VPORT_XOFFSET_13", 6339 "type_ref": "PA_CL_VPORT_XOFFSET" 6340 }, 6341 { 6342 "chips": ["gfx6"], 6343 "map": {"at": 165244, "to": "mm"}, 6344 "name": "PA_CL_VPORT_YSCALE_13", 6345 "type_ref": "PA_CL_VPORT_YSCALE" 6346 }, 6347 { 6348 "chips": ["gfx6"], 6349 "map": {"at": 165248, "to": "mm"}, 6350 "name": "PA_CL_VPORT_YOFFSET_13", 6351 "type_ref": "PA_CL_VPORT_YOFFSET" 6352 }, 6353 { 6354 "chips": ["gfx6"], 6355 "map": {"at": 165252, "to": "mm"}, 6356 "name": "PA_CL_VPORT_ZSCALE_13", 6357 "type_ref": "PA_CL_VPORT_ZSCALE" 6358 }, 6359 { 6360 "chips": ["gfx6"], 6361 "map": {"at": 165256, "to": "mm"}, 6362 "name": "PA_CL_VPORT_ZOFFSET_13", 6363 "type_ref": "PA_CL_VPORT_ZOFFSET" 6364 }, 6365 { 6366 "chips": ["gfx6"], 6367 "map": {"at": 165260, "to": "mm"}, 6368 "name": "PA_CL_VPORT_XSCALE_14", 6369 "type_ref": "PA_CL_VPORT_XSCALE" 6370 }, 6371 { 6372 "chips": ["gfx6"], 6373 "map": {"at": 165264, "to": "mm"}, 6374 "name": "PA_CL_VPORT_XOFFSET_14", 6375 "type_ref": "PA_CL_VPORT_XOFFSET" 6376 }, 6377 { 6378 "chips": ["gfx6"], 6379 "map": {"at": 165268, "to": "mm"}, 6380 "name": "PA_CL_VPORT_YSCALE_14", 6381 "type_ref": "PA_CL_VPORT_YSCALE" 6382 }, 6383 { 6384 "chips": ["gfx6"], 6385 "map": {"at": 165272, "to": "mm"}, 6386 "name": "PA_CL_VPORT_YOFFSET_14", 6387 "type_ref": "PA_CL_VPORT_YOFFSET" 6388 }, 6389 { 6390 "chips": ["gfx6"], 6391 "map": {"at": 165276, "to": "mm"}, 6392 "name": "PA_CL_VPORT_ZSCALE_14", 6393 "type_ref": "PA_CL_VPORT_ZSCALE" 6394 }, 6395 { 6396 "chips": ["gfx6"], 6397 "map": {"at": 165280, "to": "mm"}, 6398 "name": "PA_CL_VPORT_ZOFFSET_14", 6399 "type_ref": "PA_CL_VPORT_ZOFFSET" 6400 }, 6401 { 6402 "chips": ["gfx6"], 6403 "map": {"at": 165284, "to": "mm"}, 6404 "name": "PA_CL_VPORT_XSCALE_15", 6405 "type_ref": "PA_CL_VPORT_XSCALE" 6406 }, 6407 { 6408 "chips": ["gfx6"], 6409 "map": {"at": 165288, "to": "mm"}, 6410 "name": "PA_CL_VPORT_XOFFSET_15", 6411 "type_ref": "PA_CL_VPORT_XOFFSET" 6412 }, 6413 { 6414 "chips": ["gfx6"], 6415 "map": {"at": 165292, "to": "mm"}, 6416 "name": "PA_CL_VPORT_YSCALE_15", 6417 "type_ref": "PA_CL_VPORT_YSCALE" 6418 }, 6419 { 6420 "chips": ["gfx6"], 6421 "map": {"at": 165296, "to": "mm"}, 6422 "name": "PA_CL_VPORT_YOFFSET_15", 6423 "type_ref": "PA_CL_VPORT_YOFFSET" 6424 }, 6425 { 6426 "chips": ["gfx6"], 6427 "map": {"at": 165300, "to": "mm"}, 6428 "name": "PA_CL_VPORT_ZSCALE_15", 6429 "type_ref": "PA_CL_VPORT_ZSCALE" 6430 }, 6431 { 6432 "chips": ["gfx6"], 6433 "map": {"at": 165304, "to": "mm"}, 6434 "name": "PA_CL_VPORT_ZOFFSET_15", 6435 "type_ref": "PA_CL_VPORT_ZOFFSET" 6436 }, 6437 { 6438 "chips": ["gfx6"], 6439 "map": {"at": 165308, "to": "mm"}, 6440 "name": "PA_CL_UCP_0_X", 6441 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6442 }, 6443 { 6444 "chips": ["gfx6"], 6445 "map": {"at": 165312, "to": "mm"}, 6446 "name": "PA_CL_UCP_0_Y", 6447 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6448 }, 6449 { 6450 "chips": ["gfx6"], 6451 "map": {"at": 165316, "to": "mm"}, 6452 "name": "PA_CL_UCP_0_Z", 6453 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6454 }, 6455 { 6456 "chips": ["gfx6"], 6457 "map": {"at": 165320, "to": "mm"}, 6458 "name": "PA_CL_UCP_0_W", 6459 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6460 }, 6461 { 6462 "chips": ["gfx6"], 6463 "map": {"at": 165324, "to": "mm"}, 6464 "name": "PA_CL_UCP_1_X", 6465 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6466 }, 6467 { 6468 "chips": ["gfx6"], 6469 "map": {"at": 165328, "to": "mm"}, 6470 "name": "PA_CL_UCP_1_Y", 6471 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6472 }, 6473 { 6474 "chips": ["gfx6"], 6475 "map": {"at": 165332, "to": "mm"}, 6476 "name": "PA_CL_UCP_1_Z", 6477 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6478 }, 6479 { 6480 "chips": ["gfx6"], 6481 "map": {"at": 165336, "to": "mm"}, 6482 "name": "PA_CL_UCP_1_W", 6483 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6484 }, 6485 { 6486 "chips": ["gfx6"], 6487 "map": {"at": 165340, "to": "mm"}, 6488 "name": "PA_CL_UCP_2_X", 6489 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6490 }, 6491 { 6492 "chips": ["gfx6"], 6493 "map": {"at": 165344, "to": "mm"}, 6494 "name": "PA_CL_UCP_2_Y", 6495 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6496 }, 6497 { 6498 "chips": ["gfx6"], 6499 "map": {"at": 165348, "to": "mm"}, 6500 "name": "PA_CL_UCP_2_Z", 6501 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6502 }, 6503 { 6504 "chips": ["gfx6"], 6505 "map": {"at": 165352, "to": "mm"}, 6506 "name": "PA_CL_UCP_2_W", 6507 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6508 }, 6509 { 6510 "chips": ["gfx6"], 6511 "map": {"at": 165356, "to": "mm"}, 6512 "name": "PA_CL_UCP_3_X", 6513 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6514 }, 6515 { 6516 "chips": ["gfx6"], 6517 "map": {"at": 165360, "to": "mm"}, 6518 "name": "PA_CL_UCP_3_Y", 6519 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6520 }, 6521 { 6522 "chips": ["gfx6"], 6523 "map": {"at": 165364, "to": "mm"}, 6524 "name": "PA_CL_UCP_3_Z", 6525 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6526 }, 6527 { 6528 "chips": ["gfx6"], 6529 "map": {"at": 165368, "to": "mm"}, 6530 "name": "PA_CL_UCP_3_W", 6531 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6532 }, 6533 { 6534 "chips": ["gfx6"], 6535 "map": {"at": 165372, "to": "mm"}, 6536 "name": "PA_CL_UCP_4_X", 6537 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6538 }, 6539 { 6540 "chips": ["gfx6"], 6541 "map": {"at": 165376, "to": "mm"}, 6542 "name": "PA_CL_UCP_4_Y", 6543 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6544 }, 6545 { 6546 "chips": ["gfx6"], 6547 "map": {"at": 165380, "to": "mm"}, 6548 "name": "PA_CL_UCP_4_Z", 6549 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6550 }, 6551 { 6552 "chips": ["gfx6"], 6553 "map": {"at": 165384, "to": "mm"}, 6554 "name": "PA_CL_UCP_4_W", 6555 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6556 }, 6557 { 6558 "chips": ["gfx6"], 6559 "map": {"at": 165388, "to": "mm"}, 6560 "name": "PA_CL_UCP_5_X", 6561 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6562 }, 6563 { 6564 "chips": ["gfx6"], 6565 "map": {"at": 165392, "to": "mm"}, 6566 "name": "PA_CL_UCP_5_Y", 6567 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6568 }, 6569 { 6570 "chips": ["gfx6"], 6571 "map": {"at": 165396, "to": "mm"}, 6572 "name": "PA_CL_UCP_5_Z", 6573 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6574 }, 6575 { 6576 "chips": ["gfx6"], 6577 "map": {"at": 165400, "to": "mm"}, 6578 "name": "PA_CL_UCP_5_W", 6579 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6580 }, 6581 { 6582 "chips": ["gfx6"], 6583 "map": {"at": 165444, "to": "mm"}, 6584 "name": "SPI_PS_INPUT_CNTL_0", 6585 "type_ref": "SPI_PS_INPUT_CNTL_0" 6586 }, 6587 { 6588 "chips": ["gfx6"], 6589 "map": {"at": 165448, "to": "mm"}, 6590 "name": "SPI_PS_INPUT_CNTL_1", 6591 "type_ref": "SPI_PS_INPUT_CNTL_0" 6592 }, 6593 { 6594 "chips": ["gfx6"], 6595 "map": {"at": 165452, "to": "mm"}, 6596 "name": "SPI_PS_INPUT_CNTL_2", 6597 "type_ref": "SPI_PS_INPUT_CNTL_0" 6598 }, 6599 { 6600 "chips": ["gfx6"], 6601 "map": {"at": 165456, "to": "mm"}, 6602 "name": "SPI_PS_INPUT_CNTL_3", 6603 "type_ref": "SPI_PS_INPUT_CNTL_0" 6604 }, 6605 { 6606 "chips": ["gfx6"], 6607 "map": {"at": 165460, "to": "mm"}, 6608 "name": "SPI_PS_INPUT_CNTL_4", 6609 "type_ref": "SPI_PS_INPUT_CNTL_0" 6610 }, 6611 { 6612 "chips": ["gfx6"], 6613 "map": {"at": 165464, "to": "mm"}, 6614 "name": "SPI_PS_INPUT_CNTL_5", 6615 "type_ref": "SPI_PS_INPUT_CNTL_0" 6616 }, 6617 { 6618 "chips": ["gfx6"], 6619 "map": {"at": 165468, "to": "mm"}, 6620 "name": "SPI_PS_INPUT_CNTL_6", 6621 "type_ref": "SPI_PS_INPUT_CNTL_0" 6622 }, 6623 { 6624 "chips": ["gfx6"], 6625 "map": {"at": 165472, "to": "mm"}, 6626 "name": "SPI_PS_INPUT_CNTL_7", 6627 "type_ref": "SPI_PS_INPUT_CNTL_0" 6628 }, 6629 { 6630 "chips": ["gfx6"], 6631 "map": {"at": 165476, "to": "mm"}, 6632 "name": "SPI_PS_INPUT_CNTL_8", 6633 "type_ref": "SPI_PS_INPUT_CNTL_0" 6634 }, 6635 { 6636 "chips": ["gfx6"], 6637 "map": {"at": 165480, "to": "mm"}, 6638 "name": "SPI_PS_INPUT_CNTL_9", 6639 "type_ref": "SPI_PS_INPUT_CNTL_0" 6640 }, 6641 { 6642 "chips": ["gfx6"], 6643 "map": {"at": 165484, "to": "mm"}, 6644 "name": "SPI_PS_INPUT_CNTL_10", 6645 "type_ref": "SPI_PS_INPUT_CNTL_0" 6646 }, 6647 { 6648 "chips": ["gfx6"], 6649 "map": {"at": 165488, "to": "mm"}, 6650 "name": "SPI_PS_INPUT_CNTL_11", 6651 "type_ref": "SPI_PS_INPUT_CNTL_0" 6652 }, 6653 { 6654 "chips": ["gfx6"], 6655 "map": {"at": 165492, "to": "mm"}, 6656 "name": "SPI_PS_INPUT_CNTL_12", 6657 "type_ref": "SPI_PS_INPUT_CNTL_0" 6658 }, 6659 { 6660 "chips": ["gfx6"], 6661 "map": {"at": 165496, "to": "mm"}, 6662 "name": "SPI_PS_INPUT_CNTL_13", 6663 "type_ref": "SPI_PS_INPUT_CNTL_0" 6664 }, 6665 { 6666 "chips": ["gfx6"], 6667 "map": {"at": 165500, "to": "mm"}, 6668 "name": "SPI_PS_INPUT_CNTL_14", 6669 "type_ref": "SPI_PS_INPUT_CNTL_0" 6670 }, 6671 { 6672 "chips": ["gfx6"], 6673 "map": {"at": 165504, "to": "mm"}, 6674 "name": "SPI_PS_INPUT_CNTL_15", 6675 "type_ref": "SPI_PS_INPUT_CNTL_0" 6676 }, 6677 { 6678 "chips": ["gfx6"], 6679 "map": {"at": 165508, "to": "mm"}, 6680 "name": "SPI_PS_INPUT_CNTL_16", 6681 "type_ref": "SPI_PS_INPUT_CNTL_0" 6682 }, 6683 { 6684 "chips": ["gfx6"], 6685 "map": {"at": 165512, "to": "mm"}, 6686 "name": "SPI_PS_INPUT_CNTL_17", 6687 "type_ref": "SPI_PS_INPUT_CNTL_0" 6688 }, 6689 { 6690 "chips": ["gfx6"], 6691 "map": {"at": 165516, "to": "mm"}, 6692 "name": "SPI_PS_INPUT_CNTL_18", 6693 "type_ref": "SPI_PS_INPUT_CNTL_0" 6694 }, 6695 { 6696 "chips": ["gfx6"], 6697 "map": {"at": 165520, "to": "mm"}, 6698 "name": "SPI_PS_INPUT_CNTL_19", 6699 "type_ref": "SPI_PS_INPUT_CNTL_0" 6700 }, 6701 { 6702 "chips": ["gfx6"], 6703 "map": {"at": 165524, "to": "mm"}, 6704 "name": "SPI_PS_INPUT_CNTL_20", 6705 "type_ref": "SPI_PS_INPUT_CNTL_20" 6706 }, 6707 { 6708 "chips": ["gfx6"], 6709 "map": {"at": 165528, "to": "mm"}, 6710 "name": "SPI_PS_INPUT_CNTL_21", 6711 "type_ref": "SPI_PS_INPUT_CNTL_20" 6712 }, 6713 { 6714 "chips": ["gfx6"], 6715 "map": {"at": 165532, "to": "mm"}, 6716 "name": "SPI_PS_INPUT_CNTL_22", 6717 "type_ref": "SPI_PS_INPUT_CNTL_20" 6718 }, 6719 { 6720 "chips": ["gfx6"], 6721 "map": {"at": 165536, "to": "mm"}, 6722 "name": "SPI_PS_INPUT_CNTL_23", 6723 "type_ref": "SPI_PS_INPUT_CNTL_20" 6724 }, 6725 { 6726 "chips": ["gfx6"], 6727 "map": {"at": 165540, "to": "mm"}, 6728 "name": "SPI_PS_INPUT_CNTL_24", 6729 "type_ref": "SPI_PS_INPUT_CNTL_20" 6730 }, 6731 { 6732 "chips": ["gfx6"], 6733 "map": {"at": 165544, "to": "mm"}, 6734 "name": "SPI_PS_INPUT_CNTL_25", 6735 "type_ref": "SPI_PS_INPUT_CNTL_20" 6736 }, 6737 { 6738 "chips": ["gfx6"], 6739 "map": {"at": 165548, "to": "mm"}, 6740 "name": "SPI_PS_INPUT_CNTL_26", 6741 "type_ref": "SPI_PS_INPUT_CNTL_20" 6742 }, 6743 { 6744 "chips": ["gfx6"], 6745 "map": {"at": 165552, "to": "mm"}, 6746 "name": "SPI_PS_INPUT_CNTL_27", 6747 "type_ref": "SPI_PS_INPUT_CNTL_20" 6748 }, 6749 { 6750 "chips": ["gfx6"], 6751 "map": {"at": 165556, "to": "mm"}, 6752 "name": "SPI_PS_INPUT_CNTL_28", 6753 "type_ref": "SPI_PS_INPUT_CNTL_20" 6754 }, 6755 { 6756 "chips": ["gfx6"], 6757 "map": {"at": 165560, "to": "mm"}, 6758 "name": "SPI_PS_INPUT_CNTL_29", 6759 "type_ref": "SPI_PS_INPUT_CNTL_20" 6760 }, 6761 { 6762 "chips": ["gfx6"], 6763 "map": {"at": 165564, "to": "mm"}, 6764 "name": "SPI_PS_INPUT_CNTL_30", 6765 "type_ref": "SPI_PS_INPUT_CNTL_20" 6766 }, 6767 { 6768 "chips": ["gfx6"], 6769 "map": {"at": 165568, "to": "mm"}, 6770 "name": "SPI_PS_INPUT_CNTL_31", 6771 "type_ref": "SPI_PS_INPUT_CNTL_20" 6772 }, 6773 { 6774 "chips": ["gfx6"], 6775 "map": {"at": 165572, "to": "mm"}, 6776 "name": "SPI_VS_OUT_CONFIG", 6777 "type_ref": "SPI_VS_OUT_CONFIG" 6778 }, 6779 { 6780 "chips": ["gfx6"], 6781 "map": {"at": 165580, "to": "mm"}, 6782 "name": "SPI_PS_INPUT_ENA", 6783 "type_ref": "SPI_PS_INPUT_ADDR" 6784 }, 6785 { 6786 "chips": ["gfx6"], 6787 "map": {"at": 165584, "to": "mm"}, 6788 "name": "SPI_PS_INPUT_ADDR", 6789 "type_ref": "SPI_PS_INPUT_ADDR" 6790 }, 6791 { 6792 "chips": ["gfx6"], 6793 "map": {"at": 165588, "to": "mm"}, 6794 "name": "SPI_INTERP_CONTROL_0", 6795 "type_ref": "SPI_INTERP_CONTROL_0" 6796 }, 6797 { 6798 "chips": ["gfx6"], 6799 "map": {"at": 165592, "to": "mm"}, 6800 "name": "SPI_PS_IN_CONTROL", 6801 "type_ref": "SPI_PS_IN_CONTROL" 6802 }, 6803 { 6804 "chips": ["gfx6"], 6805 "map": {"at": 165600, "to": "mm"}, 6806 "name": "SPI_BARYC_CNTL", 6807 "type_ref": "SPI_BARYC_CNTL" 6808 }, 6809 { 6810 "chips": ["gfx6"], 6811 "map": {"at": 165608, "to": "mm"}, 6812 "name": "SPI_TMPRING_SIZE", 6813 "type_ref": "COMPUTE_TMPRING_SIZE" 6814 }, 6815 { 6816 "chips": ["gfx6"], 6817 "map": {"at": 165644, "to": "mm"}, 6818 "name": "SPI_SHADER_POS_FORMAT", 6819 "type_ref": "SPI_SHADER_POS_FORMAT" 6820 }, 6821 { 6822 "chips": ["gfx6"], 6823 "map": {"at": 165648, "to": "mm"}, 6824 "name": "SPI_SHADER_Z_FORMAT", 6825 "type_ref": "SPI_SHADER_Z_FORMAT" 6826 }, 6827 { 6828 "chips": ["gfx6"], 6829 "map": {"at": 165652, "to": "mm"}, 6830 "name": "SPI_SHADER_COL_FORMAT", 6831 "type_ref": "SPI_SHADER_COL_FORMAT" 6832 }, 6833 { 6834 "chips": ["gfx6"], 6835 "map": {"at": 165760, "to": "mm"}, 6836 "name": "CB_BLEND0_CONTROL", 6837 "type_ref": "CB_BLEND0_CONTROL" 6838 }, 6839 { 6840 "chips": ["gfx6"], 6841 "map": {"at": 165764, "to": "mm"}, 6842 "name": "CB_BLEND1_CONTROL", 6843 "type_ref": "CB_BLEND0_CONTROL" 6844 }, 6845 { 6846 "chips": ["gfx6"], 6847 "map": {"at": 165768, "to": "mm"}, 6848 "name": "CB_BLEND2_CONTROL", 6849 "type_ref": "CB_BLEND0_CONTROL" 6850 }, 6851 { 6852 "chips": ["gfx6"], 6853 "map": {"at": 165772, "to": "mm"}, 6854 "name": "CB_BLEND3_CONTROL", 6855 "type_ref": "CB_BLEND0_CONTROL" 6856 }, 6857 { 6858 "chips": ["gfx6"], 6859 "map": {"at": 165776, "to": "mm"}, 6860 "name": "CB_BLEND4_CONTROL", 6861 "type_ref": "CB_BLEND0_CONTROL" 6862 }, 6863 { 6864 "chips": ["gfx6"], 6865 "map": {"at": 165780, "to": "mm"}, 6866 "name": "CB_BLEND5_CONTROL", 6867 "type_ref": "CB_BLEND0_CONTROL" 6868 }, 6869 { 6870 "chips": ["gfx6"], 6871 "map": {"at": 165784, "to": "mm"}, 6872 "name": "CB_BLEND6_CONTROL", 6873 "type_ref": "CB_BLEND0_CONTROL" 6874 }, 6875 { 6876 "chips": ["gfx6"], 6877 "map": {"at": 165788, "to": "mm"}, 6878 "name": "CB_BLEND7_CONTROL", 6879 "type_ref": "CB_BLEND0_CONTROL" 6880 }, 6881 { 6882 "chips": ["gfx6"], 6883 "map": {"at": 165836, "to": "mm"}, 6884 "name": "CS_COPY_STATE", 6885 "type_ref": "CS_COPY_STATE" 6886 }, 6887 { 6888 "chips": ["gfx6"], 6889 "map": {"at": 165840, "to": "mm"}, 6890 "name": "GFX_COPY_STATE", 6891 "type_ref": "CS_COPY_STATE" 6892 }, 6893 { 6894 "chips": ["gfx6"], 6895 "map": {"at": 165844, "to": "mm"}, 6896 "name": "PA_CL_POINT_X_RAD", 6897 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6898 }, 6899 { 6900 "chips": ["gfx6"], 6901 "map": {"at": 165848, "to": "mm"}, 6902 "name": "PA_CL_POINT_Y_RAD", 6903 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6904 }, 6905 { 6906 "chips": ["gfx6"], 6907 "map": {"at": 165852, "to": "mm"}, 6908 "name": "PA_CL_POINT_SIZE", 6909 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6910 }, 6911 { 6912 "chips": ["gfx6"], 6913 "map": {"at": 165856, "to": "mm"}, 6914 "name": "PA_CL_POINT_CULL_RAD", 6915 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 6916 }, 6917 { 6918 "chips": ["gfx6"], 6919 "map": {"at": 165860, "to": "mm"}, 6920 "name": "VGT_DMA_BASE_HI", 6921 "type_ref": "VGT_DMA_BASE_HI" 6922 }, 6923 { 6924 "chips": ["gfx6"], 6925 "map": {"at": 165864, "to": "mm"}, 6926 "name": "VGT_DMA_BASE", 6927 "type_ref": "VGT_DMA_BASE" 6928 }, 6929 { 6930 "chips": ["gfx6"], 6931 "map": {"at": 165872, "to": "mm"}, 6932 "name": "VGT_DRAW_INITIATOR", 6933 "type_ref": "VGT_DRAW_INITIATOR" 6934 }, 6935 { 6936 "chips": ["gfx6"], 6937 "map": {"at": 165876, "to": "mm"}, 6938 "name": "VGT_IMMED_DATA", 6939 "type_ref": "SQ_WAVE_TTMP0" 6940 }, 6941 { 6942 "chips": ["gfx6"], 6943 "map": {"at": 165880, "to": "mm"}, 6944 "name": "VGT_EVENT_ADDRESS_REG", 6945 "type_ref": "VGT_EVENT_ADDRESS_REG" 6946 }, 6947 { 6948 "chips": ["gfx6"], 6949 "map": {"at": 165888, "to": "mm"}, 6950 "name": "DB_DEPTH_CONTROL", 6951 "type_ref": "DB_DEPTH_CONTROL" 6952 }, 6953 { 6954 "chips": ["gfx6"], 6955 "map": {"at": 165892, "to": "mm"}, 6956 "name": "DB_EQAA", 6957 "type_ref": "DB_EQAA" 6958 }, 6959 { 6960 "chips": ["gfx6"], 6961 "map": {"at": 165896, "to": "mm"}, 6962 "name": "CB_COLOR_CONTROL", 6963 "type_ref": "CB_COLOR_CONTROL" 6964 }, 6965 { 6966 "chips": ["gfx6"], 6967 "map": {"at": 165900, "to": "mm"}, 6968 "name": "DB_SHADER_CONTROL", 6969 "type_ref": "DB_SHADER_CONTROL" 6970 }, 6971 { 6972 "chips": ["gfx6"], 6973 "map": {"at": 165904, "to": "mm"}, 6974 "name": "PA_CL_CLIP_CNTL", 6975 "type_ref": "PA_CL_CLIP_CNTL" 6976 }, 6977 { 6978 "chips": ["gfx6"], 6979 "map": {"at": 165908, "to": "mm"}, 6980 "name": "PA_SU_SC_MODE_CNTL", 6981 "type_ref": "PA_SU_SC_MODE_CNTL" 6982 }, 6983 { 6984 "chips": ["gfx6"], 6985 "map": {"at": 165912, "to": "mm"}, 6986 "name": "PA_CL_VTE_CNTL", 6987 "type_ref": "PA_CL_VTE_CNTL" 6988 }, 6989 { 6990 "chips": ["gfx6"], 6991 "map": {"at": 165916, "to": "mm"}, 6992 "name": "PA_CL_VS_OUT_CNTL", 6993 "type_ref": "PA_CL_VS_OUT_CNTL" 6994 }, 6995 { 6996 "chips": ["gfx6"], 6997 "map": {"at": 165920, "to": "mm"}, 6998 "name": "PA_CL_NANINF_CNTL", 6999 "type_ref": "PA_CL_NANINF_CNTL" 7000 }, 7001 { 7002 "chips": ["gfx6"], 7003 "map": {"at": 165924, "to": "mm"}, 7004 "name": "PA_SU_LINE_STIPPLE_CNTL", 7005 "type_ref": "PA_SU_LINE_STIPPLE_CNTL" 7006 }, 7007 { 7008 "chips": ["gfx6"], 7009 "map": {"at": 165928, "to": "mm"}, 7010 "name": "PA_SU_LINE_STIPPLE_SCALE", 7011 "type_ref": "PA_SU_LINE_STIPPLE_SCALE" 7012 }, 7013 { 7014 "chips": ["gfx6"], 7015 "map": {"at": 165932, "to": "mm"}, 7016 "name": "PA_SU_PRIM_FILTER_CNTL", 7017 "type_ref": "PA_SU_PRIM_FILTER_CNTL" 7018 }, 7019 { 7020 "chips": ["gfx6"], 7021 "map": {"at": 166400, "to": "mm"}, 7022 "name": "PA_SU_POINT_SIZE", 7023 "type_ref": "PA_SU_POINT_SIZE" 7024 }, 7025 { 7026 "chips": ["gfx6"], 7027 "map": {"at": 166404, "to": "mm"}, 7028 "name": "PA_SU_POINT_MINMAX", 7029 "type_ref": "PA_SU_POINT_MINMAX" 7030 }, 7031 { 7032 "chips": ["gfx6"], 7033 "map": {"at": 166408, "to": "mm"}, 7034 "name": "PA_SU_LINE_CNTL", 7035 "type_ref": "PA_SU_LINE_CNTL" 7036 }, 7037 { 7038 "chips": ["gfx6"], 7039 "map": {"at": 166412, "to": "mm"}, 7040 "name": "PA_SC_LINE_STIPPLE", 7041 "type_ref": "PA_SC_LINE_STIPPLE" 7042 }, 7043 { 7044 "chips": ["gfx6"], 7045 "map": {"at": 166416, "to": "mm"}, 7046 "name": "VGT_OUTPUT_PATH_CNTL", 7047 "type_ref": "VGT_OUTPUT_PATH_CNTL" 7048 }, 7049 { 7050 "chips": ["gfx6"], 7051 "map": {"at": 166420, "to": "mm"}, 7052 "name": "VGT_HOS_CNTL", 7053 "type_ref": "VGT_HOS_CNTL" 7054 }, 7055 { 7056 "chips": ["gfx6"], 7057 "map": {"at": 166424, "to": "mm"}, 7058 "name": "VGT_HOS_MAX_TESS_LEVEL", 7059 "type_ref": "VGT_HOS_MAX_TESS_LEVEL" 7060 }, 7061 { 7062 "chips": ["gfx6"], 7063 "map": {"at": 166428, "to": "mm"}, 7064 "name": "VGT_HOS_MIN_TESS_LEVEL", 7065 "type_ref": "VGT_HOS_MIN_TESS_LEVEL" 7066 }, 7067 { 7068 "chips": ["gfx6"], 7069 "map": {"at": 166432, "to": "mm"}, 7070 "name": "VGT_HOS_REUSE_DEPTH", 7071 "type_ref": "VGT_HOS_REUSE_DEPTH" 7072 }, 7073 { 7074 "chips": ["gfx6"], 7075 "map": {"at": 166436, "to": "mm"}, 7076 "name": "VGT_GROUP_PRIM_TYPE", 7077 "type_ref": "VGT_GROUP_PRIM_TYPE" 7078 }, 7079 { 7080 "chips": ["gfx6"], 7081 "map": {"at": 166440, "to": "mm"}, 7082 "name": "VGT_GROUP_FIRST_DECR", 7083 "type_ref": "VGT_GROUP_FIRST_DECR" 7084 }, 7085 { 7086 "chips": ["gfx6"], 7087 "map": {"at": 166444, "to": "mm"}, 7088 "name": "VGT_GROUP_DECR", 7089 "type_ref": "VGT_GROUP_DECR" 7090 }, 7091 { 7092 "chips": ["gfx6"], 7093 "map": {"at": 166448, "to": "mm"}, 7094 "name": "VGT_GROUP_VECT_0_CNTL", 7095 "type_ref": "VGT_GROUP_VECT_0_CNTL" 7096 }, 7097 { 7098 "chips": ["gfx6"], 7099 "map": {"at": 166452, "to": "mm"}, 7100 "name": "VGT_GROUP_VECT_1_CNTL", 7101 "type_ref": "VGT_GROUP_VECT_0_CNTL" 7102 }, 7103 { 7104 "chips": ["gfx6"], 7105 "map": {"at": 166456, "to": "mm"}, 7106 "name": "VGT_GROUP_VECT_0_FMT_CNTL", 7107 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 7108 }, 7109 { 7110 "chips": ["gfx6"], 7111 "map": {"at": 166460, "to": "mm"}, 7112 "name": "VGT_GROUP_VECT_1_FMT_CNTL", 7113 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 7114 }, 7115 { 7116 "chips": ["gfx6"], 7117 "map": {"at": 166464, "to": "mm"}, 7118 "name": "VGT_GS_MODE", 7119 "type_ref": "VGT_GS_MODE" 7120 }, 7121 { 7122 "chips": ["gfx6"], 7123 "map": {"at": 166472, "to": "mm"}, 7124 "name": "PA_SC_MODE_CNTL_0", 7125 "type_ref": "PA_SC_MODE_CNTL_0" 7126 }, 7127 { 7128 "chips": ["gfx6"], 7129 "map": {"at": 166476, "to": "mm"}, 7130 "name": "PA_SC_MODE_CNTL_1", 7131 "type_ref": "PA_SC_MODE_CNTL_1" 7132 }, 7133 { 7134 "chips": ["gfx6"], 7135 "map": {"at": 166480, "to": "mm"}, 7136 "name": "VGT_ENHANCE", 7137 "type_ref": "IA_ENHANCE" 7138 }, 7139 { 7140 "chips": ["gfx6"], 7141 "map": {"at": 166484, "to": "mm"}, 7142 "name": "VGT_GS_PER_ES", 7143 "type_ref": "VGT_GS_PER_ES" 7144 }, 7145 { 7146 "chips": ["gfx6"], 7147 "map": {"at": 166488, "to": "mm"}, 7148 "name": "VGT_ES_PER_GS", 7149 "type_ref": "VGT_ES_PER_GS" 7150 }, 7151 { 7152 "chips": ["gfx6"], 7153 "map": {"at": 166492, "to": "mm"}, 7154 "name": "VGT_GS_PER_VS", 7155 "type_ref": "VGT_GS_PER_VS" 7156 }, 7157 { 7158 "chips": ["gfx6"], 7159 "map": {"at": 166496, "to": "mm"}, 7160 "name": "VGT_GSVS_RING_OFFSET_1", 7161 "type_ref": "VGT_GSVS_RING_OFFSET_1" 7162 }, 7163 { 7164 "chips": ["gfx6"], 7165 "map": {"at": 166500, "to": "mm"}, 7166 "name": "VGT_GSVS_RING_OFFSET_2", 7167 "type_ref": "VGT_GSVS_RING_OFFSET_1" 7168 }, 7169 { 7170 "chips": ["gfx6"], 7171 "map": {"at": 166504, "to": "mm"}, 7172 "name": "VGT_GSVS_RING_OFFSET_3", 7173 "type_ref": "VGT_GSVS_RING_OFFSET_1" 7174 }, 7175 { 7176 "chips": ["gfx6"], 7177 "map": {"at": 166508, "to": "mm"}, 7178 "name": "VGT_GS_OUT_PRIM_TYPE", 7179 "type_ref": "VGT_GS_OUT_PRIM_TYPE" 7180 }, 7181 { 7182 "chips": ["gfx6"], 7183 "map": {"at": 166512, "to": "mm"}, 7184 "name": "IA_ENHANCE", 7185 "type_ref": "IA_ENHANCE" 7186 }, 7187 { 7188 "chips": ["gfx6"], 7189 "map": {"at": 166516, "to": "mm"}, 7190 "name": "VGT_DMA_SIZE", 7191 "type_ref": "VGT_DMA_SIZE" 7192 }, 7193 { 7194 "chips": ["gfx6"], 7195 "map": {"at": 166520, "to": "mm"}, 7196 "name": "VGT_DMA_MAX_SIZE", 7197 "type_ref": "VGT_DMA_MAX_SIZE" 7198 }, 7199 { 7200 "chips": ["gfx6"], 7201 "map": {"at": 166524, "to": "mm"}, 7202 "name": "VGT_DMA_INDEX_TYPE", 7203 "type_ref": "VGT_DMA_INDEX_TYPE" 7204 }, 7205 { 7206 "chips": ["gfx6"], 7207 "map": {"at": 166532, "to": "mm"}, 7208 "name": "VGT_PRIMITIVEID_EN", 7209 "type_ref": "VGT_PRIMITIVEID_EN" 7210 }, 7211 { 7212 "chips": ["gfx6"], 7213 "map": {"at": 166536, "to": "mm"}, 7214 "name": "VGT_DMA_NUM_INSTANCES", 7215 "type_ref": "VGT_DMA_NUM_INSTANCES" 7216 }, 7217 { 7218 "chips": ["gfx6"], 7219 "map": {"at": 166540, "to": "mm"}, 7220 "name": "VGT_PRIMITIVEID_RESET", 7221 "type_ref": "VGT_PRIMITIVEID_RESET" 7222 }, 7223 { 7224 "chips": ["gfx6"], 7225 "map": {"at": 166544, "to": "mm"}, 7226 "name": "VGT_EVENT_INITIATOR", 7227 "type_ref": "VGT_EVENT_INITIATOR" 7228 }, 7229 { 7230 "chips": ["gfx6"], 7231 "map": {"at": 166548, "to": "mm"}, 7232 "name": "VGT_MULTI_PRIM_IB_RESET_EN", 7233 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 7234 }, 7235 { 7236 "chips": ["gfx6"], 7237 "map": {"at": 166560, "to": "mm"}, 7238 "name": "VGT_INSTANCE_STEP_RATE_0", 7239 "type_ref": "VGT_INSTANCE_STEP_RATE_0" 7240 }, 7241 { 7242 "chips": ["gfx6"], 7243 "map": {"at": 166564, "to": "mm"}, 7244 "name": "VGT_INSTANCE_STEP_RATE_1", 7245 "type_ref": "VGT_INSTANCE_STEP_RATE_0" 7246 }, 7247 { 7248 "chips": ["gfx6"], 7249 "map": {"at": 166568, "to": "mm"}, 7250 "name": "IA_MULTI_VGT_PARAM", 7251 "type_ref": "IA_MULTI_VGT_PARAM" 7252 }, 7253 { 7254 "chips": ["gfx6"], 7255 "map": {"at": 166572, "to": "mm"}, 7256 "name": "VGT_ESGS_RING_ITEMSIZE", 7257 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7258 }, 7259 { 7260 "chips": ["gfx6"], 7261 "map": {"at": 166576, "to": "mm"}, 7262 "name": "VGT_GSVS_RING_ITEMSIZE", 7263 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7264 }, 7265 { 7266 "chips": ["gfx6"], 7267 "map": {"at": 166580, "to": "mm"}, 7268 "name": "VGT_REUSE_OFF", 7269 "type_ref": "VGT_REUSE_OFF" 7270 }, 7271 { 7272 "chips": ["gfx6"], 7273 "map": {"at": 166584, "to": "mm"}, 7274 "name": "VGT_VTX_CNT_EN", 7275 "type_ref": "VGT_VTX_CNT_EN" 7276 }, 7277 { 7278 "chips": ["gfx6"], 7279 "map": {"at": 166588, "to": "mm"}, 7280 "name": "DB_HTILE_SURFACE", 7281 "type_ref": "DB_HTILE_SURFACE" 7282 }, 7283 { 7284 "chips": ["gfx6"], 7285 "map": {"at": 166592, "to": "mm"}, 7286 "name": "DB_SRESULTS_COMPARE_STATE0", 7287 "type_ref": "DB_SRESULTS_COMPARE_STATE0" 7288 }, 7289 { 7290 "chips": ["gfx6"], 7291 "map": {"at": 166596, "to": "mm"}, 7292 "name": "DB_SRESULTS_COMPARE_STATE1", 7293 "type_ref": "DB_SRESULTS_COMPARE_STATE1" 7294 }, 7295 { 7296 "chips": ["gfx6"], 7297 "map": {"at": 166600, "to": "mm"}, 7298 "name": "DB_PRELOAD_CONTROL", 7299 "type_ref": "DB_PRELOAD_CONTROL" 7300 }, 7301 { 7302 "chips": ["gfx6"], 7303 "map": {"at": 166608, "to": "mm"}, 7304 "name": "VGT_STRMOUT_BUFFER_SIZE_0", 7305 "type_ref": "COMPUTE_DIM_X" 7306 }, 7307 { 7308 "chips": ["gfx6"], 7309 "map": {"at": 166612, "to": "mm"}, 7310 "name": "VGT_STRMOUT_VTX_STRIDE_0", 7311 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 7312 }, 7313 { 7314 "chips": ["gfx6"], 7315 "map": {"at": 166620, "to": "mm"}, 7316 "name": "VGT_STRMOUT_BUFFER_OFFSET_0", 7317 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7318 }, 7319 { 7320 "chips": ["gfx6"], 7321 "map": {"at": 166624, "to": "mm"}, 7322 "name": "VGT_STRMOUT_BUFFER_SIZE_1", 7323 "type_ref": "COMPUTE_DIM_X" 7324 }, 7325 { 7326 "chips": ["gfx6"], 7327 "map": {"at": 166628, "to": "mm"}, 7328 "name": "VGT_STRMOUT_VTX_STRIDE_1", 7329 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 7330 }, 7331 { 7332 "chips": ["gfx6"], 7333 "map": {"at": 166636, "to": "mm"}, 7334 "name": "VGT_STRMOUT_BUFFER_OFFSET_1", 7335 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7336 }, 7337 { 7338 "chips": ["gfx6"], 7339 "map": {"at": 166640, "to": "mm"}, 7340 "name": "VGT_STRMOUT_BUFFER_SIZE_2", 7341 "type_ref": "COMPUTE_DIM_X" 7342 }, 7343 { 7344 "chips": ["gfx6"], 7345 "map": {"at": 166644, "to": "mm"}, 7346 "name": "VGT_STRMOUT_VTX_STRIDE_2", 7347 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 7348 }, 7349 { 7350 "chips": ["gfx6"], 7351 "map": {"at": 166652, "to": "mm"}, 7352 "name": "VGT_STRMOUT_BUFFER_OFFSET_2", 7353 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7354 }, 7355 { 7356 "chips": ["gfx6"], 7357 "map": {"at": 166656, "to": "mm"}, 7358 "name": "VGT_STRMOUT_BUFFER_SIZE_3", 7359 "type_ref": "COMPUTE_DIM_X" 7360 }, 7361 { 7362 "chips": ["gfx6"], 7363 "map": {"at": 166660, "to": "mm"}, 7364 "name": "VGT_STRMOUT_VTX_STRIDE_3", 7365 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 7366 }, 7367 { 7368 "chips": ["gfx6"], 7369 "map": {"at": 166668, "to": "mm"}, 7370 "name": "VGT_STRMOUT_BUFFER_OFFSET_3", 7371 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7372 }, 7373 { 7374 "chips": ["gfx6"], 7375 "map": {"at": 166696, "to": "mm"}, 7376 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET", 7377 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7378 }, 7379 { 7380 "chips": ["gfx6"], 7381 "map": {"at": 166700, "to": "mm"}, 7382 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", 7383 "type_ref": "COMPUTE_DIM_X" 7384 }, 7385 { 7386 "chips": ["gfx6"], 7387 "map": {"at": 166704, "to": "mm"}, 7388 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", 7389 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE" 7390 }, 7391 { 7392 "chips": ["gfx6"], 7393 "map": {"at": 166712, "to": "mm"}, 7394 "name": "VGT_GS_MAX_VERT_OUT", 7395 "type_ref": "VGT_GS_MAX_VERT_OUT" 7396 }, 7397 { 7398 "chips": ["gfx6"], 7399 "map": {"at": 166740, "to": "mm"}, 7400 "name": "VGT_SHADER_STAGES_EN", 7401 "type_ref": "VGT_SHADER_STAGES_EN" 7402 }, 7403 { 7404 "chips": ["gfx6"], 7405 "map": {"at": 166744, "to": "mm"}, 7406 "name": "VGT_LS_HS_CONFIG", 7407 "type_ref": "VGT_LS_HS_CONFIG" 7408 }, 7409 { 7410 "chips": ["gfx6"], 7411 "map": {"at": 166748, "to": "mm"}, 7412 "name": "VGT_GS_VERT_ITEMSIZE", 7413 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7414 }, 7415 { 7416 "chips": ["gfx6"], 7417 "map": {"at": 166752, "to": "mm"}, 7418 "name": "VGT_GS_VERT_ITEMSIZE_1", 7419 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7420 }, 7421 { 7422 "chips": ["gfx6"], 7423 "map": {"at": 166756, "to": "mm"}, 7424 "name": "VGT_GS_VERT_ITEMSIZE_2", 7425 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7426 }, 7427 { 7428 "chips": ["gfx6"], 7429 "map": {"at": 166760, "to": "mm"}, 7430 "name": "VGT_GS_VERT_ITEMSIZE_3", 7431 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 7432 }, 7433 { 7434 "chips": ["gfx6"], 7435 "map": {"at": 166764, "to": "mm"}, 7436 "name": "VGT_TF_PARAM", 7437 "type_ref": "VGT_TF_PARAM" 7438 }, 7439 { 7440 "chips": ["gfx6"], 7441 "map": {"at": 166768, "to": "mm"}, 7442 "name": "DB_ALPHA_TO_MASK", 7443 "type_ref": "DB_ALPHA_TO_MASK" 7444 }, 7445 { 7446 "chips": ["gfx6"], 7447 "map": {"at": 166776, "to": "mm"}, 7448 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL", 7449 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL" 7450 }, 7451 { 7452 "chips": ["gfx6"], 7453 "map": {"at": 166780, "to": "mm"}, 7454 "name": "PA_SU_POLY_OFFSET_CLAMP", 7455 "type_ref": "PA_SU_POLY_OFFSET_CLAMP" 7456 }, 7457 { 7458 "chips": ["gfx6"], 7459 "map": {"at": 166784, "to": "mm"}, 7460 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE", 7461 "type_ref": "PA_SU_POLY_OFFSET_BACK_SCALE" 7462 }, 7463 { 7464 "chips": ["gfx6"], 7465 "map": {"at": 166788, "to": "mm"}, 7466 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET", 7467 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7468 }, 7469 { 7470 "chips": ["gfx6"], 7471 "map": {"at": 166792, "to": "mm"}, 7472 "name": "PA_SU_POLY_OFFSET_BACK_SCALE", 7473 "type_ref": "PA_SU_POLY_OFFSET_BACK_SCALE" 7474 }, 7475 { 7476 "chips": ["gfx6"], 7477 "map": {"at": 166796, "to": "mm"}, 7478 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET", 7479 "type_ref": "PA_SU_POLY_OFFSET_BACK_OFFSET" 7480 }, 7481 { 7482 "chips": ["gfx6"], 7483 "map": {"at": 166800, "to": "mm"}, 7484 "name": "VGT_GS_INSTANCE_CNT", 7485 "type_ref": "VGT_GS_INSTANCE_CNT" 7486 }, 7487 { 7488 "chips": ["gfx6"], 7489 "map": {"at": 166804, "to": "mm"}, 7490 "name": "VGT_STRMOUT_CONFIG", 7491 "type_ref": "VGT_STRMOUT_CONFIG" 7492 }, 7493 { 7494 "chips": ["gfx6"], 7495 "map": {"at": 166808, "to": "mm"}, 7496 "name": "VGT_STRMOUT_BUFFER_CONFIG", 7497 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG" 7498 }, 7499 { 7500 "chips": ["gfx6"], 7501 "map": {"at": 166868, "to": "mm"}, 7502 "name": "PA_SC_CENTROID_PRIORITY_0", 7503 "type_ref": "PA_SC_CENTROID_PRIORITY_0" 7504 }, 7505 { 7506 "chips": ["gfx6"], 7507 "map": {"at": 166872, "to": "mm"}, 7508 "name": "PA_SC_CENTROID_PRIORITY_1", 7509 "type_ref": "PA_SC_CENTROID_PRIORITY_1" 7510 }, 7511 { 7512 "chips": ["gfx6"], 7513 "map": {"at": 166876, "to": "mm"}, 7514 "name": "PA_SC_LINE_CNTL", 7515 "type_ref": "PA_SC_LINE_CNTL" 7516 }, 7517 { 7518 "chips": ["gfx6"], 7519 "map": {"at": 166880, "to": "mm"}, 7520 "name": "PA_SC_AA_CONFIG", 7521 "type_ref": "PA_SC_AA_CONFIG" 7522 }, 7523 { 7524 "chips": ["gfx6"], 7525 "map": {"at": 166884, "to": "mm"}, 7526 "name": "PA_SU_VTX_CNTL", 7527 "type_ref": "PA_SU_VTX_CNTL" 7528 }, 7529 { 7530 "chips": ["gfx6"], 7531 "map": {"at": 166888, "to": "mm"}, 7532 "name": "PA_CL_GB_VERT_CLIP_ADJ", 7533 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 7534 }, 7535 { 7536 "chips": ["gfx6"], 7537 "map": {"at": 166892, "to": "mm"}, 7538 "name": "PA_CL_GB_VERT_DISC_ADJ", 7539 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 7540 }, 7541 { 7542 "chips": ["gfx6"], 7543 "map": {"at": 166896, "to": "mm"}, 7544 "name": "PA_CL_GB_HORZ_CLIP_ADJ", 7545 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 7546 }, 7547 { 7548 "chips": ["gfx6"], 7549 "map": {"at": 166900, "to": "mm"}, 7550 "name": "PA_CL_GB_HORZ_DISC_ADJ", 7551 "type_ref": "PA_CL_GB_HORZ_CLIP_ADJ" 7552 }, 7553 { 7554 "chips": ["gfx6"], 7555 "map": {"at": 166904, "to": "mm"}, 7556 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", 7557 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7558 }, 7559 { 7560 "chips": ["gfx6"], 7561 "map": {"at": 166908, "to": "mm"}, 7562 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", 7563 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7564 }, 7565 { 7566 "chips": ["gfx6"], 7567 "map": {"at": 166912, "to": "mm"}, 7568 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", 7569 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7570 }, 7571 { 7572 "chips": ["gfx6"], 7573 "map": {"at": 166916, "to": "mm"}, 7574 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", 7575 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7576 }, 7577 { 7578 "chips": ["gfx6"], 7579 "map": {"at": 166920, "to": "mm"}, 7580 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", 7581 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7582 }, 7583 { 7584 "chips": ["gfx6"], 7585 "map": {"at": 166924, "to": "mm"}, 7586 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", 7587 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7588 }, 7589 { 7590 "chips": ["gfx6"], 7591 "map": {"at": 166928, "to": "mm"}, 7592 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", 7593 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7594 }, 7595 { 7596 "chips": ["gfx6"], 7597 "map": {"at": 166932, "to": "mm"}, 7598 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", 7599 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7600 }, 7601 { 7602 "chips": ["gfx6"], 7603 "map": {"at": 166936, "to": "mm"}, 7604 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", 7605 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7606 }, 7607 { 7608 "chips": ["gfx6"], 7609 "map": {"at": 166940, "to": "mm"}, 7610 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", 7611 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7612 }, 7613 { 7614 "chips": ["gfx6"], 7615 "map": {"at": 166944, "to": "mm"}, 7616 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", 7617 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7618 }, 7619 { 7620 "chips": ["gfx6"], 7621 "map": {"at": 166948, "to": "mm"}, 7622 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", 7623 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7624 }, 7625 { 7626 "chips": ["gfx6"], 7627 "map": {"at": 166952, "to": "mm"}, 7628 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", 7629 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7630 }, 7631 { 7632 "chips": ["gfx6"], 7633 "map": {"at": 166956, "to": "mm"}, 7634 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", 7635 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7636 }, 7637 { 7638 "chips": ["gfx6"], 7639 "map": {"at": 166960, "to": "mm"}, 7640 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", 7641 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7642 }, 7643 { 7644 "chips": ["gfx6"], 7645 "map": {"at": 166964, "to": "mm"}, 7646 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", 7647 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7648 }, 7649 { 7650 "chips": ["gfx6"], 7651 "map": {"at": 166968, "to": "mm"}, 7652 "name": "PA_SC_AA_MASK_X0Y0_X1Y0", 7653 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0" 7654 }, 7655 { 7656 "chips": ["gfx6"], 7657 "map": {"at": 166972, "to": "mm"}, 7658 "name": "PA_SC_AA_MASK_X0Y1_X1Y1", 7659 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1" 7660 }, 7661 { 7662 "chips": ["gfx6"], 7663 "map": {"at": 167000, "to": "mm"}, 7664 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL", 7665 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL" 7666 }, 7667 { 7668 "chips": ["gfx6"], 7669 "map": {"at": 167004, "to": "mm"}, 7670 "name": "VGT_OUT_DEALLOC_CNTL", 7671 "type_ref": "VGT_OUT_DEALLOC_CNTL" 7672 }, 7673 { 7674 "chips": ["gfx6"], 7675 "map": {"at": 167008, "to": "mm"}, 7676 "name": "CB_COLOR0_BASE", 7677 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"chips": ["gfx6"], 7879 "map": {"at": 167172, "to": "mm"}, 7880 "name": "CB_COLOR2_CLEAR_WORD0", 7881 "type_ref": "CB_COLOR0_CLEAR_WORD0" 7882 }, 7883 { 7884 "chips": ["gfx6"], 7885 "map": {"at": 167176, "to": "mm"}, 7886 "name": "CB_COLOR2_CLEAR_WORD1", 7887 "type_ref": "CB_COLOR0_CLEAR_WORD1" 7888 }, 7889 { 7890 "chips": ["gfx6"], 7891 "map": {"at": 167188, "to": "mm"}, 7892 "name": "CB_COLOR3_BASE", 7893 "type_ref": "CB_COLOR0_BASE" 7894 }, 7895 { 7896 "chips": ["gfx6"], 7897 "map": {"at": 167192, "to": "mm"}, 7898 "name": "CB_COLOR3_PITCH", 7899 "type_ref": "CB_COLOR0_PITCH" 7900 }, 7901 { 7902 "chips": ["gfx6"], 7903 "map": {"at": 167196, "to": "mm"}, 7904 "name": "CB_COLOR3_SLICE", 7905 "type_ref": "CB_COLOR0_FMASK_SLICE" 7906 }, 7907 { 7908 "chips": ["gfx6"], 7909 "map": {"at": 167200, "to": "mm"}, 7910 "name": "CB_COLOR3_VIEW", 7911 "type_ref": "CB_COLOR0_VIEW" 7912 }, 7913 { 7914 "chips": ["gfx6"], 7915 "map": {"at": 167204, "to": "mm"}, 7916 "name": "CB_COLOR3_INFO", 7917 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167236, "to": "mm"}, 7958 "name": "CB_COLOR3_CLEAR_WORD1", 7959 "type_ref": "CB_COLOR0_CLEAR_WORD1" 7960 }, 7961 { 7962 "chips": ["gfx6"], 7963 "map": {"at": 167248, "to": "mm"}, 7964 "name": "CB_COLOR4_BASE", 7965 "type_ref": "CB_COLOR0_BASE" 7966 }, 7967 { 7968 "chips": ["gfx6"], 7969 "map": {"at": 167252, "to": "mm"}, 7970 "name": "CB_COLOR4_PITCH", 7971 "type_ref": "CB_COLOR0_PITCH" 7972 }, 7973 { 7974 "chips": ["gfx6"], 7975 "map": {"at": 167256, "to": "mm"}, 7976 "name": "CB_COLOR4_SLICE", 7977 "type_ref": "CB_COLOR0_FMASK_SLICE" 7978 }, 7979 { 7980 "chips": ["gfx6"], 7981 "map": {"at": 167260, "to": "mm"}, 7982 "name": "CB_COLOR4_VIEW", 7983 "type_ref": "CB_COLOR0_VIEW" 7984 }, 7985 { 7986 "chips": ["gfx6"], 7987 "map": {"at": 167264, "to": "mm"}, 7988 "name": "CB_COLOR4_INFO", 7989 "type_ref": "CB_COLOR0_INFO" 7990 }, 7991 { 7992 "chips": ["gfx6"], 7993 "map": {"at": 167268, "to": "mm"}, 7994 "name": "CB_COLOR4_ATTRIB", 7995 "type_ref": "CB_COLOR0_ATTRIB" 7996 }, 7997 { 7998 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"to": "mm"}, 8078 "name": "CB_COLOR5_CMASK_SLICE", 8079 "type_ref": "CB_COLOR0_CMASK_SLICE" 8080 }, 8081 { 8082 "chips": ["gfx6"], 8083 "map": {"at": 167344, "to": "mm"}, 8084 "name": "CB_COLOR5_FMASK", 8085 "type_ref": "CB_COLOR0_BASE" 8086 }, 8087 { 8088 "chips": ["gfx6"], 8089 "map": {"at": 167348, "to": "mm"}, 8090 "name": "CB_COLOR5_FMASK_SLICE", 8091 "type_ref": "CB_COLOR0_FMASK_SLICE" 8092 }, 8093 { 8094 "chips": ["gfx6"], 8095 "map": {"at": 167352, "to": "mm"}, 8096 "name": "CB_COLOR5_CLEAR_WORD0", 8097 "type_ref": "CB_COLOR0_CLEAR_WORD0" 8098 }, 8099 { 8100 "chips": ["gfx6"], 8101 "map": {"at": 167356, "to": "mm"}, 8102 "name": "CB_COLOR5_CLEAR_WORD1", 8103 "type_ref": "CB_COLOR0_CLEAR_WORD1" 8104 }, 8105 { 8106 "chips": ["gfx6"], 8107 "map": {"at": 167368, "to": "mm"}, 8108 "name": "CB_COLOR6_BASE", 8109 "type_ref": "CB_COLOR0_BASE" 8110 }, 8111 { 8112 "chips": ["gfx6"], 8113 "map": {"at": 167372, "to": "mm"}, 8114 "name": "CB_COLOR6_PITCH", 8115 "type_ref": "CB_COLOR0_PITCH" 8116 }, 8117 { 8118 "chips": ["gfx6"], 8119 "map": {"at": 167376, "to": "mm"}, 8120 "name": "CB_COLOR6_SLICE", 8121 "type_ref": "CB_COLOR0_FMASK_SLICE" 8122 }, 8123 { 8124 "chips": ["gfx6"], 8125 "map": {"at": 167380, "to": "mm"}, 8126 "name": "CB_COLOR6_VIEW", 8127 "type_ref": "CB_COLOR0_VIEW" 8128 }, 8129 { 8130 "chips": ["gfx6"], 8131 "map": {"at": 167384, "to": "mm"}, 8132 "name": "CB_COLOR6_INFO", 8133 "type_ref": "CB_COLOR0_INFO" 8134 }, 8135 { 8136 "chips": ["gfx6"], 8137 "map": {"at": 167388, "to": "mm"}, 8138 "name": "CB_COLOR6_ATTRIB", 8139 "type_ref": "CB_COLOR0_ATTRIB" 8140 }, 8141 { 8142 "chips": ["gfx6"], 8143 "map": {"at": 167396, "to": "mm"}, 8144 "name": "CB_COLOR6_CMASK", 8145 "type_ref": "CB_COLOR0_BASE" 8146 }, 8147 { 8148 "chips": ["gfx6"], 8149 "map": {"at": 167400, "to": "mm"}, 8150 "name": "CB_COLOR6_CMASK_SLICE", 8151 "type_ref": "CB_COLOR0_CMASK_SLICE" 8152 }, 8153 { 8154 "chips": ["gfx6"], 8155 "map": {"at": 167404, "to": "mm"}, 8156 "name": "CB_COLOR6_FMASK", 8157 "type_ref": "CB_COLOR0_BASE" 8158 }, 8159 { 8160 "chips": ["gfx6"], 8161 "map": {"at": 167408, "to": "mm"}, 8162 "name": "CB_COLOR6_FMASK_SLICE", 8163 "type_ref": "CB_COLOR0_FMASK_SLICE" 8164 }, 8165 { 8166 "chips": ["gfx6"], 8167 "map": {"at": 167412, "to": "mm"}, 8168 "name": "CB_COLOR6_CLEAR_WORD0", 8169 "type_ref": "CB_COLOR0_CLEAR_WORD0" 8170 }, 8171 { 8172 "chips": ["gfx6"], 8173 "map": {"at": 167416, "to": "mm"}, 8174 "name": "CB_COLOR6_CLEAR_WORD1", 8175 "type_ref": "CB_COLOR0_CLEAR_WORD1" 8176 }, 8177 { 8178 "chips": ["gfx6"], 8179 "map": {"at": 167428, "to": "mm"}, 8180 "name": "CB_COLOR7_BASE", 8181 "type_ref": "CB_COLOR0_BASE" 8182 }, 8183 { 8184 "chips": ["gfx6"], 8185 "map": {"at": 167432, "to": "mm"}, 8186 "name": "CB_COLOR7_PITCH", 8187 "type_ref": "CB_COLOR0_PITCH" 8188 }, 8189 { 8190 "chips": ["gfx6"], 8191 "map": {"at": 167436, "to": "mm"}, 8192 "name": "CB_COLOR7_SLICE", 8193 "type_ref": "CB_COLOR0_FMASK_SLICE" 8194 }, 8195 { 8196 "chips": ["gfx6"], 8197 "map": {"at": 167440, "to": "mm"}, 8198 "name": "CB_COLOR7_VIEW", 8199 "type_ref": "CB_COLOR0_VIEW" 8200 }, 8201 { 8202 "chips": ["gfx6"], 8203 "map": {"at": 167444, "to": "mm"}, 8204 "name": "CB_COLOR7_INFO", 8205 "type_ref": "CB_COLOR0_INFO" 8206 }, 8207 { 8208 "chips": ["gfx6"], 8209 "map": {"at": 167448, "to": "mm"}, 8210 "name": "CB_COLOR7_ATTRIB", 8211 "type_ref": "CB_COLOR0_ATTRIB" 8212 }, 8213 { 8214 "chips": ["gfx6"], 8215 "map": {"at": 167456, "to": "mm"}, 8216 "name": "CB_COLOR7_CMASK", 8217 "type_ref": "CB_COLOR0_BASE" 8218 }, 8219 { 8220 "chips": ["gfx6"], 8221 "map": {"at": 167460, "to": "mm"}, 8222 "name": "CB_COLOR7_CMASK_SLICE", 8223 "type_ref": "CB_COLOR0_CMASK_SLICE" 8224 }, 8225 { 8226 "chips": ["gfx6"], 8227 "map": {"at": 167464, "to": "mm"}, 8228 "name": "CB_COLOR7_FMASK", 8229 "type_ref": "CB_COLOR0_BASE" 8230 }, 8231 { 8232 "chips": ["gfx6"], 8233 "map": {"at": 167468, "to": "mm"}, 8234 "name": "CB_COLOR7_FMASK_SLICE", 8235 "type_ref": "CB_COLOR0_FMASK_SLICE" 8236 }, 8237 { 8238 "chips": ["gfx6"], 8239 "map": {"at": 167472, "to": "mm"}, 8240 "name": "CB_COLOR7_CLEAR_WORD0", 8241 "type_ref": "CB_COLOR0_CLEAR_WORD0" 8242 }, 8243 { 8244 "chips": ["gfx6"], 8245 "map": {"at": 167476, "to": "mm"}, 8246 "name": "CB_COLOR7_CLEAR_WORD1", 8247 "type_ref": "CB_COLOR0_CLEAR_WORD1" 8248 } 8249 ], 8250 "register_types": { 8251 "CB_BLEND0_CONTROL": { 8252 "fields": [ 8253 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, 8254 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, 8255 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, 8256 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, 8257 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, 8258 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, 8259 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, 8260 {"bits": [30, 30], "name": "ENABLE"}, 8261 {"bits": [31, 31], "name": "DISABLE_ROP3"} 8262 ] 8263 }, 8264 "CB_BLEND_ALPHA": { 8265 "fields": [ 8266 {"bits": [0, 31], "name": "BLEND_ALPHA"} 8267 ] 8268 }, 8269 "CB_BLEND_BLUE": { 8270 "fields": [ 8271 {"bits": [0, 31], "name": "BLEND_BLUE"} 8272 ] 8273 }, 8274 "CB_BLEND_GREEN": { 8275 "fields": [ 8276 {"bits": [0, 31], "name": "BLEND_GREEN"} 8277 ] 8278 }, 8279 "CB_BLEND_RED": { 8280 "fields": [ 8281 {"bits": [0, 31], "name": "BLEND_RED"} 8282 ] 8283 }, 8284 "CB_COLOR0_ATTRIB": { 8285 "fields": [ 8286 {"bits": [0, 4], "name": "TILE_MODE_INDEX"}, 8287 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, 8288 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, 8289 {"bits": [12, 14], "name": "NUM_SAMPLES"}, 8290 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, 8291 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} 8292 ] 8293 }, 8294 "CB_COLOR0_BASE": { 8295 "fields": [ 8296 {"bits": [0, 31], "name": "BASE_256B"} 8297 ] 8298 }, 8299 "CB_COLOR0_CLEAR_WORD0": { 8300 "fields": [ 8301 {"bits": [0, 31], "name": "CLEAR_WORD0"} 8302 ] 8303 }, 8304 "CB_COLOR0_CLEAR_WORD1": { 8305 "fields": [ 8306 {"bits": [0, 31], "name": "CLEAR_WORD1"} 8307 ] 8308 }, 8309 "CB_COLOR0_CMASK_SLICE": { 8310 "fields": [ 8311 {"bits": [0, 13], "name": "TILE_MAX"} 8312 ] 8313 }, 8314 "CB_COLOR0_FMASK_SLICE": { 8315 "fields": [ 8316 {"bits": [0, 21], "name": "TILE_MAX"} 8317 ] 8318 }, 8319 "CB_COLOR0_INFO": { 8320 "fields": [ 8321 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, 8322 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, 8323 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, 8324 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, 8325 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, 8326 {"bits": [13, 13], "name": "FAST_CLEAR"}, 8327 {"bits": [14, 14], "name": "COMPRESSION"}, 8328 {"bits": [15, 15], "name": "BLEND_CLAMP"}, 8329 {"bits": [16, 16], "name": "BLEND_BYPASS"}, 8330 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, 8331 {"bits": [18, 18], "name": "ROUND_MODE"}, 8332 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, 8333 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, 8334 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, 8335 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"} 8336 ] 8337 }, 8338 "CB_COLOR0_PITCH": { 8339 "fields": [ 8340 {"bits": [0, 10], "name": "TILE_MAX"}, 8341 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} 8342 ] 8343 }, 8344 "CB_COLOR0_VIEW": { 8345 "fields": [ 8346 {"bits": [0, 10], "name": "SLICE_START"}, 8347 {"bits": [13, 23], "name": "SLICE_MAX"} 8348 ] 8349 }, 8350 "CB_COLOR_CONTROL": { 8351 "fields": [ 8352 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, 8353 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, 8354 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} 8355 ] 8356 }, 8357 "CB_SHADER_MASK": { 8358 "fields": [ 8359 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, 8360 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, 8361 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, 8362 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, 8363 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, 8364 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, 8365 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, 8366 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} 8367 ] 8368 }, 8369 "CB_TARGET_MASK": { 8370 "fields": [ 8371 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, 8372 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, 8373 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, 8374 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, 8375 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, 8376 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, 8377 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, 8378 {"bits": [28, 31], "name": "TARGET7_ENABLE"} 8379 ] 8380 }, 8381 "CC_GC_SHADER_ARRAY_CONFIG": { 8382 "fields": [ 8383 {"bits": [1, 2], "name": "DPFP_RATE"}, 8384 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"}, 8385 {"bits": [4, 4], "name": "HALF_LDS"}, 8386 {"bits": [16, 31], "name": "INACTIVE_CUS"} 8387 ] 8388 }, 8389 "CC_SQC_BANK_DISABLE": { 8390 "fields": [ 8391 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"}, 8392 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"}, 8393 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"}, 8394 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"} 8395 ] 8396 }, 8397 "CGTT_IA_CLK_CTRL": { 8398 "fields": [ 8399 {"bits": [0, 3], "name": "ON_DELAY"}, 8400 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 8401 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 8402 {"bits": [25, 25], "name": "PERF_ENABLE"}, 8403 {"bits": [26, 26], "name": "DBG_ENABLE"}, 8404 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 8405 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 8406 {"bits": [29, 29], "name": "CORE_OVERRIDE"}, 8407 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 8408 {"bits": [31, 31], "name": "REG_OVERRIDE"} 8409 ] 8410 }, 8411 "CGTT_PA_CLK_CTRL": { 8412 "fields": [ 8413 {"bits": [0, 3], "name": "ON_DELAY"}, 8414 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 8415 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 8416 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 8417 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 8418 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 8419 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 8420 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"}, 8421 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"}, 8422 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"} 8423 ] 8424 }, 8425 "CGTT_SC_CLK_CTRL": { 8426 "fields": [ 8427 {"bits": [0, 3], "name": "ON_DELAY"}, 8428 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 8429 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 8430 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 8431 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 8432 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 8433 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 8434 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 8435 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"}, 8436 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"} 8437 ] 8438 }, 8439 "CGTT_SQ_CLK_CTRL": { 8440 "fields": [ 8441 {"bits": [0, 3], "name": "ON_DELAY"}, 8442 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 8443 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 8444 {"bits": [31, 31], "name": "REG_OVERRIDE"} 8445 ] 8446 }, 8447 "CGTT_VGT_CLK_CTRL": { 8448 "fields": [ 8449 {"bits": [0, 3], "name": "ON_DELAY"}, 8450 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 8451 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 8452 {"bits": [25, 25], "name": "PERF_ENABLE"}, 8453 {"bits": [26, 26], "name": "DBG_ENABLE"}, 8454 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 8455 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 8456 {"bits": [29, 29], "name": "GS_OVERRIDE"}, 8457 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 8458 {"bits": [31, 31], "name": "REG_OVERRIDE"} 8459 ] 8460 }, 8461 "COHER_DEST_BASE_0": { 8462 "fields": [ 8463 {"bits": [0, 31], "name": "DEST_BASE_256B"} 8464 ] 8465 }, 8466 "COMPUTE_DIM_X": { 8467 "fields": [ 8468 {"bits": [0, 31], "name": "SIZE"} 8469 ] 8470 }, 8471 "COMPUTE_DISPATCH_INITIATOR": { 8472 "fields": [ 8473 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, 8474 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, 8475 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, 8476 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, 8477 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, 8478 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, 8479 {"bits": [6, 6], "name": "ORDER_MODE"}, 8480 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, 8481 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, 8482 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, 8483 {"bits": [12, 12], "name": "DATA_ATC"}, 8484 {"bits": [14, 14], "name": "RESTORE"} 8485 ] 8486 }, 8487 "COMPUTE_NUM_THREAD_X": { 8488 "fields": [ 8489 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, 8490 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} 8491 ] 8492 }, 8493 "COMPUTE_PGM_HI": { 8494 "fields": [ 8495 {"bits": [0, 7], "name": "DATA"}, 8496 {"bits": [8, 8], "name": "INST_ATC"} 8497 ] 8498 }, 8499 "COMPUTE_PGM_RSRC1": { 8500 "fields": [ 8501 {"bits": [0, 5], "name": "VGPRS"}, 8502 {"bits": [6, 9], "name": "SGPRS"}, 8503 {"bits": [10, 11], "name": "PRIORITY"}, 8504 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 8505 {"bits": [20, 20], "name": "PRIV"}, 8506 {"bits": [21, 21], "name": "DX10_CLAMP"}, 8507 {"bits": [22, 22], "name": "DEBUG_MODE"}, 8508 {"bits": [23, 23], "name": "IEEE_MODE"}, 8509 {"bits": [24, 24], "name": "BULKY"}, 8510 {"bits": [25, 25], "name": "CDBG_USER"} 8511 ] 8512 }, 8513 "COMPUTE_PGM_RSRC2": { 8514 "fields": [ 8515 {"bits": [0, 0], "name": "SCRATCH_EN"}, 8516 {"bits": [1, 5], "name": "USER_SGPR"}, 8517 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 8518 {"bits": [7, 7], "name": "TGID_X_EN"}, 8519 {"bits": [8, 8], "name": "TGID_Y_EN"}, 8520 {"bits": [9, 9], "name": "TGID_Z_EN"}, 8521 {"bits": [10, 10], "name": "TG_SIZE_EN"}, 8522 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, 8523 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, 8524 {"bits": [15, 23], "name": "LDS_SIZE"}, 8525 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 8526 ] 8527 }, 8528 "COMPUTE_RESOURCE_LIMITS": { 8529 "fields": [ 8530 {"bits": [0, 5], "name": "WAVES_PER_SH"}, 8531 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"}, 8532 {"bits": [12, 15], "name": "TG_PER_CU"}, 8533 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, 8534 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, 8535 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, 8536 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} 8537 ] 8538 }, 8539 "COMPUTE_START_X": { 8540 "fields": [ 8541 {"bits": [0, 31], "name": "START"} 8542 ] 8543 }, 8544 "COMPUTE_STATIC_THREAD_MGMT_SE0": { 8545 "fields": [ 8546 {"bits": [0, 15], "name": "SH0_CU_EN"}, 8547 {"bits": [16, 31], "name": "SH1_CU_EN"} 8548 ] 8549 }, 8550 "COMPUTE_TBA_HI": { 8551 "fields": [ 8552 {"bits": [0, 7], "name": "DATA"} 8553 ] 8554 }, 8555 "COMPUTE_TMPRING_SIZE": { 8556 "fields": [ 8557 {"bits": [0, 11], "name": "WAVES"}, 8558 {"bits": [12, 24], "name": "WAVESIZE"} 8559 ] 8560 }, 8561 "COMPUTE_VMID": { 8562 "fields": [ 8563 {"bits": [0, 3], "name": "DATA"} 8564 ] 8565 }, 8566 "CP_APPEND_ADDR_HI": { 8567 "fields": [ 8568 {"bits": [0, 7], "name": "MEM_ADDR_HI"}, 8569 {"bits": [16, 17], "name": "CS_PS_SEL"}, 8570 {"bits": [29, 31], "name": "COMMAND"} 8571 ] 8572 }, 8573 "CP_APPEND_ADDR_LO": { 8574 "fields": [ 8575 {"bits": [2, 31], "name": "MEM_ADDR_LO"} 8576 ] 8577 }, 8578 "CP_APPEND_LAST_CS_FENCE": { 8579 "fields": [ 8580 {"bits": [0, 31], "name": "LAST_FENCE"} 8581 ] 8582 }, 8583 "CP_ATOMIC_PREOP_HI": { 8584 "fields": [ 8585 {"bits": [0, 31], "name": "ATOMIC_PREOP_HI"} 8586 ] 8587 }, 8588 "CP_ATOMIC_PREOP_LO": { 8589 "fields": [ 8590 {"bits": [0, 31], "name": "ATOMIC_PREOP_LO"} 8591 ] 8592 }, 8593 "CP_BUSY_STAT": { 8594 "fields": [ 8595 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, 8596 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"}, 8597 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"}, 8598 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"}, 8599 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"}, 8600 {"bits": [10, 10], "name": "RCIU_ME_BUSY"}, 8601 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"}, 8602 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"}, 8603 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"}, 8604 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"}, 8605 {"bits": [17, 17], "name": "ME_PARSER_BUSY"}, 8606 {"bits": [18, 18], "name": "EOP_DONE_BUSY"}, 8607 {"bits": [19, 19], "name": "STRM_OUT_BUSY"}, 8608 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"}, 8609 {"bits": [21, 21], "name": "RCIU_CE_BUSY"}, 8610 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"} 8611 ] 8612 }, 8613 "CP_CEQ1_AVAIL": { 8614 "fields": [ 8615 {"bits": [0, 10], "name": "CEQ_CNT_RING"}, 8616 {"bits": [16, 26], "name": "CEQ_CNT_IB1"} 8617 ] 8618 }, 8619 "CP_CEQ2_AVAIL": { 8620 "fields": [ 8621 {"bits": [0, 10], "name": "CEQ_CNT_IB2"} 8622 ] 8623 }, 8624 "CP_CE_HEADER_DUMP": { 8625 "fields": [ 8626 {"bits": [0, 31], "name": "CE_HEADER_DUMP"} 8627 ] 8628 }, 8629 "CP_CE_IB1_BASE_HI": { 8630 "fields": [ 8631 {"bits": [0, 7], "name": "IB1_BASE_HI"} 8632 ] 8633 }, 8634 "CP_CE_IB1_BASE_LO": { 8635 "fields": [ 8636 {"bits": [2, 31], "name": "IB1_BASE_LO"} 8637 ] 8638 }, 8639 "CP_CE_IB1_BUFSZ": { 8640 "fields": [ 8641 {"bits": [0, 19], "name": "IB1_BUFSZ"} 8642 ] 8643 }, 8644 "CP_CE_IB2_BASE_HI": { 8645 "fields": [ 8646 {"bits": [0, 7], "name": "IB2_BASE_HI"} 8647 ] 8648 }, 8649 "CP_CE_IB2_BASE_LO": { 8650 "fields": [ 8651 {"bits": [2, 31], "name": "IB2_BASE_LO"} 8652 ] 8653 }, 8654 "CP_CE_IB2_BUFSZ": { 8655 "fields": [ 8656 {"bits": [0, 19], "name": "IB2_BUFSZ"} 8657 ] 8658 }, 8659 "CP_CE_INIT_BASE_HI": { 8660 "fields": [ 8661 {"bits": [0, 7], "name": "INIT_BASE_HI"} 8662 ] 8663 }, 8664 "CP_CE_INIT_BASE_LO": { 8665 "fields": [ 8666 {"bits": [5, 31], "name": "INIT_BASE_LO"} 8667 ] 8668 }, 8669 "CP_CE_INIT_BUFSZ": { 8670 "fields": [ 8671 {"bits": [0, 11], "name": "INIT_BUFSZ"} 8672 ] 8673 }, 8674 "CP_CE_ROQ_IB1_STAT": { 8675 "fields": [ 8676 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"}, 8677 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"} 8678 ] 8679 }, 8680 "CP_CE_ROQ_IB2_STAT": { 8681 "fields": [ 8682 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"}, 8683 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"} 8684 ] 8685 }, 8686 "CP_CE_ROQ_RB_STAT": { 8687 "fields": [ 8688 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"}, 8689 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"} 8690 ] 8691 }, 8692 "CP_CMD_DATA": { 8693 "fields": [ 8694 {"bits": [0, 31], "name": "CMD_DATA"} 8695 ] 8696 }, 8697 "CP_CMD_INDEX": { 8698 "fields": [ 8699 {"bits": [0, 10], "name": "CMD_INDEX"}, 8700 {"bits": [12, 13], "name": "CMD_ME_SEL"}, 8701 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"} 8702 ] 8703 }, 8704 "CP_CNTX_STAT": { 8705 "fields": [ 8706 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"}, 8707 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"}, 8708 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"}, 8709 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"} 8710 ] 8711 }, 8712 "CP_COHER_BASE": { 8713 "fields": [ 8714 {"bits": [0, 31], "name": "COHER_BASE_256B"} 8715 ] 8716 }, 8717 "CP_COHER_CNTL": { 8718 "fields": [ 8719 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, 8720 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, 8721 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, 8722 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, 8723 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, 8724 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, 8725 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, 8726 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, 8727 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, 8728 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, 8729 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, 8730 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, 8731 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"}, 8732 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, 8733 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, 8734 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, 8735 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, 8736 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, 8737 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, 8738 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, 8739 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, 8740 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, 8741 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"} 8742 ] 8743 }, 8744 "CP_COHER_SIZE": { 8745 "fields": [ 8746 {"bits": [0, 31], "name": "COHER_SIZE_256B"} 8747 ] 8748 }, 8749 "CP_COHER_START_DELAY": { 8750 "fields": [ 8751 {"bits": [0, 5], "name": "START_DELAY_COUNT"} 8752 ] 8753 }, 8754 "CP_COHER_STATUS": { 8755 "fields": [ 8756 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, 8757 {"bits": [24, 25], "name": "MEID"}, 8758 {"bits": [30, 30], "name": "PHASE1_STATUS"}, 8759 {"bits": [31, 31], "name": "STATUS"} 8760 ] 8761 }, 8762 "CP_CSF_CNTL": { 8763 "fields": [ 8764 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"} 8765 ] 8766 }, 8767 "CP_CSF_STAT": { 8768 "fields": [ 8769 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"}, 8770 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"} 8771 ] 8772 }, 8773 "CP_DMA_CNTL": { 8774 "fields": [ 8775 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, 8776 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, 8777 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, 8778 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, 8779 {"bits": [30, 31], "name": "PIO_COUNT"} 8780 ] 8781 }, 8782 "CP_DMA_ME_COMMAND": { 8783 "fields": [ 8784 {"bits": [0, 20], "name": "BYTE_COUNT"}, 8785 {"bits": [21, 21], "name": "DIS_WC"}, 8786 {"bits": [22, 23], "name": "SRC_SWAP"}, 8787 {"bits": [24, 25], "name": "DST_SWAP"}, 8788 {"bits": [26, 26], "name": "SAS"}, 8789 {"bits": [27, 27], "name": "DAS"}, 8790 {"bits": [28, 28], "name": "SAIC"}, 8791 {"bits": [29, 29], "name": "DAIC"}, 8792 {"bits": [30, 30], "name": "RAW_WAIT"} 8793 ] 8794 }, 8795 "CP_DMA_ME_DST_ADDR": { 8796 "fields": [ 8797 {"bits": [0, 31], "name": "DST_ADDR"} 8798 ] 8799 }, 8800 "CP_DMA_ME_DST_ADDR_HI": { 8801 "fields": [ 8802 {"bits": [0, 7], "name": "DST_ADDR_HI"} 8803 ] 8804 }, 8805 "CP_DMA_ME_SRC_ADDR": { 8806 "fields": [ 8807 {"bits": [0, 31], "name": "SRC_ADDR"} 8808 ] 8809 }, 8810 "CP_DMA_ME_SRC_ADDR_HI": { 8811 "fields": [ 8812 {"bits": [0, 7], "name": "SRC_ADDR_HI"} 8813 ] 8814 }, 8815 "CP_DMA_READ_TAGS": { 8816 "fields": [ 8817 {"bits": [0, 25], "name": "DMA_READ_TAG"}, 8818 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} 8819 ] 8820 }, 8821 "CP_EOP_DONE_ADDR_HI": { 8822 "fields": [ 8823 {"bits": [0, 15], "name": "ADDR_HI"} 8824 ] 8825 }, 8826 "CP_EOP_DONE_ADDR_LO": { 8827 "fields": [ 8828 {"bits": [0, 1], "name": "ADDR_SWAP"}, 8829 {"bits": [2, 31], "name": "ADDR_LO"} 8830 ] 8831 }, 8832 "CP_EOP_DONE_DATA_HI": { 8833 "fields": [ 8834 {"bits": [0, 31], "name": "DATA_HI"} 8835 ] 8836 }, 8837 "CP_EOP_DONE_DATA_LO": { 8838 "fields": [ 8839 {"bits": [0, 31], "name": "DATA_LO"} 8840 ] 8841 }, 8842 "CP_EOP_LAST_FENCE_HI": { 8843 "fields": [ 8844 {"bits": [0, 31], "name": "LAST_FENCE_HI"} 8845 ] 8846 }, 8847 "CP_EOP_LAST_FENCE_LO": { 8848 "fields": [ 8849 {"bits": [0, 31], "name": "LAST_FENCE_LO"} 8850 ] 8851 }, 8852 "CP_GDS_ATOMIC0_PREOP_HI": { 8853 "fields": [ 8854 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_HI"} 8855 ] 8856 }, 8857 "CP_GDS_ATOMIC0_PREOP_LO": { 8858 "fields": [ 8859 {"bits": [0, 31], "name": "GDS_ATOMIC0_PREOP_LO"} 8860 ] 8861 }, 8862 "CP_GDS_ATOMIC1_PREOP_HI": { 8863 "fields": [ 8864 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_HI"} 8865 ] 8866 }, 8867 "CP_GDS_ATOMIC1_PREOP_LO": { 8868 "fields": [ 8869 {"bits": [0, 31], "name": "GDS_ATOMIC1_PREOP_LO"} 8870 ] 8871 }, 8872 "CP_GRBM_FREE_COUNT": { 8873 "fields": [ 8874 {"bits": [0, 5], "name": "FREE_COUNT"}, 8875 {"bits": [8, 13], "name": "FREE_COUNT_GDS"}, 8876 {"bits": [16, 21], "name": "FREE_COUNT_PFP"} 8877 ] 8878 }, 8879 "CP_IB1_OFFSET": { 8880 "fields": [ 8881 {"bits": [0, 19], "name": "IB1_OFFSET"} 8882 ] 8883 }, 8884 "CP_IB1_PREAMBLE_BEGIN": { 8885 "fields": [ 8886 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} 8887 ] 8888 }, 8889 "CP_IB1_PREAMBLE_END": { 8890 "fields": [ 8891 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} 8892 ] 8893 }, 8894 "CP_IB2_OFFSET": { 8895 "fields": [ 8896 {"bits": [0, 19], "name": "IB2_OFFSET"} 8897 ] 8898 }, 8899 "CP_IB2_PREAMBLE_BEGIN": { 8900 "fields": [ 8901 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} 8902 ] 8903 }, 8904 "CP_IB2_PREAMBLE_END": { 8905 "fields": [ 8906 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} 8907 ] 8908 }, 8909 "CP_INT_STAT_DEBUG": { 8910 "fields": [ 8911 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"}, 8912 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"}, 8913 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"}, 8914 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"}, 8915 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"}, 8916 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"}, 8917 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"}, 8918 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"}, 8919 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"}, 8920 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"}, 8921 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"}, 8922 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"} 8923 ] 8924 }, 8925 "CP_MC_PACK_DELAY_CNT": { 8926 "fields": [ 8927 {"bits": [0, 4], "name": "PACK_DELAY_CNT"} 8928 ] 8929 }, 8930 "CP_MEQ_AVAIL": { 8931 "fields": [ 8932 {"bits": [0, 9], "name": "MEQ_CNT"} 8933 ] 8934 }, 8935 "CP_MEQ_STAT": { 8936 "fields": [ 8937 {"bits": [0, 9], "name": "MEQ_RPTR"}, 8938 {"bits": [16, 25], "name": "MEQ_WPTR"} 8939 ] 8940 }, 8941 "CP_MEQ_THRESHOLDS": { 8942 "fields": [ 8943 {"bits": [0, 7], "name": "MEQ1_START"}, 8944 {"bits": [8, 15], "name": "MEQ2_START"} 8945 ] 8946 }, 8947 "CP_ME_CNTL": { 8948 "fields": [ 8949 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"}, 8950 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"}, 8951 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"}, 8952 {"bits": [24, 24], "name": "CE_HALT"}, 8953 {"bits": [25, 25], "name": "CE_STEP"}, 8954 {"bits": [26, 26], "name": "PFP_HALT"}, 8955 {"bits": [27, 27], "name": "PFP_STEP"}, 8956 {"bits": [28, 28], "name": "ME_HALT"}, 8957 {"bits": [29, 29], "name": "ME_STEP"} 8958 ] 8959 }, 8960 "CP_ME_HEADER_DUMP": { 8961 "fields": [ 8962 {"bits": [0, 31], "name": "ME_HEADER_DUMP"} 8963 ] 8964 }, 8965 "CP_ME_MC_RADDR_HI": { 8966 "fields": [ 8967 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"} 8968 ] 8969 }, 8970 "CP_ME_MC_RADDR_LO": { 8971 "fields": [ 8972 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, 8973 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} 8974 ] 8975 }, 8976 "CP_ME_MC_WADDR_HI": { 8977 "fields": [ 8978 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"} 8979 ] 8980 }, 8981 "CP_ME_MC_WADDR_LO": { 8982 "fields": [ 8983 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, 8984 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} 8985 ] 8986 }, 8987 "CP_ME_MC_WDATA_HI": { 8988 "fields": [ 8989 {"bits": [0, 31], "name": "ME_MC_WDATA_HI"} 8990 ] 8991 }, 8992 "CP_ME_MC_WDATA_LO": { 8993 "fields": [ 8994 {"bits": [0, 31], "name": "ME_MC_WDATA_LO"} 8995 ] 8996 }, 8997 "CP_ME_PREEMPTION": { 8998 "fields": [ 8999 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"} 9000 ] 9001 }, 9002 "CP_NUM_PRIM_NEEDED_COUNT0_HI": { 9003 "fields": [ 9004 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_HI"} 9005 ] 9006 }, 9007 "CP_NUM_PRIM_NEEDED_COUNT0_LO": { 9008 "fields": [ 9009 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT0_LO"} 9010 ] 9011 }, 9012 "CP_NUM_PRIM_NEEDED_COUNT1_HI": { 9013 "fields": [ 9014 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_HI"} 9015 ] 9016 }, 9017 "CP_NUM_PRIM_NEEDED_COUNT1_LO": { 9018 "fields": [ 9019 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT1_LO"} 9020 ] 9021 }, 9022 "CP_NUM_PRIM_NEEDED_COUNT2_HI": { 9023 "fields": [ 9024 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_HI"} 9025 ] 9026 }, 9027 "CP_NUM_PRIM_NEEDED_COUNT2_LO": { 9028 "fields": [ 9029 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT2_LO"} 9030 ] 9031 }, 9032 "CP_NUM_PRIM_NEEDED_COUNT3_HI": { 9033 "fields": [ 9034 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_HI"} 9035 ] 9036 }, 9037 "CP_NUM_PRIM_NEEDED_COUNT3_LO": { 9038 "fields": [ 9039 {"bits": [0, 31], "name": "NUM_PRIM_NEEDED_CNT3_LO"} 9040 ] 9041 }, 9042 "CP_NUM_PRIM_WRITTEN_COUNT0_HI": { 9043 "fields": [ 9044 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_HI"} 9045 ] 9046 }, 9047 "CP_NUM_PRIM_WRITTEN_COUNT0_LO": { 9048 "fields": [ 9049 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT0_LO"} 9050 ] 9051 }, 9052 "CP_NUM_PRIM_WRITTEN_COUNT1_HI": { 9053 "fields": [ 9054 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_HI"} 9055 ] 9056 }, 9057 "CP_NUM_PRIM_WRITTEN_COUNT1_LO": { 9058 "fields": [ 9059 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT1_LO"} 9060 ] 9061 }, 9062 "CP_NUM_PRIM_WRITTEN_COUNT2_HI": { 9063 "fields": [ 9064 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_HI"} 9065 ] 9066 }, 9067 "CP_NUM_PRIM_WRITTEN_COUNT2_LO": { 9068 "fields": [ 9069 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT2_LO"} 9070 ] 9071 }, 9072 "CP_NUM_PRIM_WRITTEN_COUNT3_HI": { 9073 "fields": [ 9074 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_HI"} 9075 ] 9076 }, 9077 "CP_NUM_PRIM_WRITTEN_COUNT3_LO": { 9078 "fields": [ 9079 {"bits": [0, 31], "name": "NUM_PRIM_WRITTEN_CNT3_LO"} 9080 ] 9081 }, 9082 "CP_PA_CINVOC_COUNT_HI": { 9083 "fields": [ 9084 {"bits": [0, 31], "name": "CINVOC_COUNT_HI"} 9085 ] 9086 }, 9087 "CP_PA_CINVOC_COUNT_LO": { 9088 "fields": [ 9089 {"bits": [0, 31], "name": "CINVOC_COUNT_LO"} 9090 ] 9091 }, 9092 "CP_PA_CPRIM_COUNT_HI": { 9093 "fields": [ 9094 {"bits": [0, 31], "name": "CPRIM_COUNT_HI"} 9095 ] 9096 }, 9097 "CP_PA_CPRIM_COUNT_LO": { 9098 "fields": [ 9099 {"bits": [0, 31], "name": "CPRIM_COUNT_LO"} 9100 ] 9101 }, 9102 "CP_PERFMON_CNTL": { 9103 "fields": [ 9104 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 9105 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, 9106 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, 9107 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 9108 ] 9109 }, 9110 "CP_PERFMON_CNTX_CNTL": { 9111 "fields": [ 9112 {"bits": [31, 31], "name": "PERFMON_ENABLE"} 9113 ] 9114 }, 9115 "CP_PFP_HEADER_DUMP": { 9116 "fields": [ 9117 {"bits": [0, 31], "name": "PFP_HEADER_DUMP"} 9118 ] 9119 }, 9120 "CP_PFP_IB_CONTROL": { 9121 "fields": [ 9122 {"bits": [0, 0], "name": "IB_EN"} 9123 ] 9124 }, 9125 "CP_PFP_LOAD_CONTROL": { 9126 "fields": [ 9127 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, 9128 {"bits": [1, 1], "name": "CNTX_REG_EN"}, 9129 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, 9130 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, 9131 {"bits": [24, 24], "name": "SH_CS_REG_EN"} 9132 ] 9133 }, 9134 "CP_PIPE_STATS_ADDR_HI": { 9135 "fields": [ 9136 {"bits": [0, 31], "name": "PIPE_STATS_ADDR_HI"} 9137 ] 9138 }, 9139 "CP_PIPE_STATS_ADDR_LO": { 9140 "fields": [ 9141 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"}, 9142 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} 9143 ] 9144 }, 9145 "CP_QUEUE_THRESHOLDS": { 9146 "fields": [ 9147 {"bits": [0, 5], "name": "ROQ_IB1_START"}, 9148 {"bits": [8, 13], "name": "ROQ_IB2_START"} 9149 ] 9150 }, 9151 "CP_RB0_RPTR": { 9152 "fields": [ 9153 {"bits": [0, 19], "name": "RB_RPTR"} 9154 ] 9155 }, 9156 "CP_RB_OFFSET": { 9157 "fields": [ 9158 {"bits": [0, 19], "name": "RB_OFFSET"} 9159 ] 9160 }, 9161 "CP_RB_WPTR_DELAY": { 9162 "fields": [ 9163 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"}, 9164 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"} 9165 ] 9166 }, 9167 "CP_RB_WPTR_POLL_CNTL": { 9168 "fields": [ 9169 {"bits": [0, 15], "name": "POLL_FREQUENCY"}, 9170 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"} 9171 ] 9172 }, 9173 "CP_RINGID": { 9174 "fields": [ 9175 {"bits": [0, 1], "name": "RINGID"} 9176 ] 9177 }, 9178 "CP_ROQ1_THRESHOLDS": { 9179 "fields": [ 9180 {"bits": [0, 7], "name": "RB1_START"}, 9181 {"bits": [8, 15], "name": "RB2_START"}, 9182 {"bits": [16, 23], "name": "R0_IB1_START"}, 9183 {"bits": [24, 31], "name": "R1_IB1_START"} 9184 ] 9185 }, 9186 "CP_ROQ2_AVAIL": { 9187 "fields": [ 9188 {"bits": [0, 10], "name": "ROQ_CNT_IB2"} 9189 ] 9190 }, 9191 "CP_ROQ2_THRESHOLDS": { 9192 "fields": [ 9193 {"bits": [0, 7], "name": "R2_IB1_START"}, 9194 {"bits": [8, 15], "name": "R0_IB2_START"}, 9195 {"bits": [16, 23], "name": "R1_IB2_START"}, 9196 {"bits": [24, 31], "name": "R2_IB2_START"} 9197 ] 9198 }, 9199 "CP_ROQ_AVAIL": { 9200 "fields": [ 9201 {"bits": [0, 10], "name": "ROQ_CNT_RING"}, 9202 {"bits": [16, 26], "name": "ROQ_CNT_IB1"} 9203 ] 9204 }, 9205 "CP_ROQ_IB1_STAT": { 9206 "fields": [ 9207 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"}, 9208 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"} 9209 ] 9210 }, 9211 "CP_ROQ_IB2_STAT": { 9212 "fields": [ 9213 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"}, 9214 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"} 9215 ] 9216 }, 9217 "CP_ROQ_RB_STAT": { 9218 "fields": [ 9219 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"}, 9220 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"} 9221 ] 9222 }, 9223 "CP_SCRATCH_DATA": { 9224 "fields": [ 9225 {"bits": [0, 31], "name": "SCRATCH_DATA"} 9226 ] 9227 }, 9228 "CP_SCRATCH_INDEX": { 9229 "fields": [ 9230 {"bits": [0, 7], "name": "SCRATCH_INDEX"} 9231 ] 9232 }, 9233 "CP_SC_PSINVOC_COUNT0_HI": { 9234 "fields": [ 9235 {"bits": [0, 31], "name": "PSINVOC_COUNT0_HI"} 9236 ] 9237 }, 9238 "CP_SC_PSINVOC_COUNT0_LO": { 9239 "fields": [ 9240 {"bits": [0, 31], "name": "PSINVOC_COUNT0_LO"} 9241 ] 9242 }, 9243 "CP_SC_PSINVOC_COUNT1_HI": { 9244 "fields": [ 9245 {"bits": [0, 31], "name": "OBSOLETE"} 9246 ] 9247 }, 9248 "CP_SEM_WAIT_TIMER": { 9249 "fields": [ 9250 {"bits": [0, 31], "name": "SEM_WAIT_TIMER"} 9251 ] 9252 }, 9253 "CP_SIG_SEM_ADDR_HI": { 9254 "fields": [ 9255 {"bits": [0, 7], "name": "SEM_ADDR_HI"}, 9256 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, 9257 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, 9258 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, 9259 {"bits": [29, 31], "name": "SEM_SELECT"} 9260 ] 9261 }, 9262 "CP_SIG_SEM_ADDR_LO": { 9263 "fields": [ 9264 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, 9265 {"bits": [3, 31], "name": "SEM_ADDR_LO"} 9266 ] 9267 }, 9268 "CP_STALLED_STAT1": { 9269 "fields": [ 9270 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"}, 9271 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"}, 9272 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"}, 9273 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"}, 9274 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"}, 9275 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"}, 9276 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"}, 9277 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"}, 9278 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"}, 9279 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"}, 9280 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"}, 9281 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"}, 9282 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"}, 9283 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"}, 9284 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"}, 9285 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"}, 9286 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"}, 9287 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"} 9288 ] 9289 }, 9290 "CP_STALLED_STAT2": { 9291 "fields": [ 9292 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"}, 9293 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"}, 9294 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"}, 9295 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"}, 9296 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"}, 9297 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"}, 9298 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 9299 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"}, 9300 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"}, 9301 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"}, 9302 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"}, 9303 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"}, 9304 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"}, 9305 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"}, 9306 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"}, 9307 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"}, 9308 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"}, 9309 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"}, 9310 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"}, 9311 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"}, 9312 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"}, 9313 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"}, 9314 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"}, 9315 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"}, 9316 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"}, 9317 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"}, 9318 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"}, 9319 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"}, 9320 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"}, 9321 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"}, 9322 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"} 9323 ] 9324 }, 9325 "CP_STALLED_STAT3": { 9326 "fields": [ 9327 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"}, 9328 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"}, 9329 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"}, 9330 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"}, 9331 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"}, 9332 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"}, 9333 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"}, 9334 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"}, 9335 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 9336 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"}, 9337 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"}, 9338 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"}, 9339 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"}, 9340 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"}, 9341 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"} 9342 ] 9343 }, 9344 "CP_STAT": { 9345 "fields": [ 9346 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"}, 9347 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"}, 9348 {"bits": [9, 9], "name": "ROQ_RING_BUSY"}, 9349 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"}, 9350 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"}, 9351 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"}, 9352 {"bits": [13, 13], "name": "DC_BUSY"}, 9353 {"bits": [15, 15], "name": "PFP_BUSY"}, 9354 {"bits": [16, 16], "name": "MEQ_BUSY"}, 9355 {"bits": [17, 17], "name": "ME_BUSY"}, 9356 {"bits": [18, 18], "name": "QUERY_BUSY"}, 9357 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"}, 9358 {"bits": [20, 20], "name": "INTERRUPT_BUSY"}, 9359 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"}, 9360 {"bits": [22, 22], "name": "DMA_BUSY"}, 9361 {"bits": [23, 23], "name": "RCIU_BUSY"}, 9362 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"}, 9363 {"bits": [25, 25], "name": "CPC_CPG_BUSY"}, 9364 {"bits": [26, 26], "name": "CE_BUSY"}, 9365 {"bits": [27, 27], "name": "TCIU_BUSY"}, 9366 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"}, 9367 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"}, 9368 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"}, 9369 {"bits": [31, 31], "name": "CP_BUSY"} 9370 ] 9371 }, 9372 "CP_STQ_AVAIL": { 9373 "fields": [ 9374 {"bits": [0, 8], "name": "STQ_CNT"} 9375 ] 9376 }, 9377 "CP_STQ_STAT": { 9378 "fields": [ 9379 {"bits": [0, 9], "name": "STQ_RPTR"} 9380 ] 9381 }, 9382 "CP_STQ_THRESHOLDS": { 9383 "fields": [ 9384 {"bits": [0, 7], "name": "STQ0_START"}, 9385 {"bits": [8, 15], "name": "STQ1_START"}, 9386 {"bits": [16, 23], "name": "STQ2_START"} 9387 ] 9388 }, 9389 "CP_STREAM_OUT_ADDR_HI": { 9390 "fields": [ 9391 {"bits": [0, 31], "name": "STREAM_OUT_ADDR_HI"} 9392 ] 9393 }, 9394 "CP_STREAM_OUT_ADDR_LO": { 9395 "fields": [ 9396 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"}, 9397 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} 9398 ] 9399 }, 9400 "CP_STRMOUT_CNTL": { 9401 "fields": [ 9402 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} 9403 ] 9404 }, 9405 "CP_ST_BASE_HI": { 9406 "fields": [ 9407 {"bits": [0, 7], "name": "ST_BASE_HI"} 9408 ] 9409 }, 9410 "CP_ST_BASE_LO": { 9411 "fields": [ 9412 {"bits": [2, 31], "name": "ST_BASE_LO"} 9413 ] 9414 }, 9415 "CP_ST_BUFSZ": { 9416 "fields": [ 9417 {"bits": [0, 19], "name": "ST_BUFSZ"} 9418 ] 9419 }, 9420 "CP_VGT_CSINVOC_COUNT_HI": { 9421 "fields": [ 9422 {"bits": [0, 31], "name": "CSINVOC_COUNT_HI"} 9423 ] 9424 }, 9425 "CP_VGT_CSINVOC_COUNT_LO": { 9426 "fields": [ 9427 {"bits": [0, 31], "name": "CSINVOC_COUNT_LO"} 9428 ] 9429 }, 9430 "CP_VGT_DSINVOC_COUNT_HI": { 9431 "fields": [ 9432 {"bits": [0, 31], "name": "DSINVOC_COUNT_HI"} 9433 ] 9434 }, 9435 "CP_VGT_DSINVOC_COUNT_LO": { 9436 "fields": [ 9437 {"bits": [0, 31], "name": "DSINVOC_COUNT_LO"} 9438 ] 9439 }, 9440 "CP_VGT_GSINVOC_COUNT_HI": { 9441 "fields": [ 9442 {"bits": [0, 31], "name": "GSINVOC_COUNT_HI"} 9443 ] 9444 }, 9445 "CP_VGT_GSINVOC_COUNT_LO": { 9446 "fields": [ 9447 {"bits": [0, 31], "name": "GSINVOC_COUNT_LO"} 9448 ] 9449 }, 9450 "CP_VGT_GSPRIM_COUNT_HI": { 9451 "fields": [ 9452 {"bits": [0, 31], "name": "GSPRIM_COUNT_HI"} 9453 ] 9454 }, 9455 "CP_VGT_GSPRIM_COUNT_LO": { 9456 "fields": [ 9457 {"bits": [0, 31], "name": "GSPRIM_COUNT_LO"} 9458 ] 9459 }, 9460 "CP_VGT_HSINVOC_COUNT_HI": { 9461 "fields": [ 9462 {"bits": [0, 31], "name": "HSINVOC_COUNT_HI"} 9463 ] 9464 }, 9465 "CP_VGT_HSINVOC_COUNT_LO": { 9466 "fields": [ 9467 {"bits": [0, 31], "name": "HSINVOC_COUNT_LO"} 9468 ] 9469 }, 9470 "CP_VGT_IAPRIM_COUNT_HI": { 9471 "fields": [ 9472 {"bits": [0, 31], "name": "IAPRIM_COUNT_HI"} 9473 ] 9474 }, 9475 "CP_VGT_IAPRIM_COUNT_LO": { 9476 "fields": [ 9477 {"bits": [0, 31], "name": "IAPRIM_COUNT_LO"} 9478 ] 9479 }, 9480 "CP_VGT_IAVERT_COUNT_HI": { 9481 "fields": [ 9482 {"bits": [0, 31], "name": "IAVERT_COUNT_HI"} 9483 ] 9484 }, 9485 "CP_VGT_IAVERT_COUNT_LO": { 9486 "fields": [ 9487 {"bits": [0, 31], "name": "IAVERT_COUNT_LO"} 9488 ] 9489 }, 9490 "CP_VGT_VSINVOC_COUNT_HI": { 9491 "fields": [ 9492 {"bits": [0, 31], "name": "VSINVOC_COUNT_HI"} 9493 ] 9494 }, 9495 "CP_VGT_VSINVOC_COUNT_LO": { 9496 "fields": [ 9497 {"bits": [0, 31], "name": "VSINVOC_COUNT_LO"} 9498 ] 9499 }, 9500 "CP_VMID": { 9501 "fields": [ 9502 {"bits": [0, 3], "name": "VMID"} 9503 ] 9504 }, 9505 "CP_WAIT_REG_MEM_TIMEOUT": { 9506 "fields": [ 9507 {"bits": [0, 31], "name": "WAIT_REG_MEM_TIMEOUT"} 9508 ] 9509 }, 9510 "CS_COPY_STATE": { 9511 "fields": [ 9512 {"bits": [0, 2], "name": "SRC_STATE_ID"} 9513 ] 9514 }, 9515 "DB_ALPHA_TO_MASK": { 9516 "fields": [ 9517 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, 9518 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, 9519 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, 9520 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, 9521 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, 9522 {"bits": [16, 16], "name": "OFFSET_ROUND"} 9523 ] 9524 }, 9525 "DB_COUNT_CONTROL": { 9526 "fields": [ 9527 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, 9528 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, 9529 {"bits": [4, 6], "name": "SAMPLE_RATE"}, 9530 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, 9531 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, 9532 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, 9533 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, 9534 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, 9535 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} 9536 ] 9537 }, 9538 "DB_DEPTH_BOUNDS_MAX": { 9539 "fields": [ 9540 {"bits": [0, 31], "name": "MAX"} 9541 ] 9542 }, 9543 "DB_DEPTH_BOUNDS_MIN": { 9544 "fields": [ 9545 {"bits": [0, 31], "name": "MIN"} 9546 ] 9547 }, 9548 "DB_DEPTH_CLEAR": { 9549 "fields": [ 9550 {"bits": [0, 31], "name": "DEPTH_CLEAR"} 9551 ] 9552 }, 9553 "DB_DEPTH_CONTROL": { 9554 "fields": [ 9555 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, 9556 {"bits": [1, 1], "name": "Z_ENABLE"}, 9557 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, 9558 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, 9559 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, 9560 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, 9561 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, 9562 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, 9563 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, 9564 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} 9565 ] 9566 }, 9567 "DB_DEPTH_INFO": { 9568 "fields": [ 9569 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, 9570 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 9571 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 9572 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, 9573 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, 9574 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, 9575 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} 9576 ] 9577 }, 9578 "DB_DEPTH_SIZE": { 9579 "fields": [ 9580 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, 9581 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} 9582 ] 9583 }, 9584 "DB_DEPTH_SLICE": { 9585 "fields": [ 9586 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} 9587 ] 9588 }, 9589 "DB_DEPTH_VIEW": { 9590 "fields": [ 9591 {"bits": [0, 10], "name": "SLICE_START"}, 9592 {"bits": [13, 23], "name": "SLICE_MAX"}, 9593 {"bits": [24, 24], "name": "Z_READ_ONLY"}, 9594 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} 9595 ] 9596 }, 9597 "DB_EQAA": { 9598 "fields": [ 9599 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, 9600 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, 9601 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, 9602 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, 9603 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, 9604 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, 9605 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, 9606 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, 9607 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, 9608 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, 9609 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, 9610 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} 9611 ] 9612 }, 9613 "DB_HTILE_SURFACE": { 9614 "fields": [ 9615 {"bits": [0, 0], "name": "LINEAR"}, 9616 {"bits": [1, 1], "name": "FULL_CACHE"}, 9617 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, 9618 {"bits": [3, 3], "name": "PRELOAD"}, 9619 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, 9620 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, 9621 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"} 9622 ] 9623 }, 9624 "DB_PRELOAD_CONTROL": { 9625 "fields": [ 9626 {"bits": [0, 7], "name": "START_X"}, 9627 {"bits": [8, 15], "name": "START_Y"}, 9628 {"bits": [16, 23], "name": "MAX_X"}, 9629 {"bits": [24, 31], "name": "MAX_Y"} 9630 ] 9631 }, 9632 "DB_RENDER_CONTROL": { 9633 "fields": [ 9634 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, 9635 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, 9636 {"bits": [2, 2], "name": "DEPTH_COPY"}, 9637 {"bits": [3, 3], "name": "STENCIL_COPY"}, 9638 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, 9639 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, 9640 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, 9641 {"bits": [7, 7], "name": "COPY_CENTROID"}, 9642 {"bits": [8, 11], "name": "COPY_SAMPLE"} 9643 ] 9644 }, 9645 "DB_RENDER_OVERRIDE": { 9646 "fields": [ 9647 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, 9648 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, 9649 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, 9650 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, 9651 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, 9652 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, 9653 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, 9654 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, 9655 {"bits": [11, 11], "name": "FORCE_Z_READ"}, 9656 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, 9657 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, 9658 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, 9659 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, 9660 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, 9661 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, 9662 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, 9663 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, 9664 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, 9665 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, 9666 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, 9667 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, 9668 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, 9669 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} 9670 ] 9671 }, 9672 "DB_RENDER_OVERRIDE2": { 9673 "fields": [ 9674 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, 9675 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, 9676 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, 9677 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, 9678 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, 9679 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, 9680 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, 9681 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, 9682 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, 9683 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, 9684 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, 9685 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, 9686 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, 9687 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, 9688 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} 9689 ] 9690 }, 9691 "DB_SHADER_CONTROL": { 9692 "fields": [ 9693 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, 9694 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, 9695 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, 9696 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, 9697 {"bits": [6, 6], "name": "KILL_ENABLE"}, 9698 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, 9699 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, 9700 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, 9701 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, 9702 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, 9703 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, 9704 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} 9705 ] 9706 }, 9707 "DB_SRESULTS_COMPARE_STATE0": { 9708 "fields": [ 9709 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, 9710 {"bits": [4, 11], "name": "COMPAREVALUE0"}, 9711 {"bits": [12, 19], "name": "COMPAREMASK0"}, 9712 {"bits": [24, 24], "name": "ENABLE0"} 9713 ] 9714 }, 9715 "DB_SRESULTS_COMPARE_STATE1": { 9716 "fields": [ 9717 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, 9718 {"bits": [4, 11], "name": "COMPAREVALUE1"}, 9719 {"bits": [12, 19], "name": "COMPAREMASK1"}, 9720 {"bits": [24, 24], "name": "ENABLE1"} 9721 ] 9722 }, 9723 "DB_STENCILREFMASK": { 9724 "fields": [ 9725 {"bits": [0, 7], "name": "STENCILTESTVAL"}, 9726 {"bits": [8, 15], "name": "STENCILMASK"}, 9727 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, 9728 {"bits": [24, 31], "name": "STENCILOPVAL"} 9729 ] 9730 }, 9731 "DB_STENCILREFMASK_BF": { 9732 "fields": [ 9733 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, 9734 {"bits": [8, 15], "name": "STENCILMASK_BF"}, 9735 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, 9736 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} 9737 ] 9738 }, 9739 "DB_STENCIL_CLEAR": { 9740 "fields": [ 9741 {"bits": [0, 7], "name": "CLEAR"} 9742 ] 9743 }, 9744 "DB_STENCIL_CONTROL": { 9745 "fields": [ 9746 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, 9747 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, 9748 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, 9749 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, 9750 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, 9751 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} 9752 ] 9753 }, 9754 "DB_STENCIL_INFO": { 9755 "fields": [ 9756 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, 9757 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 9758 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 9759 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 9760 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} 9761 ] 9762 }, 9763 "DB_Z_INFO": { 9764 "fields": [ 9765 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, 9766 {"bits": [2, 3], "name": "NUM_SAMPLES"}, 9767 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 9768 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 9769 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 9770 {"bits": [28, 28], "name": "READ_SIZE"}, 9771 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, 9772 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} 9773 ] 9774 }, 9775 "DEBUG_DATA": { 9776 "fields": [ 9777 {"bits": [0, 31], "name": "DEBUG_DATA"} 9778 ] 9779 }, 9780 "DEBUG_INDEX": { 9781 "fields": [ 9782 {"bits": [0, 17], "name": "DEBUG_INDEX"} 9783 ] 9784 }, 9785 "GB_ADDR_CONFIG": { 9786 "fields": [ 9787 {"bits": [0, 2], "name": "NUM_PIPES"}, 9788 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, 9789 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, 9790 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, 9791 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, 9792 {"bits": [20, 22], "name": "NUM_GPUS"}, 9793 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, 9794 {"bits": [28, 29], "name": "ROW_SIZE"}, 9795 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} 9796 ] 9797 }, 9798 "GB_TILE_MODE0": { 9799 "fields": [ 9800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"}, 9801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 9802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 9803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 9804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 9805 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 9806 ] 9807 }, 9808 "GB_TILE_MODE10": { 9809 "fields": [ 9810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 9811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 9812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 9813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 9814 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 9815 ] 9816 }, 9817 "GRBM_CNTL": { 9818 "fields": [ 9819 {"bits": [0, 7], "name": "READ_TIMEOUT"} 9820 ] 9821 }, 9822 "GRBM_DEBUG": { 9823 "fields": [ 9824 {"bits": [1, 1], "name": "IGNORE_RDY"}, 9825 {"bits": [5, 5], "name": "IGNORE_FAO"}, 9826 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"}, 9827 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"}, 9828 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"}, 9829 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"} 9830 ] 9831 }, 9832 "GRBM_DEBUG_CNTL": { 9833 "fields": [ 9834 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"} 9835 ] 9836 }, 9837 "GRBM_DEBUG_SNAPSHOT": { 9838 "fields": [ 9839 {"bits": [0, 0], "name": "CPF_RDY"}, 9840 {"bits": [1, 1], "name": "CPG_RDY"}, 9841 {"bits": [1, 1], "name": "SRBM_RDY"}, 9842 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"}, 9843 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"}, 9844 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"}, 9845 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"}, 9846 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"}, 9847 {"bits": [9, 9], "name": "GDS_RDY"}, 9848 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"}, 9849 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"}, 9850 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"}, 9851 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"}, 9852 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"}, 9853 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"}, 9854 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"}, 9855 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"}, 9856 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"}, 9857 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"}, 9858 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"}, 9859 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"}, 9860 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"} 9861 ] 9862 }, 9863 "GRBM_GFX_CLKEN_CNTL": { 9864 "fields": [ 9865 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"}, 9866 {"bits": [8, 12], "name": "POST_DELAY_CNT"} 9867 ] 9868 }, 9869 "GRBM_GFX_INDEX": { 9870 "fields": [ 9871 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, 9872 {"bits": [8, 15], "name": "SH_INDEX"}, 9873 {"bits": [16, 23], "name": "SE_INDEX"}, 9874 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, 9875 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, 9876 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} 9877 ] 9878 }, 9879 "GRBM_INT_CNTL": { 9880 "fields": [ 9881 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"}, 9882 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"} 9883 ] 9884 }, 9885 "GRBM_PERFCOUNTER0_HI": { 9886 "fields": [ 9887 {"bits": [0, 31], "name": "PERFCOUNTER_HI"} 9888 ] 9889 }, 9890 "GRBM_PERFCOUNTER0_LO": { 9891 "fields": [ 9892 {"bits": [0, 31], "name": "PERFCOUNTER_LO"} 9893 ] 9894 }, 9895 "GRBM_PERFCOUNTER0_SELECT": { 9896 "fields": [ 9897 {"bits": [0, 5], "name": "PERF_SEL"}, 9898 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 9899 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 9900 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 9901 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, 9902 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, 9903 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 9904 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, 9905 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, 9906 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, 9907 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, 9908 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, 9909 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, 9910 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, 9911 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, 9912 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 9913 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, 9914 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, 9915 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} 9916 ] 9917 }, 9918 "GRBM_PWR_CNTL": { 9919 "fields": [ 9920 {"bits": [0, 3], "name": "REQ_TYPE"}, 9921 {"bits": [4, 7], "name": "RSP_TYPE"} 9922 ] 9923 }, 9924 "GRBM_READ_ERROR": { 9925 "fields": [ 9926 {"bits": [2, 17], "name": "READ_ADDRESS"}, 9927 {"bits": [20, 21], "name": "READ_PIPEID"}, 9928 {"bits": [22, 23], "name": "READ_MEID"}, 9929 {"bits": [31, 31], "name": "READ_ERROR"} 9930 ] 9931 }, 9932 "GRBM_SCRATCH_REG0": { 9933 "fields": [ 9934 {"bits": [0, 31], "name": "SCRATCH_REG0"} 9935 ] 9936 }, 9937 "GRBM_SCRATCH_REG1": { 9938 "fields": [ 9939 {"bits": [0, 31], "name": "SCRATCH_REG1"} 9940 ] 9941 }, 9942 "GRBM_SCRATCH_REG2": { 9943 "fields": [ 9944 {"bits": [0, 31], "name": "SCRATCH_REG2"} 9945 ] 9946 }, 9947 "GRBM_SCRATCH_REG3": { 9948 "fields": [ 9949 {"bits": [0, 31], "name": "SCRATCH_REG3"} 9950 ] 9951 }, 9952 "GRBM_SCRATCH_REG4": { 9953 "fields": [ 9954 {"bits": [0, 31], "name": "SCRATCH_REG4"} 9955 ] 9956 }, 9957 "GRBM_SCRATCH_REG5": { 9958 "fields": [ 9959 {"bits": [0, 31], "name": "SCRATCH_REG5"} 9960 ] 9961 }, 9962 "GRBM_SCRATCH_REG6": { 9963 "fields": [ 9964 {"bits": [0, 31], "name": "SCRATCH_REG6"} 9965 ] 9966 }, 9967 "GRBM_SCRATCH_REG7": { 9968 "fields": [ 9969 {"bits": [0, 31], "name": "SCRATCH_REG7"} 9970 ] 9971 }, 9972 "GRBM_SE0_PERFCOUNTER_SELECT": { 9973 "fields": [ 9974 {"bits": [0, 5], "name": "PERF_SEL"}, 9975 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 9976 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 9977 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, 9978 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, 9979 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 9980 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, 9981 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, 9982 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, 9983 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 9984 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, 9985 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} 9986 ] 9987 }, 9988 "GRBM_SKEW_CNTL": { 9989 "fields": [ 9990 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"}, 9991 {"bits": [6, 11], "name": "SKEW_COUNT"} 9992 ] 9993 }, 9994 "GRBM_SOFT_RESET": { 9995 "fields": [ 9996 {"bits": [0, 0], "name": "SOFT_RESET_CP"}, 9997 {"bits": [2, 2], "name": "SOFT_RESET_RLC"}, 9998 {"bits": [16, 16], "name": "SOFT_RESET_GFX"}, 9999 {"bits": [17, 17], "name": "SOFT_RESET_CPF"}, 10000 {"bits": [18, 18], "name": "SOFT_RESET_CPC"}, 10001 {"bits": [19, 19], "name": "SOFT_RESET_CPG"} 10002 ] 10003 }, 10004 "GRBM_STATUS": { 10005 "fields": [ 10006 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, 10007 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, 10008 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, 10009 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, 10010 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, 10011 {"bits": [12, 12], "name": "DB_CLEAN"}, 10012 {"bits": [13, 13], "name": "CB_CLEAN"}, 10013 {"bits": [14, 14], "name": "TA_BUSY"}, 10014 {"bits": [15, 15], "name": "GDS_BUSY"}, 10015 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, 10016 {"bits": [17, 17], "name": "VGT_BUSY"}, 10017 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, 10018 {"bits": [19, 19], "name": "IA_BUSY"}, 10019 {"bits": [20, 20], "name": "SX_BUSY"}, 10020 {"bits": [21, 21], "name": "WD_BUSY"}, 10021 {"bits": [22, 22], "name": "SPI_BUSY"}, 10022 {"bits": [23, 23], "name": "BCI_BUSY"}, 10023 {"bits": [24, 24], "name": "SC_BUSY"}, 10024 {"bits": [25, 25], "name": "PA_BUSY"}, 10025 {"bits": [26, 26], "name": "DB_BUSY"}, 10026 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, 10027 {"bits": [29, 29], "name": "CP_BUSY"}, 10028 {"bits": [30, 30], "name": "CB_BUSY"}, 10029 {"bits": [31, 31], "name": "GUI_ACTIVE"} 10030 ] 10031 }, 10032 "GRBM_STATUS2": { 10033 "fields": [ 10034 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, 10035 {"bits": [0, 0], "name": "RLC_RQ_PENDING"}, 10036 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, 10037 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, 10038 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, 10039 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, 10040 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, 10041 {"bits": [8, 8], "name": "RLC_BUSY"}, 10042 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, 10043 {"bits": [9, 9], "name": "TC_BUSY"}, 10044 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, 10045 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, 10046 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, 10047 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, 10048 {"bits": [28, 28], "name": "CPF_BUSY"}, 10049 {"bits": [29, 29], "name": "CPC_BUSY"}, 10050 {"bits": [30, 30], "name": "CPG_BUSY"} 10051 ] 10052 }, 10053 "GRBM_STATUS_SE0": { 10054 "fields": [ 10055 {"bits": [1, 1], "name": "DB_CLEAN"}, 10056 {"bits": [2, 2], "name": "CB_CLEAN"}, 10057 {"bits": [22, 22], "name": "BCI_BUSY"}, 10058 {"bits": [23, 23], "name": "VGT_BUSY"}, 10059 {"bits": [24, 24], "name": "PA_BUSY"}, 10060 {"bits": [25, 25], "name": "TA_BUSY"}, 10061 {"bits": [26, 26], "name": "SX_BUSY"}, 10062 {"bits": [27, 27], "name": "SPI_BUSY"}, 10063 {"bits": [29, 29], "name": "SC_BUSY"}, 10064 {"bits": [30, 30], "name": "DB_BUSY"}, 10065 {"bits": [31, 31], "name": "CB_BUSY"} 10066 ] 10067 }, 10068 "GRBM_WAIT_IDLE_CLOCKS": { 10069 "fields": [ 10070 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"} 10071 ] 10072 }, 10073 "IA_CNTL_STATUS": { 10074 "fields": [ 10075 {"bits": [0, 0], "name": "IA_BUSY"}, 10076 {"bits": [1, 1], "name": "IA_DMA_BUSY"}, 10077 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"}, 10078 {"bits": [3, 3], "name": "IA_GRP_BUSY"}, 10079 {"bits": [4, 4], "name": "IA_ADC_BUSY"} 10080 ] 10081 }, 10082 "IA_DEBUG_CNTL": { 10083 "fields": [ 10084 {"bits": [0, 5], "name": "IA_DEBUG_INDX"}, 10085 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"} 10086 ] 10087 }, 10088 "IA_ENHANCE": { 10089 "fields": [ 10090 {"bits": [0, 31], "name": "MISC"} 10091 ] 10092 }, 10093 "IA_MULTI_VGT_PARAM": { 10094 "fields": [ 10095 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 10096 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 10097 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 10098 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 10099 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 10100 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} 10101 ] 10102 }, 10103 "IA_PERFCOUNTER0_SELECT": { 10104 "fields": [ 10105 {"bits": [0, 7], "name": "PERF_SEL"}, 10106 {"bits": [10, 19], "name": "PERF_SEL1"}, 10107 {"bits": [20, 23], "name": "CNTR_MODE"}, 10108 {"bits": [24, 27], "name": "PERF_MODE1"}, 10109 {"bits": [28, 31], "name": "PERF_MODE"} 10110 ] 10111 }, 10112 "IA_PERFCOUNTER1_SELECT": { 10113 "fields": [ 10114 {"bits": [0, 7], "name": "PERF_SEL"}, 10115 {"bits": [28, 31], "name": "PERF_MODE"} 10116 ] 10117 }, 10118 "IA_VMID_OVERRIDE": { 10119 "fields": [ 10120 {"bits": [0, 0], "name": "ENABLE"}, 10121 {"bits": [1, 4], "name": "VMID"} 10122 ] 10123 }, 10124 "PA_CL_CLIP_CNTL": { 10125 "fields": [ 10126 {"bits": [0, 0], "name": "UCP_ENA_0"}, 10127 {"bits": [1, 1], "name": "UCP_ENA_1"}, 10128 {"bits": [2, 2], "name": "UCP_ENA_2"}, 10129 {"bits": [3, 3], "name": "UCP_ENA_3"}, 10130 {"bits": [4, 4], "name": "UCP_ENA_4"}, 10131 {"bits": [5, 5], "name": "UCP_ENA_5"}, 10132 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, 10133 {"bits": [14, 15], "name": "PS_UCP_MODE"}, 10134 {"bits": [16, 16], "name": "CLIP_DISABLE"}, 10135 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, 10136 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, 10137 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, 10138 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, 10139 {"bits": [21, 21], "name": "VTX_KILL_OR"}, 10140 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, 10141 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, 10142 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, 10143 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, 10144 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} 10145 ] 10146 }, 10147 "PA_CL_CNTL_STATUS": { 10148 "fields": [ 10149 {"bits": [31, 31], "name": "CL_BUSY"} 10150 ] 10151 }, 10152 "PA_CL_ENHANCE": { 10153 "fields": [ 10154 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"}, 10155 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"}, 10156 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"}, 10157 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"}, 10158 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"}, 10159 {"bits": [28, 28], "name": "ECO_SPARE3"}, 10160 {"bits": [29, 29], "name": "ECO_SPARE2"}, 10161 {"bits": [30, 30], "name": "ECO_SPARE1"}, 10162 {"bits": [31, 31], "name": "ECO_SPARE0"} 10163 ] 10164 }, 10165 "PA_CL_GB_HORZ_CLIP_ADJ": { 10166 "fields": [ 10167 {"bits": [0, 31], "name": "DATA_REGISTER"} 10168 ] 10169 }, 10170 "PA_CL_NANINF_CNTL": { 10171 "fields": [ 10172 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, 10173 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, 10174 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, 10175 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, 10176 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, 10177 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, 10178 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, 10179 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, 10180 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, 10181 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, 10182 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, 10183 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, 10184 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, 10185 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, 10186 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, 10187 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} 10188 ] 10189 }, 10190 "PA_CL_VPORT_XOFFSET": { 10191 "fields": [ 10192 {"bits": [0, 31], "name": "VPORT_XOFFSET"} 10193 ] 10194 }, 10195 "PA_CL_VPORT_XSCALE": { 10196 "fields": [ 10197 {"bits": [0, 31], "name": "VPORT_XSCALE"} 10198 ] 10199 }, 10200 "PA_CL_VPORT_YOFFSET": { 10201 "fields": [ 10202 {"bits": [0, 31], "name": "VPORT_YOFFSET"} 10203 ] 10204 }, 10205 "PA_CL_VPORT_YSCALE": { 10206 "fields": [ 10207 {"bits": [0, 31], "name": "VPORT_YSCALE"} 10208 ] 10209 }, 10210 "PA_CL_VPORT_ZOFFSET": { 10211 "fields": [ 10212 {"bits": [0, 31], "name": "VPORT_ZOFFSET"} 10213 ] 10214 }, 10215 "PA_CL_VPORT_ZSCALE": { 10216 "fields": [ 10217 {"bits": [0, 31], "name": "VPORT_ZSCALE"} 10218 ] 10219 }, 10220 "PA_CL_VS_OUT_CNTL": { 10221 "fields": [ 10222 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, 10223 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, 10224 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, 10225 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, 10226 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, 10227 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, 10228 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, 10229 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, 10230 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, 10231 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, 10232 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, 10233 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, 10234 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, 10235 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, 10236 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, 10237 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, 10238 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, 10239 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, 10240 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, 10241 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, 10242 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, 10243 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, 10244 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, 10245 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, 10246 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, 10247 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"} 10248 ] 10249 }, 10250 "PA_CL_VTE_CNTL": { 10251 "fields": [ 10252 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, 10253 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, 10254 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, 10255 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, 10256 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, 10257 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, 10258 {"bits": [8, 8], "name": "VTX_XY_FMT"}, 10259 {"bits": [9, 9], "name": "VTX_Z_FMT"}, 10260 {"bits": [10, 10], "name": "VTX_W0_FMT"}, 10261 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} 10262 ] 10263 }, 10264 "PA_SC_AA_CONFIG": { 10265 "fields": [ 10266 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, 10267 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, 10268 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, 10269 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, 10270 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} 10271 ] 10272 }, 10273 "PA_SC_AA_MASK_X0Y0_X1Y0": { 10274 "fields": [ 10275 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, 10276 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} 10277 ] 10278 }, 10279 "PA_SC_AA_MASK_X0Y1_X1Y1": { 10280 "fields": [ 10281 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, 10282 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} 10283 ] 10284 }, 10285 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": { 10286 "fields": [ 10287 {"bits": [0, 3], "name": "S0_X"}, 10288 {"bits": [4, 7], "name": "S0_Y"}, 10289 {"bits": [8, 11], "name": "S1_X"}, 10290 {"bits": [12, 15], "name": "S1_Y"}, 10291 {"bits": [16, 19], "name": "S2_X"}, 10292 {"bits": [20, 23], "name": "S2_Y"}, 10293 {"bits": [24, 27], "name": "S3_X"}, 10294 {"bits": [28, 31], "name": "S3_Y"} 10295 ] 10296 }, 10297 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": { 10298 "fields": [ 10299 {"bits": [0, 3], "name": "S4_X"}, 10300 {"bits": [4, 7], "name": "S4_Y"}, 10301 {"bits": [8, 11], "name": "S5_X"}, 10302 {"bits": [12, 15], "name": "S5_Y"}, 10303 {"bits": [16, 19], "name": "S6_X"}, 10304 {"bits": [20, 23], "name": "S6_Y"}, 10305 {"bits": [24, 27], "name": "S7_X"}, 10306 {"bits": [28, 31], "name": "S7_Y"} 10307 ] 10308 }, 10309 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": { 10310 "fields": [ 10311 {"bits": [0, 3], "name": "S8_X"}, 10312 {"bits": [4, 7], "name": "S8_Y"}, 10313 {"bits": [8, 11], "name": "S9_X"}, 10314 {"bits": [12, 15], "name": "S9_Y"}, 10315 {"bits": [16, 19], "name": "S10_X"}, 10316 {"bits": [20, 23], "name": "S10_Y"}, 10317 {"bits": [24, 27], "name": "S11_X"}, 10318 {"bits": [28, 31], "name": "S11_Y"} 10319 ] 10320 }, 10321 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": { 10322 "fields": [ 10323 {"bits": [0, 3], "name": "S12_X"}, 10324 {"bits": [4, 7], "name": "S12_Y"}, 10325 {"bits": [8, 11], "name": "S13_X"}, 10326 {"bits": [12, 15], "name": "S13_Y"}, 10327 {"bits": [16, 19], "name": "S14_X"}, 10328 {"bits": [20, 23], "name": "S14_Y"}, 10329 {"bits": [24, 27], "name": "S15_X"}, 10330 {"bits": [28, 31], "name": "S15_Y"} 10331 ] 10332 }, 10333 "PA_SC_CENTROID_PRIORITY_0": { 10334 "fields": [ 10335 {"bits": [0, 3], "name": "DISTANCE_0"}, 10336 {"bits": [4, 7], "name": "DISTANCE_1"}, 10337 {"bits": [8, 11], "name": "DISTANCE_2"}, 10338 {"bits": [12, 15], "name": "DISTANCE_3"}, 10339 {"bits": [16, 19], "name": "DISTANCE_4"}, 10340 {"bits": [20, 23], "name": "DISTANCE_5"}, 10341 {"bits": [24, 27], "name": "DISTANCE_6"}, 10342 {"bits": [28, 31], "name": "DISTANCE_7"} 10343 ] 10344 }, 10345 "PA_SC_CENTROID_PRIORITY_1": { 10346 "fields": [ 10347 {"bits": [0, 3], "name": "DISTANCE_8"}, 10348 {"bits": [4, 7], "name": "DISTANCE_9"}, 10349 {"bits": [8, 11], "name": "DISTANCE_10"}, 10350 {"bits": [12, 15], "name": "DISTANCE_11"}, 10351 {"bits": [16, 19], "name": "DISTANCE_12"}, 10352 {"bits": [20, 23], "name": "DISTANCE_13"}, 10353 {"bits": [24, 27], "name": "DISTANCE_14"}, 10354 {"bits": [28, 31], "name": "DISTANCE_15"} 10355 ] 10356 }, 10357 "PA_SC_CLIPRECT_0_BR": { 10358 "fields": [ 10359 {"bits": [0, 14], "name": "BR_X"}, 10360 {"bits": [16, 30], "name": "BR_Y"} 10361 ] 10362 }, 10363 "PA_SC_CLIPRECT_0_TL": { 10364 "fields": [ 10365 {"bits": [0, 14], "name": "TL_X"}, 10366 {"bits": [16, 30], "name": "TL_Y"} 10367 ] 10368 }, 10369 "PA_SC_CLIPRECT_RULE": { 10370 "fields": [ 10371 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} 10372 ] 10373 }, 10374 "PA_SC_DEBUG_CNTL": { 10375 "fields": [ 10376 {"bits": [0, 5], "name": "SC_DEBUG_INDX"} 10377 ] 10378 }, 10379 "PA_SC_EDGERULE": { 10380 "fields": [ 10381 {"bits": [0, 3], "name": "ER_TRI"}, 10382 {"bits": [4, 7], "name": "ER_POINT"}, 10383 {"bits": [8, 11], "name": "ER_RECT"}, 10384 {"bits": [12, 17], "name": "ER_LINE_LR"}, 10385 {"bits": [18, 23], "name": "ER_LINE_RL"}, 10386 {"bits": [24, 27], "name": "ER_LINE_TB"}, 10387 {"bits": [28, 31], "name": "ER_LINE_BT"} 10388 ] 10389 }, 10390 "PA_SC_ENHANCE": { 10391 "fields": [ 10392 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"}, 10393 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"}, 10394 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"}, 10395 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"}, 10396 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"}, 10397 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"}, 10398 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"}, 10399 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"}, 10400 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"}, 10401 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"}, 10402 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"}, 10403 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"}, 10404 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"}, 10405 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"}, 10406 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"}, 10407 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"}, 10408 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"}, 10409 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"}, 10410 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"}, 10411 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"}, 10412 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"}, 10413 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"}, 10414 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"}, 10415 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"}, 10416 {"bits": [30, 30], "name": "ECO_SPARE1"}, 10417 {"bits": [31, 31], "name": "ECO_SPARE0"} 10418 ] 10419 }, 10420 "PA_SC_FIFO_DEPTH_CNTL": { 10421 "fields": [ 10422 {"bits": [0, 7], "name": "DEPTH"} 10423 ] 10424 }, 10425 "PA_SC_FIFO_SIZE": { 10426 "fields": [ 10427 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"}, 10428 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"}, 10429 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"}, 10430 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"} 10431 ] 10432 }, 10433 "PA_SC_FORCE_EOV_MAX_CNTS": { 10434 "fields": [ 10435 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"}, 10436 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"} 10437 ] 10438 }, 10439 "PA_SC_GENERIC_SCISSOR_TL": { 10440 "fields": [ 10441 {"bits": [0, 14], "name": "TL_X"}, 10442 {"bits": [16, 30], "name": "TL_Y"}, 10443 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} 10444 ] 10445 }, 10446 "PA_SC_IF_FIFO_SIZE": { 10447 "fields": [ 10448 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"}, 10449 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"}, 10450 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"}, 10451 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"} 10452 ] 10453 }, 10454 "PA_SC_LINE_CNTL": { 10455 "fields": [ 10456 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, 10457 {"bits": [10, 10], "name": "LAST_PIXEL"}, 10458 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, 10459 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} 10460 ] 10461 }, 10462 "PA_SC_LINE_STIPPLE": { 10463 "fields": [ 10464 {"bits": [0, 15], "name": "LINE_PATTERN"}, 10465 {"bits": [16, 23], "name": "REPEAT_COUNT"}, 10466 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, 10467 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} 10468 ] 10469 }, 10470 "PA_SC_LINE_STIPPLE_STATE": { 10471 "fields": [ 10472 {"bits": [0, 3], "name": "CURRENT_PTR"}, 10473 {"bits": [8, 15], "name": "CURRENT_COUNT"} 10474 ] 10475 }, 10476 "PA_SC_MODE_CNTL_0": { 10477 "fields": [ 10478 {"bits": [0, 0], "name": "MSAA_ENABLE"}, 10479 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, 10480 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, 10481 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} 10482 ] 10483 }, 10484 "PA_SC_MODE_CNTL_1": { 10485 "fields": [ 10486 {"bits": [0, 0], "name": "WALK_SIZE"}, 10487 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, 10488 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, 10489 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, 10490 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, 10491 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, 10492 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, 10493 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, 10494 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, 10495 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, 10496 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, 10497 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, 10498 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, 10499 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, 10500 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, 10501 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, 10502 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, 10503 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, 10504 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, 10505 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, 10506 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, 10507 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, 10508 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, 10509 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} 10510 ] 10511 }, 10512 "PA_SC_PERFCOUNTER0_SELECT": { 10513 "fields": [ 10514 {"bits": [0, 8], "name": "PERF_SEL"}, 10515 {"bits": [10, 19], "name": "PERF_SEL1"}, 10516 {"bits": [20, 23], "name": "CNTR_MODE"} 10517 ] 10518 }, 10519 "PA_SC_PERFCOUNTER1_SELECT": { 10520 "fields": [ 10521 {"bits": [0, 8], "name": "PERF_SEL"} 10522 ] 10523 }, 10524 "PA_SC_RASTER_CONFIG": { 10525 "fields": [ 10526 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, 10527 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, 10528 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, 10529 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, 10530 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, 10531 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, 10532 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, 10533 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, 10534 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, 10535 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, 10536 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, 10537 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, 10538 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, 10539 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, 10540 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} 10541 ] 10542 }, 10543 "PA_SC_SCREEN_SCISSOR_BR": { 10544 "fields": [ 10545 {"bits": [0, 15], "name": "BR_X"}, 10546 {"bits": [16, 31], "name": "BR_Y"} 10547 ] 10548 }, 10549 "PA_SC_SCREEN_SCISSOR_TL": { 10550 "fields": [ 10551 {"bits": [0, 15], "name": "TL_X"}, 10552 {"bits": [16, 31], "name": "TL_Y"} 10553 ] 10554 }, 10555 "PA_SC_VPORT_ZMAX_0": { 10556 "fields": [ 10557 {"bits": [0, 31], "name": "VPORT_ZMAX"} 10558 ] 10559 }, 10560 "PA_SC_VPORT_ZMIN_0": { 10561 "fields": [ 10562 {"bits": [0, 31], "name": "VPORT_ZMIN"} 10563 ] 10564 }, 10565 "PA_SC_WINDOW_OFFSET": { 10566 "fields": [ 10567 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, 10568 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} 10569 ] 10570 }, 10571 "PA_SU_CNTL_STATUS": { 10572 "fields": [ 10573 {"bits": [31, 31], "name": "SU_BUSY"} 10574 ] 10575 }, 10576 "PA_SU_DEBUG_CNTL": { 10577 "fields": [ 10578 {"bits": [0, 4], "name": "SU_DEBUG_INDX"} 10579 ] 10580 }, 10581 "PA_SU_HARDWARE_SCREEN_OFFSET": { 10582 "fields": [ 10583 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, 10584 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} 10585 ] 10586 }, 10587 "PA_SU_LINE_CNTL": { 10588 "fields": [ 10589 {"bits": [0, 15], "name": "WIDTH"} 10590 ] 10591 }, 10592 "PA_SU_LINE_STIPPLE_CNTL": { 10593 "fields": [ 10594 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, 10595 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, 10596 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, 10597 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} 10598 ] 10599 }, 10600 "PA_SU_LINE_STIPPLE_SCALE": { 10601 "fields": [ 10602 {"bits": [0, 31], "name": "LINE_STIPPLE_SCALE"} 10603 ] 10604 }, 10605 "PA_SU_LINE_STIPPLE_VALUE": { 10606 "fields": [ 10607 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} 10608 ] 10609 }, 10610 "PA_SU_PERFCOUNTER0_HI": { 10611 "fields": [ 10612 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} 10613 ] 10614 }, 10615 "PA_SU_PERFCOUNTER0_SELECT": { 10616 "fields": [ 10617 {"bits": [0, 7], "name": "PERF_SEL"}, 10618 {"bits": [10, 19], "name": "PERF_SEL1"}, 10619 {"bits": [20, 23], "name": "CNTR_MODE"} 10620 ] 10621 }, 10622 "PA_SU_PERFCOUNTER2_SELECT": { 10623 "fields": [ 10624 {"bits": [0, 7], "name": "PERF_SEL"}, 10625 {"bits": [20, 23], "name": "CNTR_MODE"} 10626 ] 10627 }, 10628 "PA_SU_POINT_MINMAX": { 10629 "fields": [ 10630 {"bits": [0, 15], "name": "MIN_SIZE"}, 10631 {"bits": [16, 31], "name": "MAX_SIZE"} 10632 ] 10633 }, 10634 "PA_SU_POINT_SIZE": { 10635 "fields": [ 10636 {"bits": [0, 15], "name": "HEIGHT"}, 10637 {"bits": [16, 31], "name": "WIDTH"} 10638 ] 10639 }, 10640 "PA_SU_POLY_OFFSET_BACK_OFFSET": { 10641 "fields": [ 10642 {"bits": [0, 31], "name": "OFFSET"} 10643 ] 10644 }, 10645 "PA_SU_POLY_OFFSET_BACK_SCALE": { 10646 "fields": [ 10647 {"bits": [0, 31], "name": "SCALE"} 10648 ] 10649 }, 10650 "PA_SU_POLY_OFFSET_CLAMP": { 10651 "fields": [ 10652 {"bits": [0, 31], "name": "CLAMP"} 10653 ] 10654 }, 10655 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": { 10656 "fields": [ 10657 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, 10658 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} 10659 ] 10660 }, 10661 "PA_SU_PRIM_FILTER_CNTL": { 10662 "fields": [ 10663 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, 10664 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, 10665 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, 10666 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, 10667 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, 10668 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, 10669 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, 10670 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, 10671 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, 10672 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, 10673 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} 10674 ] 10675 }, 10676 "PA_SU_SC_MODE_CNTL": { 10677 "fields": [ 10678 {"bits": [0, 0], "name": "CULL_FRONT"}, 10679 {"bits": [1, 1], "name": "CULL_BACK"}, 10680 {"bits": [2, 2], "name": "FACE"}, 10681 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, 10682 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"}, 10683 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"}, 10684 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, 10685 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, 10686 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, 10687 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, 10688 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, 10689 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, 10690 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} 10691 ] 10692 }, 10693 "PA_SU_VTX_CNTL": { 10694 "fields": [ 10695 {"bits": [0, 0], "name": "PIX_CENTER"}, 10696 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, 10697 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} 10698 ] 10699 }, 10700 "SCRATCH_ADDR": { 10701 "fields": [ 10702 {"bits": [0, 31], "name": "OBSOLETE_ADDR"} 10703 ] 10704 }, 10705 "SCRATCH_UMSK": { 10706 "fields": [ 10707 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, 10708 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} 10709 ] 10710 }, 10711 "SPI_BARYC_CNTL": { 10712 "fields": [ 10713 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, 10714 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, 10715 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, 10716 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, 10717 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, 10718 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, 10719 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} 10720 ] 10721 }, 10722 "SPI_CONFIG_CNTL": { 10723 "fields": [ 10724 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, 10725 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, 10726 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, 10727 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, 10728 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, 10729 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} 10730 ] 10731 }, 10732 "SPI_INTERP_CONTROL_0": { 10733 "fields": [ 10734 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, 10735 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, 10736 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, 10737 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, 10738 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, 10739 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, 10740 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} 10741 ] 10742 }, 10743 "SPI_PS_INPUT_ADDR": { 10744 "fields": [ 10745 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, 10746 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, 10747 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, 10748 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, 10749 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, 10750 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, 10751 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, 10752 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, 10753 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, 10754 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, 10755 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, 10756 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, 10757 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, 10758 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, 10759 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, 10760 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} 10761 ] 10762 }, 10763 "SPI_PS_INPUT_CNTL_0": { 10764 "fields": [ 10765 {"bits": [0, 5], "name": "OFFSET"}, 10766 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 10767 {"bits": [10, 10], "name": "FLAT_SHADE"}, 10768 {"bits": [13, 16], "name": "CYL_WRAP"}, 10769 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, 10770 {"bits": [18, 18], "name": "DUP"} 10771 ] 10772 }, 10773 "SPI_PS_INPUT_CNTL_20": { 10774 "fields": [ 10775 {"bits": [0, 5], "name": "OFFSET"}, 10776 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 10777 {"bits": [10, 10], "name": "FLAT_SHADE"}, 10778 {"bits": [18, 18], "name": "DUP"} 10779 ] 10780 }, 10781 "SPI_PS_IN_CONTROL": { 10782 "fields": [ 10783 {"bits": [0, 5], "name": "NUM_INTERP"}, 10784 {"bits": [6, 6], "name": "PARAM_GEN"}, 10785 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} 10786 ] 10787 }, 10788 "SPI_SHADER_COL_FORMAT": { 10789 "fields": [ 10790 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, 10791 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, 10792 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, 10793 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, 10794 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, 10795 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, 10796 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, 10797 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} 10798 ] 10799 }, 10800 "SPI_SHADER_PGM_HI_ES": { 10801 "fields": [ 10802 {"bits": [0, 7], "name": "MEM_BASE"} 10803 ] 10804 }, 10805 "SPI_SHADER_PGM_LO_ES": { 10806 "fields": [ 10807 {"bits": [0, 31], "name": "MEM_BASE"} 10808 ] 10809 }, 10810 "SPI_SHADER_PGM_RSRC1_ES": { 10811 "fields": [ 10812 {"bits": [0, 5], "name": "VGPRS"}, 10813 {"bits": [6, 9], "name": "SGPRS"}, 10814 {"bits": [10, 11], "name": "PRIORITY"}, 10815 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10816 {"bits": [20, 20], "name": "PRIV"}, 10817 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10818 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10819 {"bits": [23, 23], "name": "IEEE_MODE"}, 10820 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 10821 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 10822 {"bits": [27, 29], "name": "CACHE_CTL"}, 10823 {"bits": [30, 30], "name": "CDBG_USER"} 10824 ] 10825 }, 10826 "SPI_SHADER_PGM_RSRC1_GS": { 10827 "fields": [ 10828 {"bits": [0, 5], "name": "VGPRS"}, 10829 {"bits": [6, 9], "name": "SGPRS"}, 10830 {"bits": [10, 11], "name": "PRIORITY"}, 10831 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10832 {"bits": [20, 20], "name": "PRIV"}, 10833 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10834 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10835 {"bits": [23, 23], "name": "IEEE_MODE"}, 10836 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, 10837 {"bits": [25, 27], "name": "CACHE_CTL"}, 10838 {"bits": [28, 28], "name": "CDBG_USER"} 10839 ] 10840 }, 10841 "SPI_SHADER_PGM_RSRC1_HS": { 10842 "fields": [ 10843 {"bits": [0, 5], "name": "VGPRS"}, 10844 {"bits": [6, 9], "name": "SGPRS"}, 10845 {"bits": [10, 11], "name": "PRIORITY"}, 10846 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10847 {"bits": [20, 20], "name": "PRIV"}, 10848 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10849 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10850 {"bits": [23, 23], "name": "IEEE_MODE"}, 10851 {"bits": [24, 26], "name": "CACHE_CTL"}, 10852 {"bits": [27, 27], "name": "CDBG_USER"} 10853 ] 10854 }, 10855 "SPI_SHADER_PGM_RSRC1_LS": { 10856 "fields": [ 10857 {"bits": [0, 5], "name": "VGPRS"}, 10858 {"bits": [6, 9], "name": "SGPRS"}, 10859 {"bits": [10, 11], "name": "PRIORITY"}, 10860 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10861 {"bits": [20, 20], "name": "PRIV"}, 10862 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10863 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10864 {"bits": [23, 23], "name": "IEEE_MODE"}, 10865 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 10866 {"bits": [26, 28], "name": "CACHE_CTL"}, 10867 {"bits": [29, 29], "name": "CDBG_USER"} 10868 ] 10869 }, 10870 "SPI_SHADER_PGM_RSRC1_PS": { 10871 "fields": [ 10872 {"bits": [0, 5], "name": "VGPRS"}, 10873 {"bits": [6, 9], "name": "SGPRS"}, 10874 {"bits": [10, 11], "name": "PRIORITY"}, 10875 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 10876 {"bits": [20, 20], "name": "PRIV"}, 10877 {"bits": [21, 21], "name": "DX10_CLAMP"}, 10878 {"bits": [22, 22], "name": "DEBUG_MODE"}, 10879 {"bits": [23, 23], "name": "IEEE_MODE"}, 10880 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, 10881 {"bits": [25, 27], "name": "CACHE_CTL"}, 10882 {"bits": [28, 28], "name": "CDBG_USER"} 10883 ] 10884 }, 10885 "SPI_SHADER_PGM_RSRC2_ES": { 10886 "fields": [ 10887 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10888 {"bits": [1, 5], "name": "USER_SGPR"}, 10889 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10890 {"bits": [7, 7], "name": "OC_LDS_EN"}, 10891 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 10892 {"bits": [20, 28], "name": "LDS_SIZE"} 10893 ] 10894 }, 10895 "SPI_SHADER_PGM_RSRC2_GS": { 10896 "fields": [ 10897 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10898 {"bits": [1, 5], "name": "USER_SGPR"}, 10899 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10900 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 10901 ] 10902 }, 10903 "SPI_SHADER_PGM_RSRC2_HS": { 10904 "fields": [ 10905 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10906 {"bits": [1, 5], "name": "USER_SGPR"}, 10907 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10908 {"bits": [7, 7], "name": "OC_LDS_EN"}, 10909 {"bits": [8, 8], "name": "TG_SIZE_EN"}, 10910 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 10911 ] 10912 }, 10913 "SPI_SHADER_PGM_RSRC2_LS": { 10914 "fields": [ 10915 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10916 {"bits": [1, 5], "name": "USER_SGPR"}, 10917 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10918 {"bits": [7, 15], "name": "LDS_SIZE"}, 10919 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 10920 ] 10921 }, 10922 "SPI_SHADER_PGM_RSRC2_PS": { 10923 "fields": [ 10924 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10925 {"bits": [1, 5], "name": "USER_SGPR"}, 10926 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10927 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, 10928 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, 10929 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 10930 ] 10931 }, 10932 "SPI_SHADER_PGM_RSRC2_VS": { 10933 "fields": [ 10934 {"bits": [0, 0], "name": "SCRATCH_EN"}, 10935 {"bits": [1, 5], "name": "USER_SGPR"}, 10936 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 10937 {"bits": [7, 7], "name": "OC_LDS_EN"}, 10938 {"bits": [8, 8], "name": "SO_BASE0_EN"}, 10939 {"bits": [9, 9], "name": "SO_BASE1_EN"}, 10940 {"bits": [10, 10], "name": "SO_BASE2_EN"}, 10941 {"bits": [11, 11], "name": "SO_BASE3_EN"}, 10942 {"bits": [12, 12], "name": "SO_EN"}, 10943 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 10944 ] 10945 }, 10946 "SPI_SHADER_POS_FORMAT": { 10947 "fields": [ 10948 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, 10949 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, 10950 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, 10951 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} 10952 ] 10953 }, 10954 "SPI_SHADER_Z_FORMAT": { 10955 "fields": [ 10956 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} 10957 ] 10958 }, 10959 "SPI_VS_OUT_CONFIG": { 10960 "fields": [ 10961 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, 10962 {"bits": [6, 6], "name": "VS_HALF_PACK"} 10963 ] 10964 }, 10965 "SQC_CACHES": { 10966 "fields": [ 10967 {"bits": [0, 0], "name": "INST_INVALIDATE"}, 10968 {"bits": [1, 1], "name": "DATA_INVALIDATE"}, 10969 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"} 10970 ] 10971 }, 10972 "SQC_CONFIG": { 10973 "fields": [ 10974 {"bits": [0, 1], "name": "INST_CACHE_SIZE"}, 10975 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"}, 10976 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"}, 10977 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"}, 10978 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"}, 10979 {"bits": [8, 8], "name": "FORCE_IN_ORDER"}, 10980 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"}, 10981 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"}, 10982 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"} 10983 ] 10984 }, 10985 "SQC_SECDED_CNT": { 10986 "fields": [ 10987 {"bits": [0, 7], "name": "INST_SEC"}, 10988 {"bits": [8, 15], "name": "INST_DED"}, 10989 {"bits": [16, 23], "name": "DATA_SEC"}, 10990 {"bits": [24, 31], "name": "DATA_DED"} 10991 ] 10992 }, 10993 "SQ_ALU_CLK_CTRL": { 10994 "fields": [ 10995 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"}, 10996 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"} 10997 ] 10998 }, 10999 "SQ_BUF_RSRC_WORD0": { 11000 "fields": [ 11001 {"bits": [0, 31], "name": "BASE_ADDRESS"} 11002 ] 11003 }, 11004 "SQ_BUF_RSRC_WORD1": { 11005 "fields": [ 11006 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, 11007 {"bits": [16, 29], "name": "STRIDE"}, 11008 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, 11009 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} 11010 ] 11011 }, 11012 "SQ_BUF_RSRC_WORD2": { 11013 "fields": [ 11014 {"bits": [0, 31], "name": "NUM_RECORDS"} 11015 ] 11016 }, 11017 "SQ_BUF_RSRC_WORD3": { 11018 "fields": [ 11019 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 11020 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 11021 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 11022 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 11023 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, 11024 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, 11025 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, 11026 {"bits": [21, 22], "name": "INDEX_STRIDE"}, 11027 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, 11028 {"bits": [24, 24], "name": "ATC"}, 11029 {"bits": [25, 25], "name": "HASH_ENABLE"}, 11030 {"bits": [26, 26], "name": "HEAP"}, 11031 {"bits": [27, 29], "name": "MTYPE"}, 11032 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} 11033 ] 11034 }, 11035 "SQ_CONFIG": { 11036 "fields": [ 11037 {"bits": [0, 7], "name": "UNUSED"}, 11038 {"bits": [8, 8], "name": "DEBUG_EN"}, 11039 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"}, 11040 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"}, 11041 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"}, 11042 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"}, 11043 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"}, 11044 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"}, 11045 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"} 11046 ] 11047 }, 11048 "SQ_DEBUG_STS_GLOBAL": { 11049 "fields": [ 11050 {"bits": [0, 0], "name": "BUSY"}, 11051 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"}, 11052 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"}, 11053 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"} 11054 ] 11055 }, 11056 "SQ_DED_CNT": { 11057 "fields": [ 11058 {"bits": [0, 5], "name": "LDS_DED"}, 11059 {"bits": [8, 12], "name": "SGPR_DED"}, 11060 {"bits": [16, 24], "name": "VGPR_DED"} 11061 ] 11062 }, 11063 "SQ_DED_INFO": { 11064 "fields": [ 11065 {"bits": [0, 3], "name": "WAVE_ID"}, 11066 {"bits": [4, 5], "name": "SIMD_ID"}, 11067 {"bits": [6, 8], "name": "SOURCE"}, 11068 {"bits": [9, 12], "name": "VM_ID"} 11069 ] 11070 }, 11071 "SQ_FIFO_SIZES": { 11072 "fields": [ 11073 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"}, 11074 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"}, 11075 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"}, 11076 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"} 11077 ] 11078 }, 11079 "SQ_IMG_RSRC_WORD1": { 11080 "fields": [ 11081 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, 11082 {"bits": [8, 19], "name": "MIN_LOD"}, 11083 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, 11084 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, 11085 {"bits": [30, 31], "name": "MTYPE"} 11086 ] 11087 }, 11088 "SQ_IMG_RSRC_WORD2": { 11089 "fields": [ 11090 {"bits": [0, 13], "name": "WIDTH"}, 11091 {"bits": [14, 27], "name": "HEIGHT"}, 11092 {"bits": [28, 30], "name": "PERF_MOD"}, 11093 {"bits": [31, 31], "name": "INTERLACED"} 11094 ] 11095 }, 11096 "SQ_IMG_RSRC_WORD3": { 11097 "fields": [ 11098 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 11099 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 11100 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 11101 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 11102 {"bits": [12, 15], "name": "BASE_LEVEL"}, 11103 {"bits": [16, 19], "name": "LAST_LEVEL"}, 11104 {"bits": [20, 24], "name": "TILING_INDEX"}, 11105 {"bits": [25, 25], "name": "POW2_PAD"}, 11106 {"bits": [26, 26], "name": "MTYPE"}, 11107 {"bits": [27, 27], "name": "ATC"}, 11108 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} 11109 ] 11110 }, 11111 "SQ_IMG_RSRC_WORD4": { 11112 "fields": [ 11113 {"bits": [0, 12], "name": "DEPTH"}, 11114 {"bits": [13, 26], "name": "PITCH"} 11115 ] 11116 }, 11117 "SQ_IMG_RSRC_WORD5": { 11118 "fields": [ 11119 {"bits": [0, 12], "name": "BASE_ARRAY"}, 11120 {"bits": [13, 25], "name": "LAST_ARRAY"} 11121 ] 11122 }, 11123 "SQ_IMG_RSRC_WORD6": { 11124 "fields": [ 11125 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, 11126 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, 11127 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, 11128 {"bits": [21, 31], "name": "UNUNSED"} 11129 ] 11130 }, 11131 "SQ_IMG_RSRC_WORD7": { 11132 "fields": [ 11133 {"bits": [0, 31], "name": "UNUNSED"} 11134 ] 11135 }, 11136 "SQ_IMG_SAMP_WORD0": { 11137 "fields": [ 11138 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, 11139 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, 11140 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, 11141 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, 11142 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, 11143 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, 11144 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, 11145 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, 11146 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, 11147 {"bits": [21, 26], "name": "ANISO_BIAS"}, 11148 {"bits": [27, 27], "name": "TRUNC_COORD"}, 11149 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, 11150 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} 11151 ] 11152 }, 11153 "SQ_IMG_SAMP_WORD1": { 11154 "fields": [ 11155 {"bits": [0, 11], "name": "MIN_LOD"}, 11156 {"bits": [12, 23], "name": "MAX_LOD"}, 11157 {"bits": [24, 27], "name": "PERF_MIP"}, 11158 {"bits": [28, 31], "name": "PERF_Z"} 11159 ] 11160 }, 11161 "SQ_IMG_SAMP_WORD2": { 11162 "fields": [ 11163 {"bits": [0, 13], "name": "LOD_BIAS"}, 11164 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, 11165 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, 11166 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, 11167 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, 11168 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, 11169 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, 11170 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, 11171 {"bits": [30, 30], "name": "FILTER_PREC_FIX"} 11172 ] 11173 }, 11174 "SQ_IMG_SAMP_WORD3": { 11175 "fields": [ 11176 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, 11177 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, 11178 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} 11179 ] 11180 }, 11181 "SQ_IND_INDEX": { 11182 "fields": [ 11183 {"bits": [0, 3], "name": "WAVE_ID"}, 11184 {"bits": [4, 5], "name": "SIMD_ID"}, 11185 {"bits": [6, 11], "name": "THREAD_ID"}, 11186 {"bits": [12, 12], "name": "AUTO_INCR"}, 11187 {"bits": [13, 13], "name": "FORCE_READ"}, 11188 {"bits": [14, 14], "name": "READ_TIMEOUT"}, 11189 {"bits": [15, 15], "name": "UNINDEXED"}, 11190 {"bits": [16, 31], "name": "INDEX"} 11191 ] 11192 }, 11193 "SQ_INTERRUPT_WORD_AUTO": { 11194 "fields": [ 11195 {"bits": [0, 0], "name": "THREAD_TRACE"}, 11196 {"bits": [1, 1], "name": "WLT"}, 11197 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"}, 11198 {"bits": [3, 3], "name": "REG_TIMESTAMP"}, 11199 {"bits": [4, 4], "name": "CMD_TIMESTAMP"}, 11200 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"}, 11201 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"}, 11202 {"bits": [7, 7], "name": "IMMED_OVERFLOW"}, 11203 {"bits": [25, 25], "name": "SE_ID"}, 11204 {"bits": [26, 27], "name": "ENCODING"} 11205 ] 11206 }, 11207 "SQ_LB_CTR_CTRL": { 11208 "fields": [ 11209 {"bits": [0, 0], "name": "START"}, 11210 {"bits": [1, 1], "name": "LOAD"}, 11211 {"bits": [2, 2], "name": "CLEAR"} 11212 ] 11213 }, 11214 "SQ_PERFCOUNTER0_SELECT": { 11215 "fields": [ 11216 {"bits": [0, 8], "name": "PERF_SEL"}, 11217 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, 11218 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, 11219 {"bits": [20, 23], "name": "SPM_MODE"}, 11220 {"bits": [24, 27], "name": "SIMD_MASK"}, 11221 {"bits": [28, 31], "name": "PERF_MODE"} 11222 ] 11223 }, 11224 "SQ_PERFCOUNTER_CTRL": { 11225 "fields": [ 11226 {"bits": [0, 0], "name": "PS_EN"}, 11227 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 11228 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 11229 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 11230 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 11231 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 11232 {"bits": [6, 6], "name": "CS_EN"}, 11233 {"bits": [8, 12], "name": "CNTR_RATE"}, 11234 {"bits": [13, 13], "name": "DISABLE_FLUSH"} 11235 ] 11236 }, 11237 "SQ_POWER_THROTTLE": { 11238 "fields": [ 11239 {"bits": [0, 13], "name": "MIN_POWER"}, 11240 {"bits": [16, 29], "name": "MAX_POWER"}, 11241 {"bits": [30, 31], "name": "PHASE_OFFSET"} 11242 ] 11243 }, 11244 "SQ_POWER_THROTTLE2": { 11245 "fields": [ 11246 {"bits": [0, 13], "name": "MAX_POWER_DELTA"}, 11247 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"}, 11248 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"}, 11249 {"bits": [31, 31], "name": "USE_REF_CLOCK"} 11250 ] 11251 }, 11252 "SQ_RANDOM_WAVE_PRI": { 11253 "fields": [ 11254 {"bits": [0, 6], "name": "RET"}, 11255 {"bits": [7, 9], "name": "RUI"}, 11256 {"bits": [10, 20], "name": "RNG"} 11257 ] 11258 }, 11259 "SQ_REG_CREDITS": { 11260 "fields": [ 11261 {"bits": [0, 5], "name": "SRBM_CREDITS"}, 11262 {"bits": [8, 11], "name": "CMD_CREDITS"}, 11263 {"bits": [28, 28], "name": "REG_BUSY"}, 11264 {"bits": [29, 29], "name": "SRBM_OVERFLOW"}, 11265 {"bits": [30, 30], "name": "IMMED_OVERFLOW"}, 11266 {"bits": [31, 31], "name": "CMD_OVERFLOW"} 11267 ] 11268 }, 11269 "SQ_SEC_CNT": { 11270 "fields": [ 11271 {"bits": [0, 5], "name": "LDS_SEC"}, 11272 {"bits": [8, 12], "name": "SGPR_SEC"}, 11273 {"bits": [16, 24], "name": "VGPR_SEC"} 11274 ] 11275 }, 11276 "SQ_THREAD_TRACE_BASE": { 11277 "fields": [ 11278 {"bits": [0, 31], "name": "ADDR"} 11279 ] 11280 }, 11281 "SQ_THREAD_TRACE_CNTR": { 11282 "fields": [ 11283 {"bits": [0, 31], "name": "CNTR"} 11284 ] 11285 }, 11286 "SQ_THREAD_TRACE_CTRL": { 11287 "fields": [ 11288 {"bits": [31, 31], "name": "RESET_BUFFER"} 11289 ] 11290 }, 11291 "SQ_THREAD_TRACE_HIWATER": { 11292 "fields": [ 11293 {"bits": [0, 2], "name": "HIWATER"} 11294 ] 11295 }, 11296 "SQ_THREAD_TRACE_MASK": { 11297 "fields": [ 11298 {"bits": [0, 4], "name": "CU_SEL"}, 11299 {"bits": [5, 5], "name": "SH_SEL"}, 11300 {"bits": [7, 7], "name": "REG_STALL_EN"}, 11301 {"bits": [12, 13], "name": "VM_ID_MASK"}, 11302 {"bits": [14, 14], "name": "SPI_STALL_EN"}, 11303 {"bits": [15, 15], "name": "SQ_STALL_EN"}, 11304 {"bits": [16, 31], "name": "RANDOM_SEED"}, 11305 {"bits": [16, 31], "name": "RANDOM_SEED"} 11306 ] 11307 }, 11308 "SQ_THREAD_TRACE_MODE": { 11309 "fields": [ 11310 {"bits": [0, 2], "name": "MASK_PS"}, 11311 {"bits": [3, 5], "name": "MASK_VS"}, 11312 {"bits": [6, 8], "name": "MASK_GS"}, 11313 {"bits": [9, 11], "name": "MASK_ES"}, 11314 {"bits": [12, 14], "name": "MASK_HS"}, 11315 {"bits": [15, 17], "name": "MASK_LS"}, 11316 {"bits": [18, 20], "name": "MASK_CS"}, 11317 {"bits": [21, 22], "name": "MODE"}, 11318 {"bits": [23, 24], "name": "CAPTURE_MODE"}, 11319 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, 11320 {"bits": [26, 26], "name": "PRIV"}, 11321 {"bits": [27, 28], "name": "ISSUE_MASK"}, 11322 {"bits": [29, 29], "name": "TEST_MODE"}, 11323 {"bits": [30, 30], "name": "INTERRUPT_EN"}, 11324 {"bits": [31, 31], "name": "WRAP"} 11325 ] 11326 }, 11327 "SQ_THREAD_TRACE_PERF_MASK": { 11328 "fields": [ 11329 {"bits": [0, 15], "name": "SH0_MASK"}, 11330 {"bits": [16, 31], "name": "SH1_MASK"} 11331 ] 11332 }, 11333 "SQ_THREAD_TRACE_SIZE": { 11334 "fields": [ 11335 {"bits": [0, 21], "name": "SIZE"} 11336 ] 11337 }, 11338 "SQ_THREAD_TRACE_STATUS": { 11339 "fields": [ 11340 {"bits": [0, 2], "name": "FINISH_PENDING"}, 11341 {"bits": [16, 18], "name": "FINISH_DONE"}, 11342 {"bits": [29, 29], "name": "NEW_BUF"}, 11343 {"bits": [30, 30], "name": "BUSY"}, 11344 {"bits": [31, 31], "name": "FULL"} 11345 ] 11346 }, 11347 "SQ_THREAD_TRACE_TOKEN_MASK": { 11348 "fields": [ 11349 {"bits": [0, 15], "name": "TOKEN_MASK"}, 11350 {"bits": [16, 23], "name": "REG_MASK"}, 11351 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} 11352 ] 11353 }, 11354 "SQ_THREAD_TRACE_WPTR": { 11355 "fields": [ 11356 {"bits": [0, 29], "name": "WPTR"}, 11357 {"bits": [30, 31], "name": "READ_OFFSET"} 11358 ] 11359 }, 11360 "SQ_TIME_HI": { 11361 "fields": [ 11362 {"bits": [0, 31], "name": "TIME"} 11363 ] 11364 }, 11365 "SQ_WAVE_EXEC_HI": { 11366 "fields": [ 11367 {"bits": [0, 31], "name": "EXEC_HI"} 11368 ] 11369 }, 11370 "SQ_WAVE_EXEC_LO": { 11371 "fields": [ 11372 {"bits": [0, 31], "name": "EXEC_LO"} 11373 ] 11374 }, 11375 "SQ_WAVE_GPR_ALLOC": { 11376 "fields": [ 11377 {"bits": [0, 5], "name": "VGPR_BASE"}, 11378 {"bits": [8, 13], "name": "VGPR_SIZE"}, 11379 {"bits": [16, 21], "name": "SGPR_BASE"}, 11380 {"bits": [24, 27], "name": "SGPR_SIZE"} 11381 ] 11382 }, 11383 "SQ_WAVE_HW_ID": { 11384 "fields": [ 11385 {"bits": [0, 3], "name": "WAVE_ID"}, 11386 {"bits": [4, 5], "name": "SIMD_ID"}, 11387 {"bits": [6, 7], "name": "PIPE_ID"}, 11388 {"bits": [8, 11], "name": "CU_ID"}, 11389 {"bits": [12, 12], "name": "SH_ID"}, 11390 {"bits": [13, 13], "name": "SE_ID"}, 11391 {"bits": [16, 19], "name": "TG_ID"}, 11392 {"bits": [20, 23], "name": "VM_ID"}, 11393 {"bits": [24, 26], "name": "QUEUE_ID"}, 11394 {"bits": [27, 29], "name": "STATE_ID"}, 11395 {"bits": [30, 31], "name": "ME_ID"} 11396 ] 11397 }, 11398 "SQ_WAVE_IB_DBG0": { 11399 "fields": [ 11400 {"bits": [0, 2], "name": "IBUF_ST"}, 11401 {"bits": [3, 3], "name": "PC_INVALID"}, 11402 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, 11403 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, 11404 {"bits": [8, 9], "name": "IBUF_RPTR"}, 11405 {"bits": [10, 11], "name": "IBUF_WPTR"}, 11406 {"bits": [16, 18], "name": "INST_STR_ST"}, 11407 {"bits": [19, 21], "name": "MISC_CNT"}, 11408 {"bits": [22, 23], "name": "ECC_ST"}, 11409 {"bits": [24, 24], "name": "IS_HYB"}, 11410 {"bits": [25, 26], "name": "HYB_CNT"}, 11411 {"bits": [27, 27], "name": "KILL"}, 11412 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"} 11413 ] 11414 }, 11415 "SQ_WAVE_IB_STS": { 11416 "fields": [ 11417 {"bits": [0, 3], "name": "VM_CNT"}, 11418 {"bits": [4, 6], "name": "EXP_CNT"}, 11419 {"bits": [8, 12], "name": "LGKM_CNT"}, 11420 {"bits": [13, 15], "name": "VALU_CNT"} 11421 ] 11422 }, 11423 "SQ_WAVE_INST_DW0": { 11424 "fields": [ 11425 {"bits": [0, 31], "name": "INST_DW0"} 11426 ] 11427 }, 11428 "SQ_WAVE_INST_DW1": { 11429 "fields": [ 11430 {"bits": [0, 31], "name": "INST_DW1"} 11431 ] 11432 }, 11433 "SQ_WAVE_LDS_ALLOC": { 11434 "fields": [ 11435 {"bits": [0, 7], "name": "LDS_BASE"}, 11436 {"bits": [12, 20], "name": "LDS_SIZE"} 11437 ] 11438 }, 11439 "SQ_WAVE_M0": { 11440 "fields": [ 11441 {"bits": [0, 31], "name": "M0"} 11442 ] 11443 }, 11444 "SQ_WAVE_MODE": { 11445 "fields": [ 11446 {"bits": [0, 3], "name": "FP_ROUND"}, 11447 {"bits": [4, 7], "name": "FP_DENORM"}, 11448 {"bits": [8, 8], "name": "DX10_CLAMP"}, 11449 {"bits": [9, 9], "name": "IEEE"}, 11450 {"bits": [10, 10], "name": "LOD_CLAMPED"}, 11451 {"bits": [11, 11], "name": "DEBUG_EN"}, 11452 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 11453 {"bits": [28, 28], "name": "VSKIP"}, 11454 {"bits": [29, 31], "name": "CSP"} 11455 ] 11456 }, 11457 "SQ_WAVE_PC_HI": { 11458 "fields": [ 11459 {"bits": [0, 7], "name": "PC_HI"} 11460 ] 11461 }, 11462 "SQ_WAVE_PC_LO": { 11463 "fields": [ 11464 {"bits": [0, 31], "name": "PC_LO"} 11465 ] 11466 }, 11467 "SQ_WAVE_STATUS": { 11468 "fields": [ 11469 {"bits": [0, 0], "name": "SCC"}, 11470 {"bits": [1, 2], "name": "SPI_PRIO"}, 11471 {"bits": [3, 4], "name": "WAVE_PRIO"}, 11472 {"bits": [5, 5], "name": "PRIV"}, 11473 {"bits": [6, 6], "name": "TRAP_EN"}, 11474 {"bits": [7, 7], "name": "TTRACE_EN"}, 11475 {"bits": [8, 8], "name": "EXPORT_RDY"}, 11476 {"bits": [9, 9], "name": "EXECZ"}, 11477 {"bits": [10, 10], "name": "VCCZ"}, 11478 {"bits": [11, 11], "name": "IN_TG"}, 11479 {"bits": [12, 12], "name": "IN_BARRIER"}, 11480 {"bits": [13, 13], "name": "HALT"}, 11481 {"bits": [14, 14], "name": "TRAP"}, 11482 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, 11483 {"bits": [16, 16], "name": "VALID"}, 11484 {"bits": [17, 17], "name": "ECC_ERR"}, 11485 {"bits": [18, 18], "name": "SKIP_EXPORT"}, 11486 {"bits": [19, 19], "name": "PERF_EN"}, 11487 {"bits": [20, 20], "name": "COND_DBG_USER"}, 11488 {"bits": [21, 21], "name": "COND_DBG_SYS"}, 11489 {"bits": [22, 22], "name": "DATA_ATC"}, 11490 {"bits": [23, 23], "name": "INST_ATC"}, 11491 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"}, 11492 {"bits": [27, 27], "name": "MUST_EXPORT"} 11493 ] 11494 }, 11495 "SQ_WAVE_TBA_HI": { 11496 "fields": [ 11497 {"bits": [0, 7], "name": "ADDR_HI"} 11498 ] 11499 }, 11500 "SQ_WAVE_TBA_LO": { 11501 "fields": [ 11502 {"bits": [0, 31], "name": "ADDR_LO"} 11503 ] 11504 }, 11505 "SQ_WAVE_TRAPSTS": { 11506 "fields": [ 11507 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"}, 11508 {"bits": [16, 21], "name": "EXCP_CYCLE"}, 11509 {"bits": [29, 31], "name": "DP_RATE"} 11510 ] 11511 }, 11512 "SQ_WAVE_TTMP0": { 11513 "fields": [ 11514 {"bits": [0, 31], "name": "DATA"} 11515 ] 11516 }, 11517 "TA_BC_BASE_ADDR": { 11518 "fields": [ 11519 {"bits": [0, 31], "name": "ADDRESS"} 11520 ] 11521 }, 11522 "VGT_CACHE_INVALIDATION": { 11523 "fields": [ 11524 {"bits": [0, 1], "name": "CACHE_INVALIDATION"}, 11525 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"}, 11526 {"bits": [6, 7], "name": "AUTO_INVLD_EN"}, 11527 {"bits": [9, 9], "name": "USE_GS_DONE"}, 11528 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"}, 11529 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"}, 11530 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"}, 11531 {"bits": [16, 20], "name": "ES_LIMIT"} 11532 ] 11533 }, 11534 "VGT_CNTL_STATUS": { 11535 "fields": [ 11536 {"bits": [0, 0], "name": "VGT_BUSY"}, 11537 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"}, 11538 {"bits": [2, 2], "name": "VGT_OUT_BUSY"}, 11539 {"bits": [3, 3], "name": "VGT_PT_BUSY"}, 11540 {"bits": [4, 4], "name": "VGT_TE_BUSY"}, 11541 {"bits": [5, 5], "name": "VGT_VR_BUSY"}, 11542 {"bits": [6, 6], "name": "VGT_PI_BUSY"}, 11543 {"bits": [7, 7], "name": "VGT_GS_BUSY"}, 11544 {"bits": [8, 8], "name": "VGT_HS_BUSY"}, 11545 {"bits": [9, 9], "name": "VGT_TE11_BUSY"} 11546 ] 11547 }, 11548 "VGT_DEBUG_CNTL": { 11549 "fields": [ 11550 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"}, 11551 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"} 11552 ] 11553 }, 11554 "VGT_DMA_BASE": { 11555 "fields": [ 11556 {"bits": [0, 31], "name": "BASE_ADDR"} 11557 ] 11558 }, 11559 "VGT_DMA_BASE_HI": { 11560 "fields": [ 11561 {"bits": [0, 7], "name": "BASE_ADDR"} 11562 ] 11563 }, 11564 "VGT_DMA_DATA_FIFO_DEPTH": { 11565 "fields": [ 11566 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"} 11567 ] 11568 }, 11569 "VGT_DMA_INDEX_TYPE": { 11570 "fields": [ 11571 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 11572 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, 11573 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, 11574 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 11575 {"bits": [8, 8], "name": "ATC"}, 11576 {"bits": [9, 9], "name": "NOT_EOP"}, 11577 {"bits": [10, 10], "name": "REQ_PATH"} 11578 ] 11579 }, 11580 "VGT_DMA_MAX_SIZE": { 11581 "fields": [ 11582 {"bits": [0, 31], "name": "MAX_SIZE"} 11583 ] 11584 }, 11585 "VGT_DMA_NUM_INSTANCES": { 11586 "fields": [ 11587 {"bits": [0, 31], "name": "NUM_INSTANCES"} 11588 ] 11589 }, 11590 "VGT_DMA_REQ_FIFO_DEPTH": { 11591 "fields": [ 11592 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"} 11593 ] 11594 }, 11595 "VGT_DMA_SIZE": { 11596 "fields": [ 11597 {"bits": [0, 31], "name": "NUM_INDICES"} 11598 ] 11599 }, 11600 "VGT_DRAW_INITIATOR": { 11601 "fields": [ 11602 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, 11603 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, 11604 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, 11605 {"bits": [5, 5], "name": "NOT_EOP"}, 11606 {"bits": [6, 6], "name": "USE_OPAQUE"} 11607 ] 11608 }, 11609 "VGT_DRAW_INIT_FIFO_DEPTH": { 11610 "fields": [ 11611 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"} 11612 ] 11613 }, 11614 "VGT_ESGS_RING_ITEMSIZE": { 11615 "fields": [ 11616 {"bits": [0, 14], "name": "ITEMSIZE"} 11617 ] 11618 }, 11619 "VGT_ESGS_RING_SIZE": { 11620 "fields": [ 11621 {"bits": [0, 31], "name": "MEM_SIZE"} 11622 ] 11623 }, 11624 "VGT_ES_PER_GS": { 11625 "fields": [ 11626 {"bits": [0, 10], "name": "ES_PER_GS"} 11627 ] 11628 }, 11629 "VGT_EVENT_ADDRESS_REG": { 11630 "fields": [ 11631 {"bits": [0, 27], "name": "ADDRESS_LOW"} 11632 ] 11633 }, 11634 "VGT_EVENT_INITIATOR": { 11635 "fields": [ 11636 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, 11637 {"bits": [18, 26], "name": "ADDRESS_HI"}, 11638 {"bits": [27, 27], "name": "EXTENDED_EVENT"} 11639 ] 11640 }, 11641 "VGT_FIFO_DEPTHS": { 11642 "fields": [ 11643 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"}, 11644 {"bits": [7, 7], "name": "RESERVED_0"}, 11645 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"}, 11646 {"bits": [22, 31], "name": "RESERVED_1"} 11647 ] 11648 }, 11649 "VGT_GROUP_DECR": { 11650 "fields": [ 11651 {"bits": [0, 3], "name": "DECR"} 11652 ] 11653 }, 11654 "VGT_GROUP_FIRST_DECR": { 11655 "fields": [ 11656 {"bits": [0, 3], "name": "FIRST_DECR"} 11657 ] 11658 }, 11659 "VGT_GROUP_PRIM_TYPE": { 11660 "fields": [ 11661 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, 11662 {"bits": [14, 14], "name": "RETAIN_ORDER"}, 11663 {"bits": [15, 15], "name": "RETAIN_QUADS"}, 11664 {"bits": [16, 18], "name": "PRIM_ORDER"} 11665 ] 11666 }, 11667 "VGT_GROUP_VECT_0_CNTL": { 11668 "fields": [ 11669 {"bits": [0, 0], "name": "COMP_X_EN"}, 11670 {"bits": [1, 1], "name": "COMP_Y_EN"}, 11671 {"bits": [2, 2], "name": "COMP_Z_EN"}, 11672 {"bits": [3, 3], "name": "COMP_W_EN"}, 11673 {"bits": [8, 15], "name": "STRIDE"}, 11674 {"bits": [16, 23], "name": "SHIFT"} 11675 ] 11676 }, 11677 "VGT_GROUP_VECT_0_FMT_CNTL": { 11678 "fields": [ 11679 {"bits": [0, 3], "name": "X_CONV"}, 11680 {"bits": [4, 7], "name": "X_OFFSET"}, 11681 {"bits": [8, 11], "name": "Y_CONV"}, 11682 {"bits": [12, 15], "name": "Y_OFFSET"}, 11683 {"bits": [16, 19], "name": "Z_CONV"}, 11684 {"bits": [20, 23], "name": "Z_OFFSET"}, 11685 {"bits": [24, 27], "name": "W_CONV"}, 11686 {"bits": [28, 31], "name": "W_OFFSET"} 11687 ] 11688 }, 11689 "VGT_GSVS_RING_OFFSET_1": { 11690 "fields": [ 11691 {"bits": [0, 14], "name": "OFFSET"} 11692 ] 11693 }, 11694 "VGT_GS_INSTANCE_CNT": { 11695 "fields": [ 11696 {"bits": [0, 0], "name": "ENABLE"}, 11697 {"bits": [2, 8], "name": "CNT"} 11698 ] 11699 }, 11700 "VGT_GS_MAX_VERT_OUT": { 11701 "fields": [ 11702 {"bits": [0, 10], "name": "MAX_VERT_OUT"} 11703 ] 11704 }, 11705 "VGT_GS_MODE": { 11706 "fields": [ 11707 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, 11708 {"bits": [3, 3], "name": "RESERVED_0"}, 11709 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, 11710 {"bits": [6, 10], "name": "RESERVED_1"}, 11711 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, 11712 {"bits": [12, 12], "name": "RESERVED_2"}, 11713 {"bits": [13, 13], "name": "ES_PASSTHRU"}, 11714 {"bits": [14, 14], "name": "COMPUTE_MODE"}, 11715 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, 11716 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, 11717 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, 11718 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, 11719 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, 11720 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, 11721 {"bits": [21, 22], "name": "ONCHIP"} 11722 ] 11723 }, 11724 "VGT_GS_OUT_PRIM_TYPE": { 11725 "fields": [ 11726 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, 11727 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, 11728 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, 11729 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, 11730 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} 11731 ] 11732 }, 11733 "VGT_GS_PER_ES": { 11734 "fields": [ 11735 {"bits": [0, 10], "name": "GS_PER_ES"} 11736 ] 11737 }, 11738 "VGT_GS_PER_VS": { 11739 "fields": [ 11740 {"bits": [0, 3], "name": "GS_PER_VS"} 11741 ] 11742 }, 11743 "VGT_GS_VERTEX_REUSE": { 11744 "fields": [ 11745 {"bits": [0, 4], "name": "VERT_REUSE"} 11746 ] 11747 }, 11748 "VGT_HOS_CNTL": { 11749 "fields": [ 11750 {"bits": [0, 1], "name": "TESS_MODE"} 11751 ] 11752 }, 11753 "VGT_HOS_MAX_TESS_LEVEL": { 11754 "fields": [ 11755 {"bits": [0, 31], "name": "MAX_TESS"} 11756 ] 11757 }, 11758 "VGT_HOS_MIN_TESS_LEVEL": { 11759 "fields": [ 11760 {"bits": [0, 31], "name": "MIN_TESS"} 11761 ] 11762 }, 11763 "VGT_HOS_REUSE_DEPTH": { 11764 "fields": [ 11765 {"bits": [0, 7], "name": "REUSE_DEPTH"} 11766 ] 11767 }, 11768 "VGT_HS_OFFCHIP_PARAM": { 11769 "fields": [ 11770 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"}, 11771 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"} 11772 ] 11773 }, 11774 "VGT_INDEX_TYPE": { 11775 "fields": [ 11776 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} 11777 ] 11778 }, 11779 "VGT_INDX_OFFSET": { 11780 "fields": [ 11781 {"bits": [0, 31], "name": "INDX_OFFSET"} 11782 ] 11783 }, 11784 "VGT_INSTANCE_STEP_RATE_0": { 11785 "fields": [ 11786 {"bits": [0, 31], "name": "STEP_RATE"} 11787 ] 11788 }, 11789 "VGT_LAST_COPY_STATE": { 11790 "fields": [ 11791 {"bits": [0, 2], "name": "SRC_STATE_ID"}, 11792 {"bits": [16, 18], "name": "DST_STATE_ID"} 11793 ] 11794 }, 11795 "VGT_LS_HS_CONFIG": { 11796 "fields": [ 11797 {"bits": [0, 7], "name": "NUM_PATCHES"}, 11798 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, 11799 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} 11800 ] 11801 }, 11802 "VGT_MAX_VTX_INDX": { 11803 "fields": [ 11804 {"bits": [0, 31], "name": "MAX_INDX"} 11805 ] 11806 }, 11807 "VGT_MC_LAT_CNTL": { 11808 "fields": [ 11809 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"} 11810 ] 11811 }, 11812 "VGT_MIN_VTX_INDX": { 11813 "fields": [ 11814 {"bits": [0, 31], "name": "MIN_INDX"} 11815 ] 11816 }, 11817 "VGT_MULTI_PRIM_IB_RESET_EN": { 11818 "fields": [ 11819 {"bits": [0, 0], "name": "RESET_EN"} 11820 ] 11821 }, 11822 "VGT_MULTI_PRIM_IB_RESET_INDX": { 11823 "fields": [ 11824 {"bits": [0, 31], "name": "RESET_INDX"} 11825 ] 11826 }, 11827 "VGT_OUTPUT_PATH_CNTL": { 11828 "fields": [ 11829 {"bits": [0, 2], "name": "PATH_SELECT"} 11830 ] 11831 }, 11832 "VGT_OUT_DEALLOC_CNTL": { 11833 "fields": [ 11834 {"bits": [0, 6], "name": "DEALLOC_DIST"} 11835 ] 11836 }, 11837 "VGT_PERFCOUNTER_SEID_MASK": { 11838 "fields": [ 11839 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} 11840 ] 11841 }, 11842 "VGT_PRIMITIVEID_EN": { 11843 "fields": [ 11844 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, 11845 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} 11846 ] 11847 }, 11848 "VGT_PRIMITIVEID_RESET": { 11849 "fields": [ 11850 {"bits": [0, 31], "name": "VALUE"} 11851 ] 11852 }, 11853 "VGT_PRIMITIVE_TYPE": { 11854 "fields": [ 11855 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} 11856 ] 11857 }, 11858 "VGT_REUSE_OFF": { 11859 "fields": [ 11860 {"bits": [0, 0], "name": "REUSE_OFF"} 11861 ] 11862 }, 11863 "VGT_SHADER_STAGES_EN": { 11864 "fields": [ 11865 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 11866 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 11867 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 11868 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 11869 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 11870 {"bits": [8, 8], "name": "DYNAMIC_HS"} 11871 ] 11872 }, 11873 "VGT_STRMOUT_BUFFER_CONFIG": { 11874 "fields": [ 11875 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, 11876 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, 11877 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, 11878 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} 11879 ] 11880 }, 11881 "VGT_STRMOUT_CONFIG": { 11882 "fields": [ 11883 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, 11884 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, 11885 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, 11886 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, 11887 {"bits": [4, 6], "name": "RAST_STREAM"}, 11888 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, 11889 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} 11890 ] 11891 }, 11892 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": { 11893 "fields": [ 11894 {"bits": [0, 8], "name": "VERTEX_STRIDE"} 11895 ] 11896 }, 11897 "VGT_STRMOUT_VTX_STRIDE_0": { 11898 "fields": [ 11899 {"bits": [0, 9], "name": "STRIDE"} 11900 ] 11901 }, 11902 "VGT_SYS_CONFIG": { 11903 "fields": [ 11904 {"bits": [0, 0], "name": "DUAL_CORE_EN"}, 11905 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"}, 11906 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"} 11907 ] 11908 }, 11909 "VGT_TF_MEMORY_BASE": { 11910 "fields": [ 11911 {"bits": [0, 31], "name": "BASE"} 11912 ] 11913 }, 11914 "VGT_TF_PARAM": { 11915 "fields": [ 11916 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, 11917 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, 11918 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, 11919 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, 11920 {"bits": [9, 9], "name": "DEPRECATED"}, 11921 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, 11922 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, 11923 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} 11924 ] 11925 }, 11926 "VGT_TF_RING_SIZE": { 11927 "fields": [ 11928 {"bits": [0, 15], "name": "SIZE"} 11929 ] 11930 }, 11931 "VGT_VERTEX_REUSE_BLOCK_CNTL": { 11932 "fields": [ 11933 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} 11934 ] 11935 }, 11936 "VGT_VTX_CNT_EN": { 11937 "fields": [ 11938 {"bits": [0, 0], "name": "VTX_CNT_EN"} 11939 ] 11940 }, 11941 "VGT_VTX_VECT_EJECT_REG": { 11942 "fields": [ 11943 {"bits": [0, 9], "name": "PRIM_COUNT"} 11944 ] 11945 } 11946 } 11947} 11948