1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef PIPE_DEFINES_H 29 #define PIPE_DEFINES_H 30 31 #include "p_compiler.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** 38 * Gallium error codes. 39 * 40 * - A zero value always means success. 41 * - A negative value always means failure. 42 * - The meaning of a positive value is function dependent. 43 */ 44 enum pipe_error 45 { 46 PIPE_OK = 0, 47 PIPE_ERROR = -1, /**< Generic error */ 48 PIPE_ERROR_BAD_INPUT = -2, 49 PIPE_ERROR_OUT_OF_MEMORY = -3, 50 PIPE_ERROR_RETRY = -4 51 /* TODO */ 52 }; 53 54 enum pipe_blendfactor { 55 PIPE_BLENDFACTOR_ONE = 1, 56 PIPE_BLENDFACTOR_SRC_COLOR, 57 PIPE_BLENDFACTOR_SRC_ALPHA, 58 PIPE_BLENDFACTOR_DST_ALPHA, 59 PIPE_BLENDFACTOR_DST_COLOR, 60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE, 61 PIPE_BLENDFACTOR_CONST_COLOR, 62 PIPE_BLENDFACTOR_CONST_ALPHA, 63 PIPE_BLENDFACTOR_SRC1_COLOR, 64 PIPE_BLENDFACTOR_SRC1_ALPHA, 65 66 PIPE_BLENDFACTOR_ZERO = 0x11, 67 PIPE_BLENDFACTOR_INV_SRC_COLOR, 68 PIPE_BLENDFACTOR_INV_SRC_ALPHA, 69 PIPE_BLENDFACTOR_INV_DST_ALPHA, 70 PIPE_BLENDFACTOR_INV_DST_COLOR, 71 72 PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17, 73 PIPE_BLENDFACTOR_INV_CONST_ALPHA, 74 PIPE_BLENDFACTOR_INV_SRC1_COLOR, 75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA, 76 }; 77 78 enum pipe_blend_func { 79 PIPE_BLEND_ADD, 80 PIPE_BLEND_SUBTRACT, 81 PIPE_BLEND_REVERSE_SUBTRACT, 82 PIPE_BLEND_MIN, 83 PIPE_BLEND_MAX, 84 }; 85 86 enum pipe_logicop { 87 PIPE_LOGICOP_CLEAR, 88 PIPE_LOGICOP_NOR, 89 PIPE_LOGICOP_AND_INVERTED, 90 PIPE_LOGICOP_COPY_INVERTED, 91 PIPE_LOGICOP_AND_REVERSE, 92 PIPE_LOGICOP_INVERT, 93 PIPE_LOGICOP_XOR, 94 PIPE_LOGICOP_NAND, 95 PIPE_LOGICOP_AND, 96 PIPE_LOGICOP_EQUIV, 97 PIPE_LOGICOP_NOOP, 98 PIPE_LOGICOP_OR_INVERTED, 99 PIPE_LOGICOP_COPY, 100 PIPE_LOGICOP_OR_REVERSE, 101 PIPE_LOGICOP_OR, 102 PIPE_LOGICOP_SET, 103 }; 104 105 #define PIPE_MASK_R 0x1 106 #define PIPE_MASK_G 0x2 107 #define PIPE_MASK_B 0x4 108 #define PIPE_MASK_A 0x8 109 #define PIPE_MASK_RGBA 0xf 110 #define PIPE_MASK_Z 0x10 111 #define PIPE_MASK_S 0x20 112 #define PIPE_MASK_ZS 0x30 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS) 114 115 116 /** 117 * Inequality functions. Used for depth test, stencil compare, alpha 118 * test, shadow compare, etc. 119 */ 120 enum pipe_compare_func { 121 PIPE_FUNC_NEVER, 122 PIPE_FUNC_LESS, 123 PIPE_FUNC_EQUAL, 124 PIPE_FUNC_LEQUAL, 125 PIPE_FUNC_GREATER, 126 PIPE_FUNC_NOTEQUAL, 127 PIPE_FUNC_GEQUAL, 128 PIPE_FUNC_ALWAYS, 129 }; 130 131 /** Polygon fill mode */ 132 enum { 133 PIPE_POLYGON_MODE_FILL, 134 PIPE_POLYGON_MODE_LINE, 135 PIPE_POLYGON_MODE_POINT, 136 PIPE_POLYGON_MODE_FILL_RECTANGLE, 137 }; 138 139 /** Polygon face specification, eg for culling */ 140 #define PIPE_FACE_NONE 0 141 #define PIPE_FACE_FRONT 1 142 #define PIPE_FACE_BACK 2 143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK) 144 145 /** Stencil ops */ 146 enum pipe_stencil_op { 147 PIPE_STENCIL_OP_KEEP, 148 PIPE_STENCIL_OP_ZERO, 149 PIPE_STENCIL_OP_REPLACE, 150 PIPE_STENCIL_OP_INCR, 151 PIPE_STENCIL_OP_DECR, 152 PIPE_STENCIL_OP_INCR_WRAP, 153 PIPE_STENCIL_OP_DECR_WRAP, 154 PIPE_STENCIL_OP_INVERT, 155 }; 156 157 /** Texture types. 158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D 159 */ 160 enum pipe_texture_target 161 { 162 PIPE_BUFFER, 163 PIPE_TEXTURE_1D, 164 PIPE_TEXTURE_2D, 165 PIPE_TEXTURE_3D, 166 PIPE_TEXTURE_CUBE, 167 PIPE_TEXTURE_RECT, 168 PIPE_TEXTURE_1D_ARRAY, 169 PIPE_TEXTURE_2D_ARRAY, 170 PIPE_TEXTURE_CUBE_ARRAY, 171 PIPE_MAX_TEXTURE_TYPES, 172 }; 173 174 enum pipe_tex_face { 175 PIPE_TEX_FACE_POS_X, 176 PIPE_TEX_FACE_NEG_X, 177 PIPE_TEX_FACE_POS_Y, 178 PIPE_TEX_FACE_NEG_Y, 179 PIPE_TEX_FACE_POS_Z, 180 PIPE_TEX_FACE_NEG_Z, 181 PIPE_TEX_FACE_MAX, 182 }; 183 184 enum pipe_tex_wrap { 185 PIPE_TEX_WRAP_REPEAT, 186 PIPE_TEX_WRAP_CLAMP, 187 PIPE_TEX_WRAP_CLAMP_TO_EDGE, 188 PIPE_TEX_WRAP_CLAMP_TO_BORDER, 189 PIPE_TEX_WRAP_MIRROR_REPEAT, 190 PIPE_TEX_WRAP_MIRROR_CLAMP, 191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE, 192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER, 193 }; 194 195 /** Between mipmaps, ie mipfilter */ 196 enum pipe_tex_mipfilter { 197 PIPE_TEX_MIPFILTER_NEAREST, 198 PIPE_TEX_MIPFILTER_LINEAR, 199 PIPE_TEX_MIPFILTER_NONE, 200 }; 201 202 /** Within a mipmap, ie min/mag filter */ 203 enum pipe_tex_filter { 204 PIPE_TEX_FILTER_NEAREST, 205 PIPE_TEX_FILTER_LINEAR, 206 }; 207 208 enum pipe_tex_compare { 209 PIPE_TEX_COMPARE_NONE, 210 PIPE_TEX_COMPARE_R_TO_TEXTURE, 211 }; 212 213 /** 214 * Clear buffer bits 215 */ 216 #define PIPE_CLEAR_DEPTH (1 << 0) 217 #define PIPE_CLEAR_STENCIL (1 << 1) 218 #define PIPE_CLEAR_COLOR0 (1 << 2) 219 #define PIPE_CLEAR_COLOR1 (1 << 3) 220 #define PIPE_CLEAR_COLOR2 (1 << 4) 221 #define PIPE_CLEAR_COLOR3 (1 << 5) 222 #define PIPE_CLEAR_COLOR4 (1 << 6) 223 #define PIPE_CLEAR_COLOR5 (1 << 7) 224 #define PIPE_CLEAR_COLOR6 (1 << 8) 225 #define PIPE_CLEAR_COLOR7 (1 << 9) 226 /** Combined flags */ 227 /** All color buffers currently bound */ 228 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \ 229 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \ 230 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \ 231 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7) 232 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL) 233 234 /** 235 * CPU access map flags 236 */ 237 enum pipe_map_flags 238 { 239 /** 240 * Resource contents read back (or accessed directly) at transfer 241 * create time. 242 */ 243 PIPE_MAP_READ = (1 << 0), 244 245 /** 246 * Resource contents will be written back at transfer_unmap 247 * time (or modified as a result of being accessed directly). 248 */ 249 PIPE_MAP_WRITE = (1 << 1), 250 251 /** 252 * Read/modify/write 253 */ 254 PIPE_MAP_READ_WRITE = PIPE_MAP_READ | PIPE_MAP_WRITE, 255 256 /** 257 * The transfer should map the texture storage directly. The driver may 258 * return NULL if that isn't possible, and the gallium frontend needs to cope 259 * with that and use an alternative path without this flag. 260 * 261 * E.g. the gallium frontend could have a simpler path which maps textures and 262 * does read/modify/write cycles on them directly, and a more complicated 263 * path which uses minimal read and write transfers. 264 * 265 * This flag supresses implicit "DISCARD" for buffer_subdata. 266 */ 267 PIPE_MAP_DIRECTLY = (1 << 2), 268 269 /** 270 * Discards the memory within the mapped region. 271 * 272 * It should not be used with PIPE_MAP_READ. 273 * 274 * See also: 275 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag. 276 */ 277 PIPE_MAP_DISCARD_RANGE = (1 << 8), 278 279 /** 280 * Fail if the resource cannot be mapped immediately. 281 * 282 * See also: 283 * - Direct3D's D3DLOCK_DONOTWAIT flag. 284 * - Mesa's MESA_MAP_NOWAIT_BIT flag. 285 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag. 286 */ 287 PIPE_MAP_DONTBLOCK = (1 << 9), 288 289 /** 290 * Do not attempt to synchronize pending operations on the resource when mapping. 291 * 292 * It should not be used with PIPE_MAP_READ. 293 * 294 * See also: 295 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag. 296 * - Direct3D's D3DLOCK_NOOVERWRITE flag. 297 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag. 298 */ 299 PIPE_MAP_UNSYNCHRONIZED = (1 << 10), 300 301 /** 302 * Written ranges will be notified later with 303 * pipe_context::transfer_flush_region. 304 * 305 * It should not be used with PIPE_MAP_READ. 306 * 307 * See also: 308 * - pipe_context::transfer_flush_region 309 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag. 310 */ 311 PIPE_MAP_FLUSH_EXPLICIT = (1 << 11), 312 313 /** 314 * Discards all memory backing the resource. 315 * 316 * It should not be used with PIPE_MAP_READ. 317 * 318 * This is equivalent to: 319 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT 320 * - BufferData(NULL) on a GL buffer 321 * - Direct3D's D3DLOCK_DISCARD flag. 322 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag. 323 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag 324 * - D3D10's D3D10_MAP_WRITE_DISCARD flag. 325 */ 326 PIPE_MAP_DISCARD_WHOLE_RESOURCE = (1 << 12), 327 328 /** 329 * Allows the resource to be used for rendering while mapped. 330 * 331 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating 332 * the resource. 333 * 334 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER) 335 * must be called to ensure the device can see what the CPU has written. 336 */ 337 PIPE_MAP_PERSISTENT = (1 << 13), 338 339 /** 340 * If PERSISTENT is set, this ensures any writes done by the device are 341 * immediately visible to the CPU and vice versa. 342 * 343 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating 344 * the resource. 345 */ 346 PIPE_MAP_COHERENT = (1 << 14), 347 348 /** 349 * Map a resource in a thread-safe manner, because the calling thread can 350 * be any thread. It can only be used if both WRITE and UNSYNCHRONIZED are 351 * set. 352 */ 353 PIPE_MAP_THREAD_SAFE = 1 << 15, 354 355 /** 356 * Map only the depth aspect of a resource 357 */ 358 PIPE_MAP_DEPTH_ONLY = 1 << 16, 359 360 /** 361 * Map only the stencil aspect of a resource 362 */ 363 PIPE_MAP_STENCIL_ONLY = 1 << 17, 364 365 /** 366 * This and higher bits are reserved for private use by drivers. Drivers 367 * should use this as (PIPE_MAP_DRV_PRV << i). 368 */ 369 PIPE_MAP_DRV_PRV = (1 << 24) 370 }; 371 372 /** 373 * Flags for the flush function. 374 */ 375 enum pipe_flush_flags 376 { 377 PIPE_FLUSH_END_OF_FRAME = (1 << 0), 378 PIPE_FLUSH_DEFERRED = (1 << 1), 379 PIPE_FLUSH_FENCE_FD = (1 << 2), 380 PIPE_FLUSH_ASYNC = (1 << 3), 381 PIPE_FLUSH_HINT_FINISH = (1 << 4), 382 PIPE_FLUSH_TOP_OF_PIPE = (1 << 5), 383 PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6), 384 }; 385 386 /** 387 * Flags for pipe_context::dump_debug_state. 388 */ 389 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0) 390 391 /** 392 * Create a compute-only context. Use in pipe_screen::context_create. 393 * This disables draw, blit, and clear*, render_condition, and other graphics 394 * functions. Interop with other graphics contexts is still allowed. 395 * This allows scheduling jobs on a compute-only hardware command queue that 396 * can run in parallel with graphics without stalling it. 397 */ 398 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0) 399 400 /** 401 * Gather debug information and expect that pipe_context::dump_debug_state 402 * will be called. Use in pipe_screen::context_create. 403 */ 404 #define PIPE_CONTEXT_DEBUG (1 << 1) 405 406 /** 407 * Whether out-of-bounds shader loads must return zero and out-of-bounds 408 * shader stores must be dropped. 409 */ 410 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2) 411 412 /** 413 * Prefer threaded pipe_context. It also implies that video codec functions 414 * will not be used. (they will be either no-ops or NULL when threading is 415 * enabled) 416 */ 417 #define PIPE_CONTEXT_PREFER_THREADED (1 << 3) 418 419 /** 420 * Create a high priority context. 421 */ 422 #define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4) 423 424 /** 425 * Create a low priority context. 426 */ 427 #define PIPE_CONTEXT_LOW_PRIORITY (1 << 5) 428 429 /** Stop execution if the device is reset. */ 430 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6) 431 432 /** 433 * Flags for pipe_context::memory_barrier. 434 */ 435 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0) 436 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1) 437 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2) 438 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3) 439 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4) 440 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5) 441 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6) 442 #define PIPE_BARRIER_TEXTURE (1 << 7) 443 #define PIPE_BARRIER_IMAGE (1 << 8) 444 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9) 445 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10) 446 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11) 447 #define PIPE_BARRIER_UPDATE_BUFFER (1 << 12) 448 #define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13) 449 #define PIPE_BARRIER_ALL ((1 << 14) - 1) 450 451 #define PIPE_BARRIER_UPDATE \ 452 (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE) 453 454 /** 455 * Flags for pipe_context::texture_barrier. 456 */ 457 #define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0) 458 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1) 459 460 /** 461 * Resource binding flags -- gallium frontends must specify in advance all 462 * the ways a resource might be used. 463 */ 464 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */ 465 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */ 466 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */ 467 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */ 468 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */ 469 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */ 470 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */ 471 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */ 472 /* gap */ 473 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */ 474 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */ 475 #define PIPE_BIND_CUSTOM (1 << 12) /* gallium frontend/winsys usages */ 476 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */ 477 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */ 478 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */ 479 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */ 480 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */ 481 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */ 482 483 /** 484 * The first two flags above were previously part of the amorphous 485 * TEXTURE_USAGE, most of which are now descriptions of the ways a 486 * particular texture can be bound to the gallium pipeline. The two flags 487 * below do not fit within that and probably need to be migrated to some 488 * other place. 489 * 490 * Scanout is used to ask for a texture suitable for actual scanout (hence 491 * the name), which implies extra layout constraints on some hardware. 492 * It may also have some special meaning regarding mouse cursor images. 493 * 494 * The shared flag is quite underspecified, but certainly isn't a 495 * binding flag - it seems more like a message to the winsys to create 496 * a shareable allocation. 497 * 498 * The third flag has been added to be able to force textures to be created 499 * in linear mode (no tiling). 500 */ 501 #define PIPE_BIND_SCANOUT (1 << 19) /* */ 502 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */ 503 #define PIPE_BIND_LINEAR (1 << 21) 504 #define PIPE_BIND_PROTECTED (1 << 22) /* Resource will be protected/encrypted */ 505 506 507 /** 508 * Flags for the driver about resource behaviour: 509 */ 510 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0) 511 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1) 512 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2) 513 #define PIPE_RESOURCE_FLAG_SPARSE (1 << 3) 514 #define PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE (1 << 4) 515 #define PIPE_RESOURCE_FLAG_ENCRYPTED (1 << 5) 516 #define PIPE_RESOURCE_FLAG_DONT_OVER_ALLOCATE (1 << 6) 517 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 8) /* driver/winsys private */ 518 #define PIPE_RESOURCE_FLAG_FRONTEND_PRIV (1 << 24) /* gallium frontend private */ 519 520 /** 521 * Hint about the expected lifecycle of a resource. 522 * Sorted according to GPU vs CPU access. 523 */ 524 enum pipe_resource_usage { 525 PIPE_USAGE_DEFAULT, /* fast GPU access */ 526 PIPE_USAGE_IMMUTABLE, /* fast GPU access, immutable */ 527 PIPE_USAGE_DYNAMIC, /* uploaded data is used multiple times */ 528 PIPE_USAGE_STREAM, /* uploaded data is used once */ 529 PIPE_USAGE_STAGING, /* fast CPU access */ 530 }; 531 532 /** 533 * Shaders 534 */ 535 enum pipe_shader_type { 536 PIPE_SHADER_VERTEX, 537 PIPE_SHADER_FRAGMENT, 538 PIPE_SHADER_GEOMETRY, 539 PIPE_SHADER_TESS_CTRL, 540 PIPE_SHADER_TESS_EVAL, 541 PIPE_SHADER_COMPUTE, 542 PIPE_SHADER_TYPES, 543 }; 544 545 /** 546 * Primitive types: 547 */ 548 enum pipe_prim_type { 549 PIPE_PRIM_POINTS, 550 PIPE_PRIM_LINES, 551 PIPE_PRIM_LINE_LOOP, 552 PIPE_PRIM_LINE_STRIP, 553 PIPE_PRIM_TRIANGLES, 554 PIPE_PRIM_TRIANGLE_STRIP, 555 PIPE_PRIM_TRIANGLE_FAN, 556 PIPE_PRIM_QUADS, 557 PIPE_PRIM_QUAD_STRIP, 558 PIPE_PRIM_POLYGON, 559 PIPE_PRIM_LINES_ADJACENCY, 560 PIPE_PRIM_LINE_STRIP_ADJACENCY, 561 PIPE_PRIM_TRIANGLES_ADJACENCY, 562 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY, 563 PIPE_PRIM_PATCHES, 564 PIPE_PRIM_MAX, 565 }; 566 567 /** 568 * Tessellator spacing types 569 */ 570 enum pipe_tess_spacing { 571 PIPE_TESS_SPACING_FRACTIONAL_ODD, 572 PIPE_TESS_SPACING_FRACTIONAL_EVEN, 573 PIPE_TESS_SPACING_EQUAL, 574 }; 575 576 /** 577 * Query object types 578 */ 579 enum pipe_query_type { 580 PIPE_QUERY_OCCLUSION_COUNTER, 581 PIPE_QUERY_OCCLUSION_PREDICATE, 582 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE, 583 PIPE_QUERY_TIMESTAMP, 584 PIPE_QUERY_TIMESTAMP_DISJOINT, 585 PIPE_QUERY_TIME_ELAPSED, 586 PIPE_QUERY_PRIMITIVES_GENERATED, 587 PIPE_QUERY_PRIMITIVES_EMITTED, 588 PIPE_QUERY_SO_STATISTICS, 589 PIPE_QUERY_SO_OVERFLOW_PREDICATE, 590 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE, 591 PIPE_QUERY_GPU_FINISHED, 592 PIPE_QUERY_PIPELINE_STATISTICS, 593 PIPE_QUERY_PIPELINE_STATISTICS_SINGLE, 594 PIPE_QUERY_TYPES, 595 /* start of driver queries, see pipe_screen::get_driver_query_info */ 596 PIPE_QUERY_DRIVER_SPECIFIC = 256, 597 }; 598 599 /** 600 * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries. 601 */ 602 enum pipe_statistics_query_index { 603 PIPE_STAT_QUERY_IA_VERTICES, 604 PIPE_STAT_QUERY_IA_PRIMITIVES, 605 PIPE_STAT_QUERY_VS_INVOCATIONS, 606 PIPE_STAT_QUERY_GS_INVOCATIONS, 607 PIPE_STAT_QUERY_GS_PRIMITIVES, 608 PIPE_STAT_QUERY_C_INVOCATIONS, 609 PIPE_STAT_QUERY_C_PRIMITIVES, 610 PIPE_STAT_QUERY_PS_INVOCATIONS, 611 PIPE_STAT_QUERY_HS_INVOCATIONS, 612 PIPE_STAT_QUERY_DS_INVOCATIONS, 613 PIPE_STAT_QUERY_CS_INVOCATIONS, 614 }; 615 616 /** 617 * Conditional rendering modes 618 */ 619 enum pipe_render_cond_flag { 620 PIPE_RENDER_COND_WAIT, 621 PIPE_RENDER_COND_NO_WAIT, 622 PIPE_RENDER_COND_BY_REGION_WAIT, 623 PIPE_RENDER_COND_BY_REGION_NO_WAIT, 624 }; 625 626 /** 627 * Point sprite coord modes 628 */ 629 enum pipe_sprite_coord_mode { 630 PIPE_SPRITE_COORD_UPPER_LEFT, 631 PIPE_SPRITE_COORD_LOWER_LEFT, 632 }; 633 634 /** 635 * Texture & format swizzles 636 */ 637 enum pipe_swizzle { 638 PIPE_SWIZZLE_X, 639 PIPE_SWIZZLE_Y, 640 PIPE_SWIZZLE_Z, 641 PIPE_SWIZZLE_W, 642 PIPE_SWIZZLE_0, 643 PIPE_SWIZZLE_1, 644 PIPE_SWIZZLE_NONE, 645 PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */ 646 }; 647 648 /** 649 * Viewport swizzles 650 */ 651 enum pipe_viewport_swizzle { 652 PIPE_VIEWPORT_SWIZZLE_POSITIVE_X, 653 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_X, 654 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Y, 655 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Y, 656 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Z, 657 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Z, 658 PIPE_VIEWPORT_SWIZZLE_POSITIVE_W, 659 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_W, 660 }; 661 662 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull 663 664 665 /** 666 * Device reset status. 667 */ 668 enum pipe_reset_status 669 { 670 PIPE_NO_RESET, 671 PIPE_GUILTY_CONTEXT_RESET, 672 PIPE_INNOCENT_CONTEXT_RESET, 673 PIPE_UNKNOWN_CONTEXT_RESET, 674 }; 675 676 677 /** 678 * Conservative rasterization modes. 679 */ 680 enum pipe_conservative_raster_mode 681 { 682 PIPE_CONSERVATIVE_RASTER_OFF, 683 684 /** 685 * The post-snap mode means the conservative rasterization occurs after 686 * the conversion from floating-point to fixed-point coordinates 687 * on the subpixel grid. 688 */ 689 PIPE_CONSERVATIVE_RASTER_POST_SNAP, 690 691 /** 692 * The pre-snap mode means the conservative rasterization occurs before 693 * the conversion from floating-point to fixed-point coordinates. 694 */ 695 PIPE_CONSERVATIVE_RASTER_PRE_SNAP, 696 }; 697 698 699 /** 700 * resource_get_handle flags. 701 */ 702 /* Requires pipe_context::flush_resource before external use. */ 703 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0) 704 /* Expected external use of the resource: */ 705 #define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1) 706 #define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2) 707 708 /** 709 * pipe_image_view access flags. 710 */ 711 #define PIPE_IMAGE_ACCESS_READ (1 << 0) 712 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1) 713 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \ 714 PIPE_IMAGE_ACCESS_WRITE) 715 716 /** 717 * Implementation capabilities/limits which are queried through 718 * pipe_screen::get_param() 719 */ 720 enum pipe_cap 721 { 722 PIPE_CAP_GRAPHICS, 723 PIPE_CAP_NPOT_TEXTURES, 724 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS, 725 PIPE_CAP_ANISOTROPIC_FILTER, 726 PIPE_CAP_POINT_SPRITE, 727 PIPE_CAP_MAX_RENDER_TARGETS, 728 PIPE_CAP_OCCLUSION_QUERY, 729 PIPE_CAP_QUERY_TIME_ELAPSED, 730 PIPE_CAP_TEXTURE_SHADOW_MAP, 731 PIPE_CAP_TEXTURE_SWIZZLE, 732 PIPE_CAP_MAX_TEXTURE_2D_SIZE, 733 PIPE_CAP_MAX_TEXTURE_3D_LEVELS, 734 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS, 735 PIPE_CAP_TEXTURE_MIRROR_CLAMP, 736 PIPE_CAP_BLEND_EQUATION_SEPARATE, 737 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS, 738 PIPE_CAP_PRIMITIVE_RESTART, 739 /** subset of PRIMITIVE_RESTART where the restart index is always the fixed 740 * maximum value for the index type 741 */ 742 PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX, 743 /** blend enables and write masks per rendertarget */ 744 PIPE_CAP_INDEP_BLEND_ENABLE, 745 /** different blend funcs per rendertarget */ 746 PIPE_CAP_INDEP_BLEND_FUNC, 747 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS, 748 PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 749 PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 750 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 751 PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 752 PIPE_CAP_DEPTH_CLIP_DISABLE, 753 PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE, 754 PIPE_CAP_SHADER_STENCIL_EXPORT, 755 PIPE_CAP_TGSI_INSTANCEID, 756 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR, 757 PIPE_CAP_FRAGMENT_COLOR_CLAMPED, 758 PIPE_CAP_MIXED_COLORBUFFER_FORMATS, 759 PIPE_CAP_SEAMLESS_CUBE_MAP, 760 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE, 761 PIPE_CAP_MIN_TEXEL_OFFSET, 762 PIPE_CAP_MAX_TEXEL_OFFSET, 763 PIPE_CAP_CONDITIONAL_RENDER, 764 PIPE_CAP_TEXTURE_BARRIER, 765 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS, 766 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS, 767 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME, 768 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS, 769 PIPE_CAP_VERTEX_COLOR_UNCLAMPED, 770 PIPE_CAP_VERTEX_COLOR_CLAMPED, 771 PIPE_CAP_GLSL_FEATURE_LEVEL, 772 PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY, 773 PIPE_CAP_ESSL_FEATURE_LEVEL, 774 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION, 775 PIPE_CAP_USER_VERTEX_BUFFERS, 776 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY, 777 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY, 778 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY, 779 PIPE_CAP_COMPUTE, 780 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT, 781 PIPE_CAP_START_INSTANCE, 782 PIPE_CAP_QUERY_TIMESTAMP, 783 PIPE_CAP_TEXTURE_MULTISAMPLE, 784 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, 785 PIPE_CAP_CUBE_MAP_ARRAY, 786 PIPE_CAP_TEXTURE_BUFFER_OBJECTS, 787 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT, 788 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY, 789 PIPE_CAP_TGSI_TEXCOORD, 790 PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER, 791 PIPE_CAP_QUERY_PIPELINE_STATISTICS, 792 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK, 793 PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE, 794 PIPE_CAP_MAX_VIEWPORTS, 795 PIPE_CAP_ENDIANNESS, 796 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES, 797 PIPE_CAP_TGSI_VS_LAYER_VIEWPORT, 798 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES, 799 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS, 800 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS, 801 PIPE_CAP_TEXTURE_GATHER_SM5, 802 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT, 803 PIPE_CAP_FAKE_SW_MSAA, 804 PIPE_CAP_TEXTURE_QUERY_LOD, 805 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET, 806 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET, 807 PIPE_CAP_SAMPLE_SHADING, 808 PIPE_CAP_TEXTURE_GATHER_OFFSETS, 809 PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION, 810 PIPE_CAP_MAX_VERTEX_STREAMS, 811 PIPE_CAP_DRAW_INDIRECT, 812 PIPE_CAP_TGSI_FS_FINE_DERIVATIVE, 813 PIPE_CAP_VENDOR_ID, 814 PIPE_CAP_DEVICE_ID, 815 PIPE_CAP_ACCELERATED, 816 PIPE_CAP_VIDEO_MEMORY, 817 PIPE_CAP_UMA, 818 PIPE_CAP_CONDITIONAL_RENDER_INVERTED, 819 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE, 820 PIPE_CAP_SAMPLER_VIEW_TARGET, 821 PIPE_CAP_CLIP_HALFZ, 822 PIPE_CAP_VERTEXID_NOBASE, 823 PIPE_CAP_POLYGON_OFFSET_CLAMP, 824 PIPE_CAP_MULTISAMPLE_Z_RESOLVE, 825 PIPE_CAP_RESOURCE_FROM_USER_MEMORY, 826 PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY, 827 PIPE_CAP_DEVICE_RESET_STATUS_QUERY, 828 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS, 829 PIPE_CAP_TEXTURE_FLOAT_LINEAR, 830 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR, 831 PIPE_CAP_DEPTH_BOUNDS_TEST, 832 PIPE_CAP_TGSI_TXQS, 833 PIPE_CAP_FORCE_PERSAMPLE_INTERP, 834 PIPE_CAP_SHAREABLE_SHADERS, 835 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS, 836 PIPE_CAP_CLEAR_TEXTURE, 837 PIPE_CAP_CLEAR_SCISSORED, 838 PIPE_CAP_DRAW_PARAMETERS, 839 PIPE_CAP_TGSI_PACK_HALF_FLOAT, 840 PIPE_CAP_MULTI_DRAW_INDIRECT, 841 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS, 842 PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL, 843 PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL, 844 PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL, 845 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT, 846 PIPE_CAP_INVALIDATE_BUFFER, 847 PIPE_CAP_GENERATE_MIPMAP, 848 PIPE_CAP_STRING_MARKER, 849 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS, 850 PIPE_CAP_QUERY_BUFFER_OBJECT, 851 PIPE_CAP_QUERY_MEMORY_INFO, 852 PIPE_CAP_PCI_GROUP, 853 PIPE_CAP_PCI_BUS, 854 PIPE_CAP_PCI_DEVICE, 855 PIPE_CAP_PCI_FUNCTION, 856 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT, 857 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR, 858 PIPE_CAP_CULL_DISTANCE, 859 PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES, 860 PIPE_CAP_TGSI_VOTE, 861 PIPE_CAP_MAX_WINDOW_RECTANGLES, 862 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED, 863 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS, 864 PIPE_CAP_RASTERIZER_SUBPIXEL_BITS, 865 PIPE_CAP_MIXED_COLOR_DEPTH_BITS, 866 PIPE_CAP_TGSI_ARRAY_COMPONENTS, 867 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS, 868 PIPE_CAP_TGSI_CAN_READ_OUTPUTS, 869 PIPE_CAP_NATIVE_FENCE_FD, 870 PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY, 871 PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS, 872 PIPE_CAP_FBFETCH, 873 PIPE_CAP_TGSI_MUL_ZERO_WINS, 874 PIPE_CAP_DOUBLES, 875 PIPE_CAP_INT64, 876 PIPE_CAP_INT64_DIVMOD, 877 PIPE_CAP_TGSI_TEX_TXF_LZ, 878 PIPE_CAP_TGSI_CLOCK, 879 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE, 880 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE, 881 PIPE_CAP_TGSI_BALLOT, 882 PIPE_CAP_TGSI_TES_LAYER_VIEWPORT, 883 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX, 884 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION, 885 PIPE_CAP_POST_DEPTH_COVERAGE, 886 PIPE_CAP_BINDLESS_TEXTURE, 887 PIPE_CAP_NIR_SAMPLERS_AS_DEREF, 888 PIPE_CAP_QUERY_SO_OVERFLOW, 889 PIPE_CAP_MEMOBJ, 890 PIPE_CAP_LOAD_CONSTBUF, 891 PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS, 892 PIPE_CAP_TILE_RASTER_ORDER, 893 PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES, 894 PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS, 895 PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET, 896 PIPE_CAP_CONTEXT_PRIORITY_MASK, 897 PIPE_CAP_FENCE_SIGNAL, 898 PIPE_CAP_CONSTBUF0_FLAGS, 899 PIPE_CAP_PACKED_UNIFORMS, 900 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES, 901 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES, 902 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES, 903 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES, 904 PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS, 905 PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE, 906 PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE, 907 PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS, 908 PIPE_CAP_MAX_GS_INVOCATIONS, 909 PIPE_CAP_MAX_SHADER_BUFFER_SIZE, 910 PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE, 911 PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS, 912 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS, 913 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS, 914 PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET, 915 PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET, 916 PIPE_CAP_SURFACE_SAMPLE_COUNT, 917 PIPE_CAP_TGSI_ATOMFADD, 918 PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE, 919 PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND, 920 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL, 921 PIPE_CAP_NIR_COMPACT_ARRAYS, 922 PIPE_CAP_MAX_VARYINGS, 923 PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK, 924 PIPE_CAP_COMPUTE_SHADER_DERIVATIVES, 925 PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS, 926 PIPE_CAP_IMAGE_LOAD_FORMATTED, 927 PIPE_CAP_THROTTLE, 928 PIPE_CAP_DMABUF, 929 PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA, 930 PIPE_CAP_FRAGMENT_SHADER_INTERLOCK, 931 PIPE_CAP_FBFETCH_COHERENT, 932 PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED, 933 PIPE_CAP_ATOMIC_FLOAT_MINMAX, 934 PIPE_CAP_TGSI_DIV, 935 PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, 936 PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES, 937 PIPE_CAP_VERTEX_SHADER_SATURATE, 938 PIPE_CAP_TEXTURE_SHADOW_LOD, 939 PIPE_CAP_SHADER_SAMPLES_IDENTICAL, 940 PIPE_CAP_TGSI_ATOMINC_WRAP, 941 PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF, 942 PIPE_CAP_GL_SPIRV, 943 PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS, 944 PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION, 945 PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE, 946 PIPE_CAP_FLATSHADE, 947 PIPE_CAP_ALPHA_TEST, 948 PIPE_CAP_POINT_SIZE_FIXED, 949 PIPE_CAP_TWO_SIDED_COLOR, 950 PIPE_CAP_CLIP_PLANES, 951 PIPE_CAP_MAX_VERTEX_BUFFERS, 952 PIPE_CAP_OPENCL_INTEGER_FUNCTIONS, 953 PIPE_CAP_INTEGER_MULTIPLY_32X16, 954 /* Turn draw, dispatch, blit into NOOP */ 955 PIPE_CAP_FRONTEND_NOOP, 956 PIPE_CAP_NIR_IMAGES_AS_DEREF, 957 PIPE_CAP_PACKED_STREAM_OUTPUT, 958 PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED, 959 PIPE_CAP_PSIZ_CLAMPED, 960 PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES, 961 PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE, 962 PIPE_CAP_VIEWPORT_SWIZZLE, 963 PIPE_CAP_SYSTEM_SVM, 964 PIPE_CAP_VIEWPORT_MASK, 965 PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL, 966 PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE, 967 PIPE_CAP_GLSL_ZERO_INIT, 968 PIPE_CAP_BLEND_EQUATION_ADVANCED, 969 PIPE_CAP_NIR_ATOMICS_AS_DEREF, 970 PIPE_CAP_NO_CLIP_ON_COPY_TEX, 971 PIPE_CAP_MAX_TEXTURE_MB, 972 PIPE_CAP_SHADER_ATOMIC_INT64, 973 PIPE_CAP_DEVICE_PROTECTED_CONTENT, 974 }; 975 976 /** 977 * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should 978 * return a bitmask of the supported priorities. If the driver does not 979 * support prioritized contexts, it can return 0. 980 * 981 * Note that these match __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_* 982 */ 983 #define PIPE_CONTEXT_PRIORITY_LOW (1 << 0) 984 #define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1) 985 #define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2) 986 987 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0) 988 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1) 989 990 enum pipe_endian 991 { 992 PIPE_ENDIAN_LITTLE = 0, 993 PIPE_ENDIAN_BIG = 1, 994 #if UTIL_ARCH_LITTLE_ENDIAN 995 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE 996 #elif UTIL_ARCH_BIG_ENDIAN 997 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG 998 #endif 999 }; 1000 1001 /** 1002 * Implementation limits which are queried through 1003 * pipe_screen::get_paramf() 1004 */ 1005 enum pipe_capf 1006 { 1007 PIPE_CAPF_MAX_LINE_WIDTH, 1008 PIPE_CAPF_MAX_LINE_WIDTH_AA, 1009 PIPE_CAPF_MAX_POINT_WIDTH, 1010 PIPE_CAPF_MAX_POINT_WIDTH_AA, 1011 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY, 1012 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS, 1013 PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE, 1014 PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE, 1015 PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY, 1016 }; 1017 1018 /** Shader caps not specific to any single stage */ 1019 enum pipe_shader_cap 1020 { 1021 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */ 1022 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS, 1023 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS, 1024 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS, 1025 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH, 1026 PIPE_SHADER_CAP_MAX_INPUTS, 1027 PIPE_SHADER_CAP_MAX_OUTPUTS, 1028 PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE, 1029 PIPE_SHADER_CAP_MAX_CONST_BUFFERS, 1030 PIPE_SHADER_CAP_MAX_TEMPS, 1031 /* boolean caps */ 1032 PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED, 1033 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR, 1034 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR, 1035 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR, 1036 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR, 1037 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */ 1038 PIPE_SHADER_CAP_INTEGERS, 1039 PIPE_SHADER_CAP_INT64_ATOMICS, 1040 PIPE_SHADER_CAP_FP16, 1041 PIPE_SHADER_CAP_FP16_DERIVATIVES, 1042 PIPE_SHADER_CAP_INT16, 1043 PIPE_SHADER_CAP_GLSL_16BIT_CONSTS, 1044 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS, 1045 PIPE_SHADER_CAP_PREFERRED_IR, 1046 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, 1047 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, 1048 PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED, /* all rounding modes */ 1049 PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED, 1050 PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED, 1051 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, 1052 PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT, 1053 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, 1054 PIPE_SHADER_CAP_SUPPORTED_IRS, 1055 PIPE_SHADER_CAP_MAX_SHADER_IMAGES, 1056 PIPE_SHADER_CAP_LOWER_IF_THRESHOLD, 1057 PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS, 1058 PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED, 1059 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS, 1060 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS, 1061 }; 1062 1063 /** 1064 * Shader intermediate representation. 1065 * 1066 * Note that if the driver requests something other than TGSI, it must 1067 * always be prepared to receive TGSI in addition to its preferred IR. 1068 * If the driver requests TGSI as its preferred IR, it will *always* 1069 * get TGSI. 1070 * 1071 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with 1072 * gallium frontends that only understand TGSI. 1073 */ 1074 enum pipe_shader_ir 1075 { 1076 PIPE_SHADER_IR_TGSI = 0, 1077 PIPE_SHADER_IR_NATIVE, 1078 PIPE_SHADER_IR_NIR, 1079 PIPE_SHADER_IR_NIR_SERIALIZED, 1080 }; 1081 1082 /** 1083 * Compute-specific implementation capability. They can be queried 1084 * using pipe_screen::get_compute_param. 1085 */ 1086 enum pipe_compute_cap 1087 { 1088 PIPE_COMPUTE_CAP_ADDRESS_BITS, 1089 PIPE_COMPUTE_CAP_IR_TARGET, 1090 PIPE_COMPUTE_CAP_GRID_DIMENSION, 1091 PIPE_COMPUTE_CAP_MAX_GRID_SIZE, 1092 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE, 1093 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, 1094 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, 1095 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE, 1096 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE, 1097 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE, 1098 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 1099 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY, 1100 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS, 1101 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED, 1102 PIPE_COMPUTE_CAP_SUBGROUP_SIZE, 1103 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK, 1104 }; 1105 1106 /** 1107 * Resource parameters. They can be queried using 1108 * pipe_screen::get_resource_param. 1109 */ 1110 enum pipe_resource_param 1111 { 1112 PIPE_RESOURCE_PARAM_NPLANES, 1113 PIPE_RESOURCE_PARAM_STRIDE, 1114 PIPE_RESOURCE_PARAM_OFFSET, 1115 PIPE_RESOURCE_PARAM_MODIFIER, 1116 PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED, 1117 PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS, 1118 PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD, 1119 PIPE_RESOURCE_PARAM_LAYER_STRIDE, 1120 }; 1121 1122 /** 1123 * Types of parameters for pipe_context::set_context_param. 1124 */ 1125 enum pipe_context_param 1126 { 1127 /* A hint for the driver that it should pin its execution threads to 1128 * a group of cores sharing a specific L3 cache if the CPU has multiple 1129 * L3 caches. This is needed for good multithreading performance on 1130 * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have 1131 * any internal threads or don't run on affected CPUs can ignore this. 1132 */ 1133 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE, 1134 }; 1135 1136 /** 1137 * Composite query types 1138 */ 1139 1140 /** 1141 * Query result for PIPE_QUERY_SO_STATISTICS. 1142 */ 1143 struct pipe_query_data_so_statistics 1144 { 1145 uint64_t num_primitives_written; 1146 uint64_t primitives_storage_needed; 1147 }; 1148 1149 /** 1150 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT. 1151 */ 1152 struct pipe_query_data_timestamp_disjoint 1153 { 1154 uint64_t frequency; 1155 bool disjoint; 1156 }; 1157 1158 /** 1159 * Query result for PIPE_QUERY_PIPELINE_STATISTICS. 1160 */ 1161 struct pipe_query_data_pipeline_statistics 1162 { 1163 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */ 1164 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */ 1165 uint64_t vs_invocations; /**< Num vertex shader invocations. */ 1166 uint64_t gs_invocations; /**< Num geometry shader invocations. */ 1167 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */ 1168 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */ 1169 uint64_t c_primitives; /**< Num primitives that were rendered. */ 1170 uint64_t ps_invocations; /**< Num pixel shader invocations. */ 1171 uint64_t hs_invocations; /**< Num hull shader invocations. */ 1172 uint64_t ds_invocations; /**< Num domain shader invocations. */ 1173 uint64_t cs_invocations; /**< Num compute shader invocations. */ 1174 }; 1175 1176 /** 1177 * For batch queries. 1178 */ 1179 union pipe_numeric_type_union 1180 { 1181 uint64_t u64; 1182 uint32_t u32; 1183 float f; 1184 }; 1185 1186 /** 1187 * Query result (returned by pipe_context::get_query_result). 1188 */ 1189 union pipe_query_result 1190 { 1191 /* PIPE_QUERY_OCCLUSION_PREDICATE */ 1192 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */ 1193 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */ 1194 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */ 1195 /* PIPE_QUERY_GPU_FINISHED */ 1196 bool b; 1197 1198 /* PIPE_QUERY_OCCLUSION_COUNTER */ 1199 /* PIPE_QUERY_TIMESTAMP */ 1200 /* PIPE_QUERY_TIME_ELAPSED */ 1201 /* PIPE_QUERY_PRIMITIVES_GENERATED */ 1202 /* PIPE_QUERY_PRIMITIVES_EMITTED */ 1203 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */ 1204 /* PIPE_DRIVER_QUERY_TYPE_BYTES */ 1205 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */ 1206 /* PIPE_DRIVER_QUERY_TYPE_HZ */ 1207 uint64_t u64; 1208 1209 /* PIPE_DRIVER_QUERY_TYPE_UINT */ 1210 uint32_t u32; 1211 1212 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */ 1213 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */ 1214 float f; 1215 1216 /* PIPE_QUERY_SO_STATISTICS */ 1217 struct pipe_query_data_so_statistics so_statistics; 1218 1219 /* PIPE_QUERY_TIMESTAMP_DISJOINT */ 1220 struct pipe_query_data_timestamp_disjoint timestamp_disjoint; 1221 1222 /* PIPE_QUERY_PIPELINE_STATISTICS */ 1223 struct pipe_query_data_pipeline_statistics pipeline_statistics; 1224 1225 /* batch queries (variable length) */ 1226 union pipe_numeric_type_union batch[1]; 1227 }; 1228 1229 enum pipe_query_value_type 1230 { 1231 PIPE_QUERY_TYPE_I32, 1232 PIPE_QUERY_TYPE_U32, 1233 PIPE_QUERY_TYPE_I64, 1234 PIPE_QUERY_TYPE_U64, 1235 }; 1236 1237 union pipe_color_union 1238 { 1239 float f[4]; 1240 int i[4]; 1241 unsigned int ui[4]; 1242 }; 1243 1244 enum pipe_driver_query_type 1245 { 1246 PIPE_DRIVER_QUERY_TYPE_UINT64, 1247 PIPE_DRIVER_QUERY_TYPE_UINT, 1248 PIPE_DRIVER_QUERY_TYPE_FLOAT, 1249 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE, 1250 PIPE_DRIVER_QUERY_TYPE_BYTES, 1251 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS, 1252 PIPE_DRIVER_QUERY_TYPE_HZ, 1253 PIPE_DRIVER_QUERY_TYPE_DBM, 1254 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE, 1255 PIPE_DRIVER_QUERY_TYPE_VOLTS, 1256 PIPE_DRIVER_QUERY_TYPE_AMPS, 1257 PIPE_DRIVER_QUERY_TYPE_WATTS, 1258 }; 1259 1260 /* Whether an average value per frame or a cumulative value should be 1261 * displayed. 1262 */ 1263 enum pipe_driver_query_result_type 1264 { 1265 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 1266 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE, 1267 }; 1268 1269 /** 1270 * Some hardware requires some hardware-specific queries to be submitted 1271 * as batched queries. The corresponding query objects are created using 1272 * create_batch_query, and at most one such query may be active at 1273 * any time. 1274 */ 1275 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0) 1276 1277 /* Do not list this query in the HUD. */ 1278 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1) 1279 1280 struct pipe_driver_query_info 1281 { 1282 const char *name; 1283 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */ 1284 union pipe_numeric_type_union max_value; /* max value that can be returned */ 1285 enum pipe_driver_query_type type; 1286 enum pipe_driver_query_result_type result_type; 1287 unsigned group_id; 1288 unsigned flags; 1289 }; 1290 1291 struct pipe_driver_query_group_info 1292 { 1293 const char *name; 1294 unsigned max_active_queries; 1295 unsigned num_queries; 1296 }; 1297 1298 enum pipe_fd_type 1299 { 1300 PIPE_FD_TYPE_NATIVE_SYNC, 1301 PIPE_FD_TYPE_SYNCOBJ, 1302 }; 1303 1304 /** 1305 * counter type and counter data type enums used by INTEL_performance_query 1306 * APIs in gallium drivers. 1307 */ 1308 enum pipe_perf_counter_type 1309 { 1310 PIPE_PERF_COUNTER_TYPE_EVENT, 1311 PIPE_PERF_COUNTER_TYPE_DURATION_NORM, 1312 PIPE_PERF_COUNTER_TYPE_DURATION_RAW, 1313 PIPE_PERF_COUNTER_TYPE_THROUGHPUT, 1314 PIPE_PERF_COUNTER_TYPE_RAW, 1315 PIPE_PERF_COUNTER_TYPE_TIMESTAMP, 1316 }; 1317 1318 enum pipe_perf_counter_data_type 1319 { 1320 PIPE_PERF_COUNTER_DATA_TYPE_BOOL32, 1321 PIPE_PERF_COUNTER_DATA_TYPE_UINT32, 1322 PIPE_PERF_COUNTER_DATA_TYPE_UINT64, 1323 PIPE_PERF_COUNTER_DATA_TYPE_FLOAT, 1324 PIPE_PERF_COUNTER_DATA_TYPE_DOUBLE, 1325 }; 1326 1327 #define PIPE_UUID_SIZE 16 1328 1329 #ifdef __cplusplus 1330 } 1331 #endif 1332 1333 #endif 1334