1 /**************************************************************************
2 
3 Copyright (C) 2004-2005 Nicolai Haehnle et al.
4 
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 on the rights to use, copy, modify, merge, publish, distribute, sub
9 license, and/or sell copies of the Software, and to permit persons to whom
10 the Software is furnished to do so, subject to the following conditions:
11 
12 The above copyright notice and this permission notice (including the next
13 paragraph) shall be included in all copies or substantial portions of the
14 Software.
15 
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 USE OR OTHER DEALINGS IN THE SOFTWARE.
23 
24 **************************************************************************/
25 
26 /* *INDENT-OFF* */
27 
28 #ifndef _R300_REG_H
29 #define _R300_REG_H
30 
31 #define R300_MC_INIT_MISC_LAT_TIMER	0x180
32 #	define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT	0
33 #	define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT	4
34 #	define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT	8
35 #	define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT	12
36 #	define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT	16
37 #	define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT	20
38 #	define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT	24
39 #	define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT	28
40 
41 
42 #define R300_MC_INIT_GFX_LAT_TIMER	0x154
43 #	define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT	0
44 #	define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT	4
45 #	define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT	8
46 #	define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT	12
47 #	define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT	16
48 #	define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT	20
49 #	define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT	24
50 #	define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT	28
51 
52 /*
53  * This file contains registers and constants for the R300. They have been
54  * found mostly by examining command buffers captured using glxtest, as well
55  * as by extrapolating some known registers and constants from the R200.
56  * I am fairly certain that they are correct unless stated otherwise
57  * in comments.
58  */
59 
60 #define R300_SE_VPORT_XSCALE                0x1D98
61 #define R300_SE_VPORT_XOFFSET               0x1D9C
62 #define R300_SE_VPORT_YSCALE                0x1DA0
63 #define R300_SE_VPORT_YOFFSET               0x1DA4
64 #define R300_SE_VPORT_ZSCALE                0x1DA8
65 #define R300_SE_VPORT_ZOFFSET               0x1DAC
66 
67 #define R300_VAP_PORT_IDX0		    0x2040
68 /*
69  * Vertex Array Processing (VAP) Control
70  */
71 #define R300_VAP_CNTL	0x2080
72 #       define R300_PVS_NUM_SLOTS_SHIFT                 0
73 #       define R300_PVS_NUM_CNTLRS_SHIFT                4
74 #       define R300_PVS_NUM_FPUS_SHIFT                  8
75 #       define R300_VF_MAX_VTX_NUM_SHIFT                18
76 #       define R300_PVS_NUM_SLOTS(x)                    ((x) << 0)
77 #       define R300_PVS_NUM_CNTLRS(x)                   ((x) << 4)
78 #       define R300_PVS_NUM_FPUS(x)                     ((x) << 8)
79 #       define R300_PVS_VF_MAX_VTX_NUM(x)               ((x) << 18)
80 #       define R300_GL_CLIP_SPACE_DEF                   (0 << 22)
81 #       define R300_DX_CLIP_SPACE_DEF                   (1 << 22)
82 #       define R500_TCL_STATE_OPTIMIZATION              (1 << 23)
83 
84 /* This register is written directly and also starts data section
85  * in many 3d CP_PACKET3's
86  */
87 #define R300_VAP_VF_CNTL	0x2084
88 #	define	R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT              0
89 #	define  R300_VAP_VF_CNTL__PRIM_NONE                     (0<<0)
90 #	define  R300_VAP_VF_CNTL__PRIM_POINTS                   (1<<0)
91 #	define  R300_VAP_VF_CNTL__PRIM_LINES                    (2<<0)
92 #	define  R300_VAP_VF_CNTL__PRIM_LINE_STRIP               (3<<0)
93 #	define  R300_VAP_VF_CNTL__PRIM_TRIANGLES                (4<<0)
94 #	define  R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN             (5<<0)
95 #	define  R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP           (6<<0)
96 #	define  R300_VAP_VF_CNTL__PRIM_LINE_LOOP                (12<<0)
97 #	define  R300_VAP_VF_CNTL__PRIM_QUADS                    (13<<0)
98 #	define  R300_VAP_VF_CNTL__PRIM_QUAD_STRIP               (14<<0)
99 #	define  R300_VAP_VF_CNTL__PRIM_POLYGON                  (15<<0)
100 
101 #	define	R300_VAP_VF_CNTL__PRIM_WALK__SHIFT              4
102 	/* State based - direct writes to registers trigger vertex
103            generation */
104 #	define	R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED         (0<<4)
105 #	define	R300_VAP_VF_CNTL__PRIM_WALK_INDICES             (1<<4)
106 #	define	R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST         (2<<4)
107 #	define	R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED     (3<<4)
108 
109 	/* I don't think I saw these three used.. */
110 #	define	R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT            6
111 #	define	R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT     9
112 #	define	R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT        10
113 
114 	/* index size - when not set the indices are assumed to be 16 bit */
115 #	define	R300_VAP_VF_CNTL__INDEX_SIZE_32bit              (1<<11)
116 #       define R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS          (1<<14)
117 	/* number of vertices */
118 #	define	R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT           16
119 
120 #define R500_VAP_INDEX_OFFSET		    0x208c
121 
122 #define R500_VAP_ALT_NUM_VERTICES                           0x2088
123 
124 #define R300_VAP_OUTPUT_VTX_FMT_0           0x2090
125 #       define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT     (1<<0)
126 #       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1)
127 #       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2)
128 #       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3)
129 #       define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4)
130 #       define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16)
131 
132 #define R300_VAP_OUTPUT_VTX_FMT_1           0x2094
133 	/* each of the following is 3 bits wide, specifies number
134 	   of components */
135 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0
136 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3
137 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6
138 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9
139 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12
140 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15
141 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18
142 #       define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21
143 #	define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT  0
144 #	define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT  1
145 #	define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2
146 #	define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3
147 #	define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4
148 
149 #define R300_VAP_VPORT_XSCALE                     0x2098
150 #define R300_VAP_VPORT_XOFFSET                    0x209c
151 #define R300_VAP_VPORT_YSCALE                     0x20a0
152 #define R300_VAP_VPORT_YOFFSET                    0x20a4
153 #define R300_VAP_VPORT_ZSCALE                     0x20a8
154 #define R300_VAP_VPORT_ZOFFSET                    0x20ac
155 
156 #define R300_VAP_VTE_CNTL                         0x20b0
157 #define R300_SE_VTE_CNTL R300_VAP_VTE_CNTL
158 #   define R300_VPORT_X_SCALE_ENA                           (1 << 0)
159 #   define R300_VPORT_X_OFFSET_ENA                          (1 << 1)
160 #   define R300_VPORT_Y_SCALE_ENA                           (1 << 2)
161 #   define R300_VPORT_Y_OFFSET_ENA                          (1 << 3)
162 #   define R300_VPORT_Z_SCALE_ENA                           (1 << 4)
163 #   define R300_VPORT_Z_OFFSET_ENA                          (1 << 5)
164 #   define R300_VTX_XY_FMT                                  (1 << 8)
165 #   define R300_VTX_Z_FMT                                   (1 << 9)
166 #   define R300_VTX_W0_FMT                                  (1 << 10)
167 #   define R300_SERIAL_PROC_ENA                             (1 << 11)
168 
169 #define R300_VAP_VTX_SIZE               0x20b4
170 
171 /* BEGIN: Vertex data assembly - lots of uncertainties */
172 
173 /* gap */
174 
175 /* Maximum Vertex Indx Clamp */
176 #define R300_VAP_VF_MAX_VTX_INDX         0x2134
177 /* Minimum Vertex Indx Clamp */
178 #define R300_VAP_VF_MIN_VTX_INDX         0x2138
179 
180 /** Vertex assembler/processor control status */
181 #define R300_VAP_CNTL_STATUS              0x2140
182 /* No swap at all (default) */
183 #	define R300_VC_NO_SWAP                  (0 << 0)
184 /* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */
185 #	define R300_VC_16BIT_SWAP               (1 << 0)
186 /* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */
187 #	define R300_VC_32BIT_SWAP               (2 << 0)
188 /* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */
189 #	define R300_VC_HALF_DWORD_SWAP          (3 << 0)
190 /* The TCL engine will not be used (as it is logically or even physically removed) */
191 #	define R300_VAP_TCL_BYPASS		(1 << 8)
192 /* Read only flag if TCL engine is busy. */
193 #	define R300_VAP_PVS_BUSY                (1 << 11)
194 /* Read only flag if the vertex store is busy. */
195 #	define R300_VAP_VS_BUSY                 (1 << 24)
196 /* Read only flag if the reciprocal engine is busy. */
197 #	define R300_VAP_RCP_BUSY                (1 << 25)
198 /* Read only flag if the viewport transform engine is busy. */
199 #	define R300_VAP_VTE_BUSY                (1 << 26)
200 /* Read only flag if the memory interface unit is busy. */
201 #	define R300_VAP_MUI_BUSY                (1 << 27)
202 /* Read only flag if the vertex cache is busy. */
203 #	define R300_VAP_VC_BUSY                 (1 << 28)
204 /* Read only flag if the vertex fetcher is busy. */
205 #	define R300_VAP_VF_BUSY                 (1 << 29)
206 /* Read only flag if the register pipeline is busy. */
207 #	define R300_VAP_REGPIPE_BUSY            (1 << 30)
208 /* Read only flag if the VAP engine is busy. */
209 #	define R300_VAP_VAP_BUSY                (1 << 31)
210 
211 /* gap */
212 
213 /* Where do we get our vertex data?
214  *
215  * Vertex data either comes either from immediate mode registers or from
216  * vertex arrays.
217  * There appears to be no mixed mode (though we can force the pitch of
218  * vertex arrays to 0, effectively reusing the same element over and over
219  * again).
220  *
221  * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure
222  * if these registers influence vertex array processing.
223  *
224  * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.
225  *
226  * In both cases, vertex attributes are then passed through INPUT_ROUTE.
227  *
228  * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data
229  * into the vertex processor's input registers.
230  * The first word routes the first input, the second word the second, etc.
231  * The corresponding input is routed into the register with the given index.
232  * The list is ended by a word with INPUT_ROUTE_END set.
233  *
234  * Always set COMPONENTS_4 in immediate mode.
235  */
236 
237 #define R300_VAP_PROG_STREAM_CNTL_0                     0x2150
238 #       define R300_DATA_TYPE_0_SHIFT                   0
239 #       define R300_DATA_TYPE_FLOAT_1                   0
240 #       define R300_DATA_TYPE_FLOAT_2                   1
241 #       define R300_DATA_TYPE_FLOAT_3                   2
242 #       define R300_DATA_TYPE_FLOAT_4                   3
243 #       define R300_DATA_TYPE_BYTE                      4
244 #       define R300_DATA_TYPE_D3DCOLOR                  5
245 #       define R300_DATA_TYPE_SHORT_2                   6
246 #       define R300_DATA_TYPE_SHORT_4                   7
247 #       define R300_DATA_TYPE_VECTOR_3_TTT              8
248 #       define R300_DATA_TYPE_VECTOR_3_EET              9
249 #       define R300_DATA_TYPE_FLOAT_8                   10
250 #       define R300_DATA_TYPE_FLT16_2                   11
251 #       define R300_DATA_TYPE_FLT16_4                   12
252 #       define R300_SKIP_DWORDS_SHIFT                   4
253 #       define R300_DST_VEC_LOC_SHIFT                   8
254 #       define R300_LAST_VEC                            (1 << 13)
255 #       define R300_SIGNED                              (1 << 14)
256 #       define R300_NORMALIZE                           (1 << 15)
257 #       define R300_DATA_TYPE_1_SHIFT                   16
258 #define R300_VAP_PROG_STREAM_CNTL_1                     0x2154
259 #define R300_VAP_PROG_STREAM_CNTL_2                     0x2158
260 #define R300_VAP_PROG_STREAM_CNTL_3                     0x215C
261 #define R300_VAP_PROG_STREAM_CNTL_4                     0x2160
262 #define R300_VAP_PROG_STREAM_CNTL_5                     0x2164
263 #define R300_VAP_PROG_STREAM_CNTL_6                     0x2168
264 #define R300_VAP_PROG_STREAM_CNTL_7                     0x216C
265 /* gap */
266 
267 /* Notes:
268  *  - always set up to produce at least two attributes:
269  *    if vertex program uses only position, fglrx will set normal, too
270  *  - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
271  */
272 #define R300_VAP_VTX_STATE_CNTL               0x2180
273 #       define R300_COLOR_0_ASSEMBLY_SHIFT    0
274 #       define R300_SEL_COLOR                 0
275 #       define R300_SEL_USER_COLOR_0          1
276 #       define R300_SEL_USER_COLOR_1          2
277 #       define R300_COLOR_1_ASSEMBLY_SHIFT    2
278 #       define R300_COLOR_2_ASSEMBLY_SHIFT    4
279 #       define R300_COLOR_3_ASSEMBLY_SHIFT    6
280 #       define R300_COLOR_4_ASSEMBLY_SHIFT    8
281 #       define R300_COLOR_5_ASSEMBLY_SHIFT    10
282 #       define R300_COLOR_6_ASSEMBLY_SHIFT    12
283 #       define R300_COLOR_7_ASSEMBLY_SHIFT    14
284 #       define R300_UPDATE_USER_COLOR_0_ENA   (1 << 16)
285 
286 /*
287  * Each bit in this field applies to the corresponding vector in the VSM
288  * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit
289  * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream.
290  */
291 #define R300_VAP_VSM_VTX_ASSM               0x2184
292 #       define R300_INPUT_CNTL_POS               0x00000001
293 #       define R300_INPUT_CNTL_NORMAL            0x00000002
294 #       define R300_INPUT_CNTL_COLOR             0x00000004
295 #       define R300_INPUT_CNTL_TC0               0x00000400
296 #       define R300_INPUT_CNTL_TC1               0x00000800
297 #       define R300_INPUT_CNTL_TC2               0x00001000 /* GUESS */
298 #       define R300_INPUT_CNTL_TC3               0x00002000 /* GUESS */
299 #       define R300_INPUT_CNTL_TC4               0x00004000 /* GUESS */
300 #       define R300_INPUT_CNTL_TC5               0x00008000 /* GUESS */
301 #       define R300_INPUT_CNTL_TC6               0x00010000 /* GUESS */
302 #       define R300_INPUT_CNTL_TC7               0x00020000 /* GUESS */
303 
304 /* Programmable Stream Control Signed Normalize Control */
305 #define R300_VAP_PSC_SGN_NORM_CNTL                0x21dc
306 #   define SGN_NORM_ZERO                                    0
307 #   define SGN_NORM_ZERO_CLAMP_MINUS_ONE                    1
308 #   define SGN_NORM_NO_ZERO                                 2
309 #   define R300_SGN_NORM_NO_ZERO (SGN_NORM_NO_ZERO | \
310         (SGN_NORM_NO_ZERO << 2) | (SGN_NORM_NO_ZERO << 4) | \
311         (SGN_NORM_NO_ZERO << 6) | (SGN_NORM_NO_ZERO << 8) | \
312         (SGN_NORM_NO_ZERO << 10) | (SGN_NORM_NO_ZERO << 12) | \
313         (SGN_NORM_NO_ZERO << 14) | (SGN_NORM_NO_ZERO << 16) | \
314         (SGN_NORM_NO_ZERO << 18) | (SGN_NORM_NO_ZERO << 20) | \
315         (SGN_NORM_NO_ZERO << 22) | (SGN_NORM_NO_ZERO << 24) | \
316         (SGN_NORM_NO_ZERO << 26) | (SGN_NORM_NO_ZERO << 28) | \
317         (SGN_NORM_NO_ZERO << 30))
318 
319 /* gap */
320 
321 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0
322  * are set to a swizzling bit pattern, other words are 0.
323  *
324  * In immediate mode, the pattern is always set to xyzw. In vertex array
325  * mode, the swizzling pattern is e.g. used to set zw components in texture
326  * coordinates with only tweo components.
327  */
328 #define R300_VAP_PROG_STREAM_CNTL_EXT_0                 0x21e0
329 #       define R300_SWIZZLE0_SHIFT                      0
330 #       define R300_SWIZZLE_SELECT_X_SHIFT              0
331 #       define R300_SWIZZLE_SELECT_Y_SHIFT              3
332 #       define R300_SWIZZLE_SELECT_Z_SHIFT              6
333 #       define R300_SWIZZLE_SELECT_W_SHIFT              9
334 
335 #       define R300_SWIZZLE_SELECT_X                    0
336 #       define R300_SWIZZLE_SELECT_Y                    1
337 #       define R300_SWIZZLE_SELECT_Z                    2
338 #       define R300_SWIZZLE_SELECT_W                    3
339 #       define R300_SWIZZLE_SELECT_FP_ZERO              4
340 #       define R300_SWIZZLE_SELECT_FP_ONE               5
341 /* alternate forms for r300_emit.c */
342 #       define R300_INPUT_ROUTE_SELECT_X    0
343 #       define R300_INPUT_ROUTE_SELECT_Y    1
344 #       define R300_INPUT_ROUTE_SELECT_Z    2
345 #       define R300_INPUT_ROUTE_SELECT_W    3
346 #       define R300_INPUT_ROUTE_SELECT_ZERO 4
347 #       define R300_INPUT_ROUTE_SELECT_ONE  5
348 
349 #       define R300_WRITE_ENA_SHIFT                     12
350 #       define R300_WRITE_ENA_X                         1
351 #       define R300_WRITE_ENA_Y                         2
352 #       define R300_WRITE_ENA_Z                         4
353 #       define R300_WRITE_ENA_W                         8
354 #       define R300_SWIZZLE1_SHIFT                      16
355 
356 #       define R300_VAP_SWIZZLE_X001 \
357         ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \
358          (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Y_SHIFT) | \
359          (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | \
360          (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \
361          (0xf << R300_WRITE_ENA_SHIFT))
362 
363 #       define R300_VAP_SWIZZLE_XY01 \
364         ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \
365          (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \
366          (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) | \
367          (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \
368          (0xf << R300_WRITE_ENA_SHIFT))
369 
370 #       define R300_VAP_SWIZZLE_XYZ1 \
371         ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \
372          (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \
373          (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | \
374          (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) | \
375          (0xf << R300_WRITE_ENA_SHIFT))
376 
377 #       define R300_VAP_SWIZZLE_XYZW \
378         ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | \
379          (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | \
380          (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | \
381          (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | \
382          (0xf << R300_WRITE_ENA_SHIFT))
383 
384 #define R300_VAP_PROG_STREAM_CNTL_EXT_1                 0x21e4
385 #define R300_VAP_PROG_STREAM_CNTL_EXT_2                 0x21e8
386 #define R300_VAP_PROG_STREAM_CNTL_EXT_3                 0x21ec
387 #define R300_VAP_PROG_STREAM_CNTL_EXT_4                 0x21f0
388 #define R300_VAP_PROG_STREAM_CNTL_EXT_5                 0x21f4
389 #define R300_VAP_PROG_STREAM_CNTL_EXT_6                 0x21f8
390 #define R300_VAP_PROG_STREAM_CNTL_EXT_7                 0x21fc
391 
392 /* END: Vertex data assembly */
393 
394 /* gap */
395 
396 /* BEGIN: Upload vertex program and data */
397 
398 /*
399  * The programmable vertex shader unit has a memory bank of unknown size
400  * that can be written to in 16 byte units by writing the address into
401  * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).
402  *
403  * Pointers into the memory bank are always in multiples of 16 bytes.
404  *
405  * The memory bank is divided into areas with fixed meaning.
406  *
407  * Starting at address UPLOAD_PROGRAM: Vertex program instructions.
408  * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),
409  * whereas the difference between known addresses suggests size 512.
410  *
411  * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.
412  * Native reported limits and the VPI layout suggest size 256, whereas
413  * difference between known addresses suggests size 512.
414  *
415  * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the
416  * floating point pointsize. The exact purpose of this state is uncertain,
417  * as there is also the R300_RE_POINTSIZE register.
418  *
419  * Multiple vertex programs and parameter sets can be loaded at once,
420  * which could explain the size discrepancy.
421  */
422 #define R300_VAP_PVS_VECTOR_INDX_REG         0x2200
423 #       define R300_PVS_CODE_START           0
424 #       define R300_MAX_PVS_CODE_LINES       256
425 #       define R500_MAX_PVS_CODE_LINES       1024
426 #       define R300_PVS_CONST_START          512
427 #       define R500_PVS_CONST_START          1024
428 #       define R300_MAX_PVS_CONST_VECS       256
429 #       define R500_MAX_PVS_CONST_VECS       256
430 #       define R300_PVS_UCP_START            1024
431 #       define R500_PVS_UCP_START            1536
432 #       define R300_POINT_VPORT_SCALE_OFFSET 1030
433 #       define R500_POINT_VPORT_SCALE_OFFSET 1542
434 #       define R300_POINT_GEN_TEX_OFFSET     1031
435 #       define R500_POINT_GEN_TEX_OFFSET     1543
436 
437 /*
438  * These are obsolete defines form r300_context.h, but they might give some
439  * clues when investigating the addresses further...
440  */
441 #if 0
442 #define VSF_DEST_PROGRAM        0x0
443 #define VSF_DEST_MATRIX0        0x200
444 #define VSF_DEST_MATRIX1        0x204
445 #define VSF_DEST_MATRIX2        0x208
446 #define VSF_DEST_VECTOR0        0x20c
447 #define VSF_DEST_VECTOR1        0x20d
448 #define VSF_DEST_UNKNOWN1       0x400
449 #define VSF_DEST_UNKNOWN2       0x406
450 #endif
451 
452 /* gap */
453 
454 #define R300_VAP_PVS_UPLOAD_DATA            0x2208
455 
456 /* END: Upload vertex program and data */
457 
458 /* gap */
459 
460 /* I do not know the purpose of this register. However, I do know that
461  * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL
462  * for normal rendering.
463  *
464  * 2007-11-05: This register is the user clip plane control register, but there
465  * also seems to be a rendering mode control; the NORMAL/CLEAR defines.
466  *
467  * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view
468  */
469 #define R500_VAP_TEX_TO_COLOR_CNTL		0x2218
470 
471 #define R300_VAP_CLIP_CNTL                       0x221C
472 #       define R300_VAP_UCP_ENABLE_0             (1 << 0)
473 #       define R300_VAP_UCP_ENABLE_1             (1 << 1)
474 #       define R300_VAP_UCP_ENABLE_2             (1 << 2)
475 #       define R300_VAP_UCP_ENABLE_3             (1 << 3)
476 #       define R300_VAP_UCP_ENABLE_4             (1 << 4)
477 #       define R300_VAP_UCP_ENABLE_5             (1 << 5)
478 #       define R300_PS_UCP_MODE_DIST_COP         (0 << 14)
479 #       define R300_PS_UCP_MODE_RADIUS_COP       (1 << 14)
480 #       define R300_PS_UCP_MODE_RADIUS_COP_CLIP  (2 << 14)
481 #       define R300_PS_UCP_MODE_CLIP_AS_TRIFAN   (3 << 14)
482 #       define R300_CLIP_DISABLE                 (1 << 16)
483 #       define R300_UCP_CULL_ONLY_ENABLE         (1 << 17)
484 #       define R300_BOUNDARY_EDGE_FLAG_ENABLE    (1 << 18)
485 #       define R500_COLOR2_IS_TEXTURE            (1 << 20)
486 #       define R500_COLOR3_IS_TEXTURE            (1 << 21)
487 
488 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
489  * plane is per-pixel and the second plane is per-vertex.
490  *
491  * This was determined by experimentation alone but I believe it is correct.
492  *
493  * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.
494  */
495 #define R300_VAP_GB_VERT_CLIP_ADJ                   0x2220
496 #define R300_VAP_GB_VERT_DISC_ADJ                   0x2224
497 #define R300_VAP_GB_HORZ_CLIP_ADJ                   0x2228
498 #define R300_VAP_GB_HORZ_DISC_ADJ                   0x222c
499 
500 #define R300_VAP_PVS_FLOW_CNTL_ADDRS_0      0x2230
501 #define R300_PVS_FC_ACT_ADRS(x)             ((x) << 0)
502 #define R300_PVS_FC_LOOP_CNT_JMP_INST(x)    ((x) << 8)
503 #define R300_PVS_FC_LAST_INST(x)            ((x) << 16)
504 #define R300_PVS_FC_RTN_INST(x)             ((x) << 24)
505 
506 /* gap */
507 
508 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between
509  * rendering commands and overwriting vertex program parameters.
510  * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
511  * avoids bugs caused by still running shaders reading bad data from memory.
512  */
513 #define R300_VAP_PVS_STATE_FLUSH_REG        0x2284
514 
515 /* This register is used to define the number of core clocks to wait for a
516  * vertex to be received by the VAP input controller (while the primitive
517  * path is backed up) before forcing any accumulated vertices to be submitted
518  * to the vertex processing path.
519  */
520 #define VAP_PVS_VTX_TIMEOUT_REG             0x2288
521 #       define R300_2288_R300                    0x00750000 /* -- nh */
522 #       define R300_2288_RV350                   0x0000FFFF /* -- Vladimir */
523 
524 #define R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 0x2290
525 #define R300_PVS_FC_LOOP_INIT_VAL(x)        ((x) << 0)
526 #define R300_PVS_FC_LOOP_STEP_VAL(x)        ((x) << 8)
527 
528 /* gap */
529 
530 /* Addresses are relative to the vertex program instruction area of the
531  * memory bank. PROGRAM_END points to the last instruction of the active
532  * program
533  *
534  * The meaning of the two UNKNOWN fields is obviously not known. However,
535  * experiments so far have shown that both *must* point to an instruction
536  * inside the vertex program, otherwise the GPU locks up.
537  *
538  * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and
539  * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to
540  * position takes place.
541  *
542  * Most likely this is used to ignore rest of the program in cases
543  * where group of verts arent visible. For some reason this "section"
544  * is sometimes accepted other instruction that have no relationship with
545  * position calculations.
546  */
547 #define R300_VAP_PVS_CODE_CNTL_0            0x22D0
548 #       define R300_PVS_FIRST_INST_SHIFT         0
549 #       define R300_PVS_XYZW_VALID_INST_SHIFT    10
550 #       define R300_PVS_LAST_INST_SHIFT          20
551 #       define R300_PVS_FIRST_INST(x)            ((x) << 0)
552 #       define R300_PVS_XYZW_VALID_INST(x)       ((x) << 10)
553 #       define R300_PVS_LAST_INST(x)             ((x) << 20)
554 /* Addresses are relative to the vertex program parameters area. */
555 #define R300_VAP_PVS_CONST_CNTL             0x22D4
556 #       define R300_PVS_CONST_BASE_OFFSET_SHIFT  0
557 #       define R300_PVS_CONST_BASE_OFFSET(x)     (x)
558 #       define R300_PVS_MAX_CONST_ADDR_SHIFT     16
559 #       define R300_PVS_MAX_CONST_ADDR(x)        ((x) << 16)
560 #define R300_VAP_PVS_CODE_CNTL_1	    0x22D8
561 #       define R300_PVS_LAST_VTX_SRC_INST_SHIFT  0
562 #define R300_VAP_PVS_FLOW_CNTL_OPC          0x22DC
563 #define R300_VAP_PVS_FC_OPC_JUMP(x)         (1 << (2 * (x)))
564 #define R300_VAP_PVS_FC_OPC_LOOP(x)         (2 << (2 * (x)))
565 #define R300_VAP_PVS_FC_OPC_JSR(x)          (3 << (2 * (x)))
566 
567 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for
568  * immediate vertices
569  */
570 #define R300_VAP_VTX_COLOR_R                0x2464
571 #define R300_VAP_VTX_COLOR_G                0x2468
572 #define R300_VAP_VTX_COLOR_B                0x246C
573 #define R300_VAP_VTX_POS_0_X_1              0x2490 /* used for glVertex2*() */
574 #define R300_VAP_VTX_POS_0_Y_1              0x2494
575 #define R300_VAP_VTX_COLOR_PKD              0x249C /* RGBA */
576 #define R300_VAP_VTX_POS_0_X_2              0x24A0 /* used for glVertex3*() */
577 #define R300_VAP_VTX_POS_0_Y_2              0x24A4
578 #define R300_VAP_VTX_POS_0_Z_2              0x24A8
579 /* write 0 to indicate end of packet? */
580 #define R300_VAP_VTX_END_OF_PKT             0x24AC
581 
582 #define R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0   0x2500
583 #define R500_PVS_FC_ACT_ADRS(x)             ((x) << 0)
584 #define R500_PVS_FC_LOOP_CNT_JMP_INST(x)    ((x) << 16)
585 
586 #define R500_VAP_PVS_FLOW_CNTL_ADDRS_UW_0   0x2504
587 #define R500_PVS_FC_LAST_INST(x)            ((x) << 0)
588 #define R500_PVS_FC_RTN_INST(x)             ((x) << 16)
589 
590 /* gap */
591 
592 /* These are values from r300_reg/r300_reg.h - they are known to be correct
593  * and are here so we can use one register file instead of several
594  * - Vladimir
595  */
596 #define R300_GB_VAP_RASTER_VTX_FMT_0	0x4000
597 #	define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT	(1<<0)
598 #	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT	(1<<1)
599 #	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT	(1<<2)
600 #	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT	(1<<3)
601 #	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT	(1<<4)
602 #	define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE	(0xf<<5)
603 #	define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT	(0x1<<16)
604 
605 #define R300_GB_VAP_RASTER_VTX_FMT_1	0x4004
606 	/* each of the following is 3 bits wide, specifies number
607 	   of components */
608 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT	0
609 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT	3
610 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT	6
611 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT	9
612 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT	12
613 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT	15
614 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT	18
615 #	define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT	21
616 
617 /* UNK30 seems to enables point to quad transformation on textures
618  * (or something closely related to that).
619  * This bit is rather fatal at the time being due to lackings at pixel
620  * shader side
621  * Specifies top of Raster pipe specific enable controls.
622  */
623 #define R300_GB_ENABLE	0x4008
624 #	define R300_GB_POINT_STUFF_DISABLE     (0 << 0)
625 #	define R300_GB_POINT_STUFF_ENABLE      (1 << 0) /* Specifies if points will have stuffed texture coordinates. */
626 #	define R300_GB_LINE_STUFF_DISABLE      (0 << 1)
627 #	define R300_GB_LINE_STUFF_ENABLE       (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */
628 #	define R300_GB_TRIANGLE_STUFF_DISABLE  (0 << 2)
629 #	define R300_GB_TRIANGLE_STUFF_ENABLE   (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */
630 #	define R300_GB_STENCIL_AUTO_DISABLE    (0 << 4)
631 #	define R300_GB_STENCIL_AUTO_ENABLE     (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */
632 #	define R300_GB_STENCIL_AUTO_FORCE      (2 << 4) /* Force 0 into dzy low bit. */
633 
634 	/* each of the following is 2 bits wide */
635 #define R300_GB_TEX_REPLICATE	0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */
636 #define R300_GB_TEX_ST		1 /* Stuff with source texture coordinates (S,T). */
637 #define R300_GB_TEX_STR		2 /* Stuff with source texture coordinates (S,T,R). */
638 #	define R300_GB_TEX0_SOURCE_SHIFT	16
639 #	define R300_GB_TEX1_SOURCE_SHIFT	18
640 #	define R300_GB_TEX2_SOURCE_SHIFT	20
641 #	define R300_GB_TEX3_SOURCE_SHIFT	22
642 #	define R300_GB_TEX4_SOURCE_SHIFT	24
643 #	define R300_GB_TEX5_SOURCE_SHIFT	26
644 #	define R300_GB_TEX6_SOURCE_SHIFT	28
645 #	define R300_GB_TEX7_SOURCE_SHIFT	30
646 
647 /* MSPOS - positions for multisample antialiasing (?) */
648 #define R300_GB_MSPOS0                           0x4010
649 	/* shifts - each of the fields is 4 bits */
650 #	define R300_GB_MSPOS0__MS_X0_SHIFT	0
651 #	define R300_GB_MSPOS0__MS_Y0_SHIFT	4
652 #	define R300_GB_MSPOS0__MS_X1_SHIFT	8
653 #	define R300_GB_MSPOS0__MS_Y1_SHIFT	12
654 #	define R300_GB_MSPOS0__MS_X2_SHIFT	16
655 #	define R300_GB_MSPOS0__MS_Y2_SHIFT	20
656 #	define R300_GB_MSPOS0__MSBD0_Y		24
657 #	define R300_GB_MSPOS0__MSBD0_X		28
658 
659 #define R300_GB_MSPOS1                           0x4014
660 #	define R300_GB_MSPOS1__MS_X3_SHIFT	0
661 #	define R300_GB_MSPOS1__MS_Y3_SHIFT	4
662 #	define R300_GB_MSPOS1__MS_X4_SHIFT	8
663 #	define R300_GB_MSPOS1__MS_Y4_SHIFT	12
664 #	define R300_GB_MSPOS1__MS_X5_SHIFT	16
665 #	define R300_GB_MSPOS1__MS_Y5_SHIFT	20
666 #	define R300_GB_MSPOS1__MSBD1		24
667 
668 /* Specifies the graphics pipeline configuration for rasterization. */
669 #define R300_GB_TILE_CONFIG                      0x4018
670 #	define R300_GB_TILE_DISABLE             (0 << 0)
671 #	define R300_GB_TILE_ENABLE              (1 << 0)
672 #	define R300_GB_TILE_PIPE_COUNT_RV300	(0 << 1) /* RV350 (1 pipe, 1 ctx) */
673 #	define R300_GB_TILE_PIPE_COUNT_R300	(3 << 1) /* R300 (2 pipes, 1 ctx) */
674 #	define R300_GB_TILE_PIPE_COUNT_R420_3P  (6 << 1) /* R420-3P (3 pipes, 1 ctx) */
675 #	define R300_GB_TILE_PIPE_COUNT_R420	(7 << 1) /* R420 (4 pipes, 1 ctx) */
676 #	define R300_GB_TILE_SIZE_8		(0 << 4)
677 #	define R300_GB_TILE_SIZE_16		(1 << 4)
678 #	define R300_GB_TILE_SIZE_32		(2 << 4)
679 #	define R300_GB_SUPER_SIZE_1		(0 << 6)
680 #	define R300_GB_SUPER_SIZE_2		(1 << 6)
681 #	define R300_GB_SUPER_SIZE_4		(2 << 6)
682 #	define R300_GB_SUPER_SIZE_8		(3 << 6)
683 #	define R300_GB_SUPER_SIZE_16		(4 << 6)
684 #	define R300_GB_SUPER_SIZE_32		(5 << 6)
685 #	define R300_GB_SUPER_SIZE_64		(6 << 6)
686 #	define R300_GB_SUPER_SIZE_128		(7 << 6)
687 #	define R300_GB_SUPER_X_SHIFT		9	/* 3 bits wide */
688 #	define R300_GB_SUPER_Y_SHIFT		12	/* 3 bits wide */
689 #	define R300_GB_SUPER_TILE_A		(0 << 15)
690 #	define R300_GB_SUPER_TILE_B		(1 << 15)
691 #	define R300_GB_SUBPIXEL_1_12		(0 << 16)
692 #	define R300_GB_SUBPIXEL_1_16		(1 << 16)
693 #	define R300_GB_TILE_CONFIG_QUADS_PER_RAS_4   (0 << 17)
694 #	define R300_GB_TILE_CONFIG_QUADS_PER_RAS_8   (1 << 17)
695 #	define R300_GB_TILE_CONFIG_QUADS_PER_RAS_16  (2 << 17)
696 #	define R300_GB_TILE_CONFIG_QUADS_PER_RAS_32  (3 << 17)
697 #	define R300_GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19)
698 #	define R300_GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19)
699 #	define R300_GB_TILE_CONFIG_ALT_SCAN_EN_LR    (0 << 20)
700 #	define R300_GB_TILE_CONFIG_ALT_SCAN_EN_LRL   (1 << 20)
701 #	define R300_GB_TILE_CONFIG_ALT_OFFSET        (0 << 21)
702 #	define R300_GB_TILE_CONFIG_SUBPRECISION      (0 << 22)
703 #	define R300_GB_TILE_CONFIG_ALT_TILING_DEF    (0 << 23)
704 #	define R300_GB_TILE_CONFIG_ALT_TILING_3_2    (1 << 23)
705 #	define R300_GB_TILE_CONFIG_Z_EXTENDED_24_1   (0 << 24)
706 #	define R300_GB_TILE_CONFIG_Z_EXTENDED_S25_1  (1 << 24)
707 
708 /* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */
709 #define R300_GB_FIFO_SIZE	0x4024
710 	/* each of the following is 2 bits wide */
711 #define R300_GB_FIFO_SIZE_32	0
712 #define R300_GB_FIFO_SIZE_64	1
713 #define R300_GB_FIFO_SIZE_128	2
714 #define R300_GB_FIFO_SIZE_256	3
715 #	define R300_SC_IFIFO_SIZE_SHIFT	0
716 #	define R300_SC_TZFIFO_SIZE_SHIFT	2
717 #	define R300_SC_BFIFO_SIZE_SHIFT	4
718 
719 #	define R300_US_OFIFO_SIZE_SHIFT	12
720 #	define R300_US_WFIFO_SIZE_SHIFT	14
721 	/* the following use the same constants as above, but meaning is
722 	   is times 2 (i.e. instead of 32 words it means 64 */
723 #	define R300_RS_TFIFO_SIZE_SHIFT	6
724 #	define R300_RS_CFIFO_SIZE_SHIFT	8
725 #	define R300_US_RAM_SIZE_SHIFT		10
726 	/* watermarks, 3 bits wide */
727 #	define R300_RS_HIGHWATER_COL_SHIFT	16
728 #	define R300_RS_HIGHWATER_TEX_SHIFT	19
729 #	define R300_OFIFO_HIGHWATER_SHIFT	22	/* two bits only */
730 #	define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT	24
731 
732 #define R300_GB_Z_PEQ_CONFIG                          0x4028
733 #	define R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4    (0 << 0)
734 #	define R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8    (1 << 0)
735 
736 /* Specifies various polygon specific selects (fog, depth, perspective). */
737 #define R300_GB_SELECT                           0x401c
738 #	define R300_GB_FOG_SELECT_C0A		(0 << 0)
739 #	define R300_GB_FOG_SELECT_C1A           (1 << 0)
740 #	define R300_GB_FOG_SELECT_C2A           (2 << 0)
741 #	define R300_GB_FOG_SELECT_C3A           (3 << 0)
742 #	define R300_GB_FOG_SELECT_1_1_W         (4 << 0)
743 #	define R300_GB_FOG_SELECT_Z		(5 << 0)
744 #	define R300_GB_DEPTH_SELECT_Z		(0 << 3)
745 #	define R300_GB_DEPTH_SELECT_1_1_W	(1 << 3)
746 #	define R300_GB_W_SELECT_1_W		(0 << 4)
747 #	define R300_GB_W_SELECT_1		(1 << 4)
748 #	define R300_GB_FOG_STUFF_DISABLE        (0 << 5)
749 #	define R300_GB_FOG_STUFF_ENABLE         (1 << 5)
750 #	define R300_GB_FOG_STUFF_TEX_SHIFT      6
751 #	define R300_GB_FOG_STUFF_TEX_MASK       0x000003c0
752 #	define R300_GB_FOG_STUFF_COMP_SHIFT     10
753 #	define R300_GB_FOG_STUFF_COMP_MASK      0x00000c00
754 
755 /* Specifies the graphics pipeline configuration for antialiasing. */
756 #define R300_GB_AA_CONFIG                         0x4020
757 #	define R300_GB_AA_CONFIG_AA_DISABLE           (0 << 0)
758 #	define R300_GB_AA_CONFIG_AA_ENABLE            (1 << 0)
759 #	define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2  (0 << 1)
760 #	define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3  (1 << 1)
761 #	define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4  (2 << 1)
762 #	define R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6  (3 << 1)
763 
764 /* Selects which of 4 pipes are active. */
765 #define R300_GB_PIPE_SELECT                           0x402c
766 #	define R300_GB_PIPE_SELECT_PIPE0_ID_SHIFT  0
767 #	define R300_GB_PIPE_SELECT_PIPE1_ID_SHIFT  2
768 #	define R300_GB_PIPE_SELECT_PIPE2_ID_SHIFT  4
769 #	define R300_GB_PIPE_SELECT_PIPE3_ID_SHIFT  6
770 #	define R300_GB_PIPE_SELECT_PIPE_MASK_SHIFT 8
771 #	define R300_GB_PIPE_SELECT_MAX_PIPE        12
772 #	define R300_GB_PIPE_SELECT_BAD_PIPES       14
773 #	define R300_GB_PIPE_SELECT_CONFIG_PIPES    18
774 
775 
776 /* Specifies the sizes of the various FIFO`s in the sc/rs. */
777 #define R300_GB_FIFO_SIZE1                            0x4070
778 /* High water mark for SC input fifo */
779 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0
780 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK  0x0000003f
781 /* High water mark for SC input fifo (B) */
782 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6
783 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK  0x00000fc0
784 /* High water mark for RS colors' fifo */
785 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT   12
786 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK    0x0003f000
787 /* High water mark for RS textures' fifo */
788 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT   18
789 #	define R300_GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK    0x00fc0000
790 
791 /* This table specifies the source location and format for up to 16 texture
792  * addresses (i[0]:i[15]) and four colors (c[0]:c[3])
793  */
794 #define R500_RS_IP_0					0x4074
795 #define R500_RS_IP_1					0x4078
796 #define R500_RS_IP_2					0x407C
797 #define R500_RS_IP_3					0x4080
798 #define R500_RS_IP_4					0x4084
799 #define R500_RS_IP_5					0x4088
800 #define R500_RS_IP_6					0x408C
801 #define R500_RS_IP_7					0x4090
802 #define R500_RS_IP_8					0x4094
803 #define R500_RS_IP_9					0x4098
804 #define R500_RS_IP_10					0x409C
805 #define R500_RS_IP_11					0x40A0
806 #define R500_RS_IP_12					0x40A4
807 #define R500_RS_IP_13					0x40A8
808 #define R500_RS_IP_14					0x40AC
809 #define R500_RS_IP_15					0x40B0
810 #define R500_RS_IP_PTR_K0                               62
811 #define R500_RS_IP_PTR_K1                               63
812 #define R500_RS_IP_TEX_PTR_S_SHIFT 			0
813 #define R500_RS_IP_TEX_PTR_T_SHIFT 			6
814 #define R500_RS_IP_TEX_PTR_R_SHIFT 			12
815 #define R500_RS_IP_TEX_PTR_Q_SHIFT 			18
816 #define R500_RS_IP_COL_PTR_SHIFT 			24
817 #define R500_RS_IP_COL_FMT_SHIFT 			27
818 #       define R500_RS_SEL_S(x)                         ((x) << 0)
819 #       define R500_RS_SEL_T(x)                         ((x) << 6)
820 #       define R500_RS_SEL_R(x)                         ((x) << 12)
821 #       define R500_RS_SEL_Q(x)                         ((x) << 18)
822 #	define R500_RS_COL_PTR(x)		        ((x) << 24)
823 #       define R500_RS_COL_FMT(x)                       ((x) << 27)
824 /* gap */
825 #define R500_RS_IP_OFFSET_DIS 				(0 << 31)
826 #define R500_RS_IP_OFFSET_EN 				(1 << 31)
827 
828 /* gap */
829 
830 /* Zero to flush caches. */
831 #define R300_TX_INVALTAGS                   0x4100
832 #define R300_TX_FLUSH                       0x0
833 
834 /* The upper enable bits are guessed, based on fglrx reported limits. */
835 #define R300_TX_ENABLE                      0x4104
836 #       define R300_TX_ENABLE_0                  (1 << 0)
837 #       define R300_TX_ENABLE_1                  (1 << 1)
838 #       define R300_TX_ENABLE_2                  (1 << 2)
839 #       define R300_TX_ENABLE_3                  (1 << 3)
840 #       define R300_TX_ENABLE_4                  (1 << 4)
841 #       define R300_TX_ENABLE_5                  (1 << 5)
842 #       define R300_TX_ENABLE_6                  (1 << 6)
843 #       define R300_TX_ENABLE_7                  (1 << 7)
844 #       define R300_TX_ENABLE_8                  (1 << 8)
845 #       define R300_TX_ENABLE_9                  (1 << 9)
846 #       define R300_TX_ENABLE_10                 (1 << 10)
847 #       define R300_TX_ENABLE_11                 (1 << 11)
848 #       define R300_TX_ENABLE_12                 (1 << 12)
849 #       define R300_TX_ENABLE_13                 (1 << 13)
850 #       define R300_TX_ENABLE_14                 (1 << 14)
851 #       define R300_TX_ENABLE_15                 (1 << 15)
852 
853 #define R500_TX_FILTER_4		    0x4110
854 #	define R500_TX_WEIGHT_1_SHIFT            (0)
855 #	define R500_TX_WEIGHT_0_SHIFT            (11)
856 #	define R500_TX_WEIGHT_PAIR               (1<<22)
857 #	define R500_TX_PHASE_SHIFT               (23)
858 #	define R500_TX_DIRECTION_HORIZONTAL	 (0<<27)
859 #	define R500_TX_DIRECTION_VERITCAL	 (1<<27)
860 
861 #define R500_SU_TEX_WRAP_PS3		    0x4114
862 
863 /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
864 #define R300_GA_POINT_S0                              0x4200
865 
866 /* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */
867 #define R300_GA_POINT_T0                              0x4204
868 
869 /* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
870 #define R300_GA_POINT_S1                              0x4208
871 
872 /* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */
873 #define R300_GA_POINT_T1                              0x420c
874 
875 /* Specifies amount to shift integer position of vertex (screen space) before
876  * converting to float for triangle stipple.
877  */
878 #define R300_GA_TRIANGLE_STIPPLE            0x4214
879 #	define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0
880 #	define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK  0x0000000f
881 #	define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16
882 #	define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK  0x000f0000
883 
884 /* The pointsize is given in multiples of 6. The pointsize can be enormous:
885  * Clear() renders a single point that fills the entire framebuffer.
886  * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in
887  * 8b precision).
888  */
889 #define R300_GA_POINT_SIZE                   0x421C
890 #       define R300_POINTSIZE_Y_SHIFT         0
891 #       define R300_POINTSIZE_Y_MASK          0x0000ffff
892 #       define R300_POINTSIZE_X_SHIFT         16
893 #       define R300_POINTSIZE_X_MASK          0xffff0000
894 #       define R300_POINTSIZE_MAX             (R300_POINTSIZE_Y_MASK / 6)
895 
896 /* Red fill color */
897 #define R500_GA_FILL_R                                0x4220
898 
899 /* Green fill color */
900 #define R500_GA_FILL_G                                0x4224
901 
902 /* Blue fill color */
903 #define R500_GA_FILL_B                                0x4228
904 
905 /* Alpha fill color */
906 #define R500_GA_FILL_A                                0x422c
907 
908 
909 /* Specifies maximum and minimum point & sprite sizes for per vertex size
910  * specification. The lower part (15:0) is MIN and (31:16) is max.
911  */
912 #define R300_GA_POINT_MINMAX                0x4230
913 #       define R300_GA_POINT_MINMAX_MIN_SHIFT          0
914 #       define R300_GA_POINT_MINMAX_MIN_MASK           (0xFFFF << 0)
915 #       define R300_GA_POINT_MINMAX_MAX_SHIFT          16
916 #       define R300_GA_POINT_MINMAX_MAX_MASK           (0xFFFF << 16)
917 
918 /* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b
919  * subprecision); (16.0) fixed format.
920  *
921  * The line width is given in multiples of 6.
922  * In default mode lines are classified as vertical lines.
923  */
924 #define R300_GA_LINE_CNTL                             0x4234
925 #       define R300_GA_LINE_CNTL_WIDTH_SHIFT       0
926 #       define R300_GA_LINE_CNTL_WIDTH_MASK        0x0000ffff
927 #	define R300_GA_LINE_CNTL_END_TYPE_HOR      (0 << 16)
928 #	define R300_GA_LINE_CNTL_END_TYPE_VER      (1 << 16)
929 #	define R300_GA_LINE_CNTL_END_TYPE_SQR      (2 << 16) /* horizontal or vertical depending upon slope */
930 #	define R300_GA_LINE_CNTL_END_TYPE_COMP     (3 << 16) /* Computed (perpendicular to slope) */
931 #	define R500_GA_LINE_CNTL_SORT_NO           (0 << 18)
932 #	define R500_GA_LINE_CNTL_SORT_MINX_MINY    (1 << 18)
933 
934 /* Line Stipple configuration information. */
935 #define R300_GA_LINE_STIPPLE_CONFIG                   0x4238
936 #	define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO     (0 << 0)
937 #	define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE   (1 << 0)
938 #	define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0)
939 #	define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2
940 #	define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK  0xfffffffc
941 
942 /* Used to load US instructions and constants */
943 #define R500_GA_US_VECTOR_INDEX               0x4250
944 #	define R500_GA_US_VECTOR_INDEX_SHIFT       0
945 #	define R500_GA_US_VECTOR_INDEX_MASK        0x000000ff
946 #	define R500_GA_US_VECTOR_INDEX_TYPE_INSTR  (0 << 16)
947 #	define R500_GA_US_VECTOR_INDEX_TYPE_CONST  (1 << 16)
948 #	define R500_GA_US_VECTOR_INDEX_CLAMP_NO    (0 << 17)
949 #	define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17)
950 
951 /* Data register for loading US instructions and constants */
952 #define R500_GA_US_VECTOR_DATA                0x4254
953 
954 /* Specifies color properties and mappings of textures. */
955 #define R500_GA_COLOR_CONTROL_PS3                     0x4258
956 #	define R500_TEX0_SHADING_PS3_SOLID       (0 << 0)
957 #	define R500_TEX0_SHADING_PS3_FLAT        (1 << 0)
958 #	define R500_TEX0_SHADING_PS3_GOURAUD     (2 << 0)
959 #	define R500_TEX1_SHADING_PS3_SOLID       (0 << 2)
960 #	define R500_TEX1_SHADING_PS3_FLAT        (1 << 2)
961 #	define R500_TEX1_SHADING_PS3_GOURAUD     (2 << 2)
962 #	define R500_TEX2_SHADING_PS3_SOLID       (0 << 4)
963 #	define R500_TEX2_SHADING_PS3_FLAT        (1 << 4)
964 #	define R500_TEX2_SHADING_PS3_GOURAUD     (2 << 4)
965 #	define R500_TEX3_SHADING_PS3_SOLID       (0 << 6)
966 #	define R500_TEX3_SHADING_PS3_FLAT        (1 << 6)
967 #	define R500_TEX3_SHADING_PS3_GOURAUD     (2 << 6)
968 #	define R500_TEX4_SHADING_PS3_SOLID       (0 << 8)
969 #	define R500_TEX4_SHADING_PS3_FLAT        (1 << 8)
970 #	define R500_TEX4_SHADING_PS3_GOURAUD     (2 << 8)
971 #	define R500_TEX5_SHADING_PS3_SOLID       (0 << 10)
972 #	define R500_TEX5_SHADING_PS3_FLAT        (1 << 10)
973 #	define R500_TEX5_SHADING_PS3_GOURAUD     (2 << 10)
974 #	define R500_TEX6_SHADING_PS3_SOLID       (0 << 12)
975 #	define R500_TEX6_SHADING_PS3_FLAT        (1 << 12)
976 #	define R500_TEX6_SHADING_PS3_GOURAUD     (2 << 12)
977 #	define R500_TEX7_SHADING_PS3_SOLID       (0 << 14)
978 #	define R500_TEX7_SHADING_PS3_FLAT        (1 << 14)
979 #	define R500_TEX7_SHADING_PS3_GOURAUD     (2 << 14)
980 #	define R500_TEX8_SHADING_PS3_SOLID       (0 << 16)
981 #	define R500_TEX8_SHADING_PS3_FLAT        (1 << 16)
982 #	define R500_TEX8_SHADING_PS3_GOURAUD     (2 << 16)
983 #	define R500_TEX9_SHADING_PS3_SOLID       (0 << 18)
984 #	define R500_TEX9_SHADING_PS3_FLAT        (1 << 18)
985 #	define R500_TEX9_SHADING_PS3_GOURAUD     (2 << 18)
986 #	define R500_TEX10_SHADING_PS3_SOLID      (0 << 20)
987 #	define R500_TEX10_SHADING_PS3_FLAT       (1 << 20)
988 #	define R500_TEX10_SHADING_PS3_GOURAUD    (2 << 20)
989 #	define R500_COLOR0_TEX_OVERRIDE_NO       (0 << 22)
990 #	define R500_COLOR0_TEX_OVERRIDE_TEX_0    (1 << 22)
991 #	define R500_COLOR0_TEX_OVERRIDE_TEX_1    (2 << 22)
992 #	define R500_COLOR0_TEX_OVERRIDE_TEX_2    (3 << 22)
993 #	define R500_COLOR0_TEX_OVERRIDE_TEX_3    (4 << 22)
994 #	define R500_COLOR0_TEX_OVERRIDE_TEX_4    (5 << 22)
995 #	define R500_COLOR0_TEX_OVERRIDE_TEX_5    (6 << 22)
996 #	define R500_COLOR0_TEX_OVERRIDE_TEX_6    (7 << 22)
997 #	define R500_COLOR0_TEX_OVERRIDE_TEX_7    (8 << 22)
998 #	define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22)
999 #	define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22)
1000 #	define R500_COLOR1_TEX_OVERRIDE_NO       (0 << 26)
1001 #	define R500_COLOR1_TEX_OVERRIDE_TEX_0    (1 << 26)
1002 #	define R500_COLOR1_TEX_OVERRIDE_TEX_1    (2 << 26)
1003 #	define R500_COLOR1_TEX_OVERRIDE_TEX_2    (3 << 26)
1004 #	define R500_COLOR1_TEX_OVERRIDE_TEX_3    (4 << 26)
1005 #	define R500_COLOR1_TEX_OVERRIDE_TEX_4    (5 << 26)
1006 #	define R500_COLOR1_TEX_OVERRIDE_TEX_5    (6 << 26)
1007 #	define R500_COLOR1_TEX_OVERRIDE_TEX_6    (7 << 26)
1008 #	define R500_COLOR1_TEX_OVERRIDE_TEX_7    (8 << 26)
1009 #	define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26)
1010 #	define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26)
1011 
1012 /* Returns idle status of various G3D block, captured when GA_IDLE written or
1013  * when hard or soft reset asserted.
1014  */
1015 #define R500_GA_IDLE                                  0x425c
1016 #	define R500_GA_IDLE_PIPE3_Z_IDLE  (0 << 0)
1017 #	define R500_GA_IDLE_PIPE2_Z_IDLE  (0 << 1)
1018 #	define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2)
1019 #	define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3)
1020 #	define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4)
1021 #	define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5)
1022 #	define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6)
1023 #	define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7)
1024 #	define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8)
1025 #	define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9)
1026 #	define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10)
1027 #	define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11)
1028 #	define R500_GA_IDLE_PIPE1_Z_IDLE  (0 << 12)
1029 #	define R500_GA_IDLE_PIPE0_Z_IDLE  (0 << 13)
1030 #	define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14)
1031 #	define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15)
1032 #	define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16)
1033 #	define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17)
1034 #	define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18)
1035 #	define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19)
1036 #	define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20)
1037 #	define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21)
1038 #	define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22)
1039 #	define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23)
1040 #	define R500_GA_IDLE_SU_IDLE       (0 << 24)
1041 #	define R500_GA_IDLE_GA_IDLE       (0 << 25)
1042 #	define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26)
1043 
1044 /* Current value of stipple accumulator. */
1045 #define R300_GA_LINE_STIPPLE_VALUE            0x4260
1046 
1047 /* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */
1048 #define R300_GA_LINE_S0                               0x4264
1049 /* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */
1050 #define R300_GA_LINE_S1                               0x4268
1051 
1052 /* GA Input fifo high water marks */
1053 #define R500_GA_FIFO_CNTL                             0x4270
1054 #	define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK   0x00000007
1055 #	define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT  0
1056 #	define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK  0x00000038
1057 #	define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3
1058 #	define R500_GA_FIFO_CNTL_VERTEX_REG_MASK    0x00003fc0
1059 #	define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT   6
1060 
1061 /* GA enhance/tweaks */
1062 #define R300_GA_ENHANCE                               0x4274
1063 #	define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT   (0 << 0)
1064 #	define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */
1065 #	define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT   (0 << 1)
1066 #	define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE      (1 << 1) /* Enables high-performance register/primitive switching. */
1067 #	define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT   (0 << 2) /* R520+ only */
1068 #	define R500_GA_ENHANCE_REG_READWRITE_ENABLE      (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */
1069 #	define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT     (0 << 3)
1070 #	define R500_GA_ENHANCE_REG_NOSTALL_ENABLE        (1 << 3) /* Enables GA support of no-stall reads for register read back. */
1071 
1072 #define R300_GA_COLOR_CONTROL                   0x4278
1073 #	define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID      (0 << 0)
1074 #	define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT       (1 << 0)
1075 #	define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD    (2 << 0)
1076 #	define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID    (0 << 2)
1077 #	define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT     (1 << 2)
1078 #	define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD  (2 << 2)
1079 #	define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID      (0 << 4)
1080 #	define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT       (1 << 4)
1081 #	define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD    (2 << 4)
1082 #	define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID    (0 << 6)
1083 #	define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT     (1 << 6)
1084 #	define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD  (2 << 6)
1085 #	define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID      (0 << 8)
1086 #	define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT       (1 << 8)
1087 #	define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD    (2 << 8)
1088 #	define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID    (0 << 10)
1089 #	define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT     (1 << 10)
1090 #	define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD  (2 << 10)
1091 #	define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID      (0 << 12)
1092 #	define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT       (1 << 12)
1093 #	define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD    (2 << 12)
1094 #	define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID    (0 << 14)
1095 #	define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT     (1 << 14)
1096 #	define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD  (2 << 14)
1097 #	define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST  (0 << 16)
1098 #	define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16)
1099 #	define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD  (2 << 16)
1100 #	define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST   (3 << 16)
1101 
1102 #       define R300_SHADE_MODEL_FLAT ( \
1103         R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | \
1104         R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \
1105         R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | \
1106         R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT | \
1107         R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | \
1108         R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \
1109         R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | \
1110         R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT )
1111 
1112 #       define R300_SHADE_MODEL_SMOOTH ( \
1113         R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | \
1114         R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \
1115         R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | \
1116         R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \
1117         R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | \
1118         R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \
1119         R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | \
1120         R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD )
1121 
1122 /* Specifies red & green components of fill color -- S312 format -- Backwards comp. */
1123 #define R300_GA_SOLID_RG                         0x427c
1124 #	define GA_SOLID_RG_COLOR_GREEN_SHIFT 0
1125 #	define GA_SOLID_RG_COLOR_GREEN_MASK  0x0000ffff
1126 #	define GA_SOLID_RG_COLOR_RED_SHIFT   16
1127 #	define GA_SOLID_RG_COLOR_RED_MASK    0xffff0000
1128 /* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */
1129 #define R300_GA_SOLID_BA                         0x4280
1130 #	define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0
1131 #	define GA_SOLID_BA_COLOR_ALPHA_MASK  0x0000ffff
1132 #	define GA_SOLID_BA_COLOR_BLUE_SHIFT  16
1133 #	define GA_SOLID_BA_COLOR_BLUE_MASK   0xffff0000
1134 
1135 /* Polygon Mode
1136  * Dangerous
1137  */
1138 #define R300_GA_POLY_MODE                             0x4288
1139 #	define R300_GA_POLY_MODE_DISABLE           (0 << 0)
1140 #	define R300_GA_POLY_MODE_DUAL              (1 << 0) /* send 2 sets of 3 polys with specified poly type */
1141 /* reserved */
1142 #	define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4)
1143 #	define R300_GA_POLY_MODE_FRONT_PTYPE_LINE  (1 << 4)
1144 #	define R300_GA_POLY_MODE_FRONT_PTYPE_TRI   (2 << 4)
1145 /* reserved */
1146 #	define R300_GA_POLY_MODE_BACK_PTYPE_POINT  (0 << 7)
1147 #	define R300_GA_POLY_MODE_BACK_PTYPE_LINE   (1 << 7)
1148 #	define R300_GA_POLY_MODE_BACK_PTYPE_TRI    (2 << 7)
1149 /* reserved */
1150 
1151 /* Specifies the rouding mode for geometry & color SPFP to FP conversions. */
1152 #define R300_GA_ROUND_MODE                            0x428c
1153 #	define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC   (0 << 0)
1154 #	define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0)
1155 #	define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC      (0 << 2)
1156 #	define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST    (1 << 2)
1157 #	define R300_GA_ROUND_MODE_RGB_CLAMP_RGB          (0 << 4)
1158 #	define R300_GA_ROUND_MODE_RGB_CLAMP_FP20         (1 << 4)
1159 #	define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB        (0 << 5)
1160 #	define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20       (1 << 5)
1161 #	define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT    6
1162 #	define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK     0x000003c0
1163 
1164 /* Specifies x & y offsets for vertex data after conversion to FP.
1165  * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b
1166  * subprecision).
1167  */
1168 #define R300_GA_OFFSET                                0x4290
1169 #	define R300_GA_OFFSET_X_OFFSET_SHIFT 0
1170 #	define R300_GA_OFFSET_X_OFFSET_MASK  0x0000ffff
1171 #	define R300_GA_OFFSET_Y_OFFSET_SHIFT 16
1172 #	define R300_GA_OFFSET_Y_OFFSET_MASK  0xffff0000
1173 
1174 /* Specifies the scale to apply to fog. */
1175 #define R300_GA_FOG_SCALE                     0x4294
1176 /* Specifies the offset to apply to fog. */
1177 #define R300_GA_FOG_OFFSET                    0x4298
1178 /* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */
1179 #define R300_GA_SOFT_RESET                    0x429c
1180 
1181 /* Not sure why there are duplicate of factor and constant values.
1182  * My best guess so far is that there are separate zbiases for test and write.
1183  * Ordering might be wrong.
1184  * Some of the tests indicate that fgl has a fallback implementation of zbias
1185  * via pixel shaders.
1186  */
1187 #define R300_SU_TEX_WRAP                      0x42A0
1188 #define R300_SU_POLY_OFFSET_FRONT_SCALE       0x42A4
1189 #define R300_SU_POLY_OFFSET_FRONT_OFFSET      0x42A8
1190 #define R300_SU_POLY_OFFSET_BACK_SCALE        0x42AC
1191 #define R300_SU_POLY_OFFSET_BACK_OFFSET       0x42B0
1192 
1193 /* This register needs to be set to (1<<1) for RV350 to correctly
1194  * perform depth test (see --vb-triangles in r300_demo)
1195  * Don't know about other chips. - Vladimir
1196  * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.
1197  * My guess is that there are two bits for each zbias primitive
1198  * (FILL, LINE, POINT).
1199  *  One to enable depth test and one for depth write.
1200  * Yet this doesnt explain why depth writes work ...
1201  */
1202 #define R300_SU_POLY_OFFSET_ENABLE	       0x42B4
1203 #	define R300_FRONT_ENABLE	       (1 << 0)
1204 #	define R300_BACK_ENABLE 	       (1 << 1)
1205 #	define R300_PARA_ENABLE 	       (1 << 2)
1206 
1207 #define R300_SU_CULL_MODE                      0x42B8
1208 #       define R300_CULL_FRONT                   (1 << 0)
1209 #       define R300_CULL_BACK                    (1 << 1)
1210 #       define R300_FRONT_FACE_CCW               (0 << 2)
1211 #       define R300_FRONT_FACE_CW                (1 << 2)
1212 
1213 /* SU Depth Scale value */
1214 #define R300_SU_DEPTH_SCALE                 0x42c0
1215 /* SU Depth Offset value */
1216 #define R300_SU_DEPTH_OFFSET                0x42c4
1217 
1218 #define R300_SU_REG_DEST		    0x42c8
1219 #	define R300_RASTER_PIPE_SELECT_0	(1 << 0)
1220 #	define R300_RASTER_PIPE_SELECT_1	(1 << 1)
1221 #	define R300_RASTER_PIPE_SELECT_2	(1 << 2)
1222 #	define R300_RASTER_PIPE_SELECT_3	(1 << 3)
1223 #	define R300_RASTER_PIPE_SELECT_ALL	0xf
1224 
1225 
1226 /* BEGIN: Rasterization / Interpolators - many guesses */
1227 
1228 /*
1229  * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends
1230  * on the vertex program, *not* the fragment program)
1231  */
1232 #define R300_RS_COUNT                      0x4300
1233 #       define R300_IT_COUNT_SHIFT               0
1234 #       define R300_IT_COUNT_MASK                0x0000007f
1235 #       define R300_IC_COUNT_SHIFT               7
1236 #       define R300_IC_COUNT_MASK                0x00000780
1237 #       define R300_W_ADDR_SHIFT                 12
1238 #       define R300_W_ADDR_MASK                  0x0003f000
1239 #       define R300_HIRES_DIS                    (0 << 18)
1240 #       define R300_HIRES_EN                     (1 << 18)
1241 #       define R300_IT_COUNT(x)                  ((x) << 0)
1242 #       define R300_IC_COUNT(x)                  ((x) << 7)
1243 #       define R300_W_COUNT(x)                   ((x) << 12)
1244 
1245 #define R300_RS_INST_COUNT                       0x4304
1246 #       define R300_RS_INST_COUNT_SHIFT          0
1247 #       define R300_RS_INST_COUNT_MASK           0x0000000f
1248 #       define R300_RS_TX_OFFSET_SHIFT           5
1249 #	define R300_RS_TX_OFFSET_MASK            0x000000e0
1250 #       define R300_RS_TX_OFFSET(x)              ((x) << 5)
1251 
1252 /* gap */
1253 
1254 /* Only used for texture coordinates.
1255  * Use the source field to route texture coordinate input from the
1256  * vertex program to the desired interpolator. Note that the source
1257  * field is relative to the outputs the vertex program *actually*
1258  * writes. If a vertex program only writes texcoord[1], this will
1259  * be source index 0.
1260  * Set INTERP_USED on all interpolators that produce data used by
1261  * the fragment program. INTERP_USED looks like a swizzling mask,
1262  * but I haven't seen it used that way.
1263  *
1264  * Note: The _UNKNOWN constants are always set in their respective
1265  * register. I don't know if this is necessary.
1266  */
1267 #define R300_RS_IP_0				        0x4310
1268 #define R300_RS_IP_1				        0x4314
1269 #define R300_RS_IP_2				        0x4318
1270 #define R300_RS_IP_3				        0x431C
1271 #	define R300_RS_TEX_PTR(x)		        (x << 0)
1272 #	define R300_RS_COL_PTR(x)		        ((x) << 6)
1273 #	define R300_RS_COL_FMT(x)		        ((x) << 9)
1274 #	define R300_RS_COL_FMT_RGBA		        0
1275 #	define R300_RS_COL_FMT_RGB0		        1
1276 #	define R300_RS_COL_FMT_RGB1		        2
1277 #	define R300_RS_COL_FMT_000A		        4
1278 #	define R300_RS_COL_FMT_0000		        5
1279 #	define R300_RS_COL_FMT_0001		        6
1280 #	define R300_RS_COL_FMT_111A		        8
1281 #	define R300_RS_COL_FMT_1110		        9
1282 #	define R300_RS_COL_FMT_1111		        10
1283 #	define R300_RS_SEL_S(x)		                ((x) << 13)
1284 #	define R300_RS_SEL_T(x)		                ((x) << 16)
1285 #	define R300_RS_SEL_R(x)		                ((x) << 19)
1286 #	define R300_RS_SEL_Q(x)		                ((x) << 22)
1287 #	define R300_RS_SEL_C0		                0
1288 #	define R300_RS_SEL_C1		                1
1289 #	define R300_RS_SEL_C2		                2
1290 #	define R300_RS_SEL_C3		                3
1291 #	define R300_RS_SEL_K0		                4
1292 #	define R300_RS_SEL_K1		                5
1293 
1294 
1295 /*  */
1296 #define R500_RS_INST_0					0x4320
1297 #define R500_RS_INST_1					0x4324
1298 #define R500_RS_INST_2					0x4328
1299 #define R500_RS_INST_3					0x432c
1300 #define R500_RS_INST_4					0x4330
1301 #define R500_RS_INST_5					0x4334
1302 #define R500_RS_INST_6					0x4338
1303 #define R500_RS_INST_7					0x433c
1304 #define R500_RS_INST_8					0x4340
1305 #define R500_RS_INST_9					0x4344
1306 #define R500_RS_INST_10					0x4348
1307 #define R500_RS_INST_11					0x434c
1308 #define R500_RS_INST_12					0x4350
1309 #define R500_RS_INST_13					0x4354
1310 #define R500_RS_INST_14					0x4358
1311 #define R500_RS_INST_15					0x435c
1312 #define R500_RS_INST_TEX_ID_SHIFT			0
1313 #        define R500_RS_INST_TEX_ID(x)                  ((x) << 0)
1314 #define R500_RS_INST_TEX_CN_WRITE			(1 << 4)
1315 #define R500_RS_INST_TEX_ADDR_SHIFT			5
1316 #        define R500_RS_INST_TEX_ADDR(x)                ((x) << 5)
1317 #define R500_RS_INST_COL_ID_SHIFT			12
1318 #        define R500_RS_INST_COL_ID(x)                  ((x) << 12)
1319 #define R500_RS_INST_COL_CN_NO_WRITE			(0 << 16)
1320 #define R500_RS_INST_COL_CN_WRITE			(1 << 16)
1321 #define R500_RS_INST_COL_CN_WRITE_FBUFFER		(2 << 16)
1322 #define R500_RS_INST_COL_CN_WRITE_BACKFACE		(3 << 16)
1323 #define R500_RS_INST_COL_ADDR_SHIFT			18
1324 #        define R500_RS_INST_COL_ADDR(x)                ((x) << 18)
1325 #define R500_RS_INST_TEX_ADJ				(1 << 25)
1326 #define R500_RS_INST_W_CN				(1 << 26)
1327 
1328 /* These DWORDs control how vertex data is routed into fragment program
1329  * registers, after interpolators.
1330  */
1331 #define R300_RS_INST_0                     0x4330
1332 #define R300_RS_INST_1                     0x4334
1333 #define R300_RS_INST_2                     0x4338
1334 #define R300_RS_INST_3                     0x433C
1335 #define R300_RS_INST_4                     0x4340
1336 #define R300_RS_INST_5                     0x4344
1337 #define R300_RS_INST_6                     0x4348
1338 #define R300_RS_INST_7                     0x434C
1339 #	define R300_RS_INST_TEX_ID(x)  		((x) << 0)
1340 #	define R300_RS_INST_TEX_CN_WRITE 	(1 << 3)
1341 #	define R300_RS_INST_TEX_ADDR(x)		((x) << 6)
1342 #	define R300_RS_INST_TEX_ADDR_SHIFT 	6
1343 #	define R300_RS_INST_COL_ID(x)		((x) << 11)
1344 #	define R300_RS_INST_COL_CN_WRITE	(1 << 14)
1345 #	define R300_RS_INST_COL_ADDR(x)		((x) << 17)
1346 #	define R300_RS_INST_COL_ADDR_SHIFT	17
1347 #	define R300_RS_INST_TEX_ADJ		(1 << 22)
1348 #	define R300_RS_COL_BIAS_UNUSED_SHIFT    23
1349 
1350 /* END: Rasterization / Interpolators - many guesses */
1351 
1352 /* Hierarchical Z Enable */
1353 #define R300_SC_HYPERZ                   0x43a4
1354 #	define R300_SC_HYPERZ_DISABLE     (0 << 0)
1355 #	define R300_SC_HYPERZ_ENABLE      (1 << 0)
1356 #	define R300_SC_HYPERZ_MIN         (0 << 1)
1357 #	define R300_SC_HYPERZ_MAX         (1 << 1)
1358 #	define R300_SC_HYPERZ_ADJ_256     (0 << 2)
1359 #	define R300_SC_HYPERZ_ADJ_128     (1 << 2)
1360 #	define R300_SC_HYPERZ_ADJ_64      (2 << 2)
1361 #	define R300_SC_HYPERZ_ADJ_32      (3 << 2)
1362 #	define R300_SC_HYPERZ_ADJ_16      (4 << 2)
1363 #	define R300_SC_HYPERZ_ADJ_8       (5 << 2)
1364 #	define R300_SC_HYPERZ_ADJ_4       (6 << 2)
1365 #	define R300_SC_HYPERZ_ADJ_2       (7 << 2)
1366 #	define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
1367 #	define R300_SC_HYPERZ_HZ_Z0MIN    (1 << 5)
1368 #	define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
1369 #	define R300_SC_HYPERZ_HZ_Z0MAX    (1 << 6)
1370 
1371 #define R300_SC_EDGERULE                 0x43a8
1372 
1373 /* BEGIN: Scissors and cliprects */
1374 
1375 /* There are four clipping rectangles. Their corner coordinates are inclusive.
1376  * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
1377  * on whether the pixel is inside cliprects 0-3, respectively. For example,
1378  * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
1379  * the number 3 (binary 0011).
1380  * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,
1381  * the pixel is rasterized.
1382  *
1383  * In addition to this, there is a scissors rectangle. Only pixels inside the
1384  * scissors rectangle are drawn. (coordinates are inclusive)
1385  *
1386  * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
1387  * for the purpose of clipping and scissors.
1388  */
1389 #define R300_SC_CLIPRECT_TL_0               0x43B0
1390 #define R300_SC_CLIPRECT_BR_0               0x43B4
1391 #define R300_SC_CLIPRECT_TL_1               0x43B8
1392 #define R300_SC_CLIPRECT_BR_1               0x43BC
1393 #define R300_SC_CLIPRECT_TL_2               0x43C0
1394 #define R300_SC_CLIPRECT_BR_2               0x43C4
1395 #define R300_SC_CLIPRECT_TL_3               0x43C8
1396 #define R300_SC_CLIPRECT_BR_3               0x43CC
1397 #       define R300_CLIPRECT_OFFSET              1440
1398 #       define R300_CLIPRECT_MASK                0x1FFF
1399 #       define R300_CLIPRECT_X_SHIFT             0
1400 #       define R300_CLIPRECT_X_MASK              (0x1FFF << 0)
1401 #       define R300_CLIPRECT_Y_SHIFT             13
1402 #       define R300_CLIPRECT_Y_MASK              (0x1FFF << 13)
1403 #define R300_SC_CLIP_RULE                   0x43D0
1404 #       define R300_CLIP_OUT                     (1 << 0)
1405 #       define R300_CLIP_0                       (1 << 1)
1406 #       define R300_CLIP_1                       (1 << 2)
1407 #       define R300_CLIP_10                      (1 << 3)
1408 #       define R300_CLIP_2                       (1 << 4)
1409 #       define R300_CLIP_20                      (1 << 5)
1410 #       define R300_CLIP_21                      (1 << 6)
1411 #       define R300_CLIP_210                     (1 << 7)
1412 #       define R300_CLIP_3                       (1 << 8)
1413 #       define R300_CLIP_30                      (1 << 9)
1414 #       define R300_CLIP_31                      (1 << 10)
1415 #       define R300_CLIP_310                     (1 << 11)
1416 #       define R300_CLIP_32                      (1 << 12)
1417 #       define R300_CLIP_320                     (1 << 13)
1418 #       define R300_CLIP_321                     (1 << 14)
1419 #       define R300_CLIP_3210                    (1 << 15)
1420 
1421 /* gap */
1422 
1423 #define R300_SC_SCISSORS_TL                 0x43E0
1424 #define R300_SC_SCISSORS_BR                 0x43E4
1425 #       define R300_SCISSORS_OFFSET              1440
1426 #       define R300_SCISSORS_X_SHIFT             0
1427 #       define R300_SCISSORS_X_MASK              (0x1FFF << 0)
1428 #       define R300_SCISSORS_Y_SHIFT             13
1429 #       define R300_SCISSORS_Y_MASK              (0x1FFF << 13)
1430 
1431 /* Screen door sample mask */
1432 #define R300_SC_SCREENDOOR                 0x43e8
1433 
1434 /* END: Scissors and cliprects */
1435 
1436 /* BEGIN: Texture specification */
1437 
1438 /*
1439  * The texture specification dwords are grouped by meaning and not by texture
1440  * unit. This means that e.g. the offset for texture image unit N is found in
1441  * register TX_OFFSET_0 + (4*N)
1442  */
1443 #define R300_TX_FILTER0_0                        0x4400
1444 #define R300_TX_FILTER0_1                        0x4404
1445 #define R300_TX_FILTER0_2                        0x4408
1446 #define R300_TX_FILTER0_3                        0x440c
1447 #define R300_TX_FILTER0_4                        0x4410
1448 #define R300_TX_FILTER0_5                        0x4414
1449 #define R300_TX_FILTER0_6                        0x4418
1450 #define R300_TX_FILTER0_7                        0x441c
1451 #define R300_TX_FILTER0_8                        0x4420
1452 #define R300_TX_FILTER0_9                        0x4424
1453 #define R300_TX_FILTER0_10                       0x4428
1454 #define R300_TX_FILTER0_11                       0x442c
1455 #define R300_TX_FILTER0_12                       0x4430
1456 #define R300_TX_FILTER0_13                       0x4434
1457 #define R300_TX_FILTER0_14                       0x4438
1458 #define R300_TX_FILTER0_15                       0x443c
1459 #       define R300_TX_REPEAT                    0
1460 #       define R300_TX_MIRRORED                  1
1461 #       define R300_TX_CLAMP_TO_EDGE             2
1462 #	define R300_TX_MIRROR_ONCE_TO_EDGE       3
1463 #       define R300_TX_CLAMP                     4
1464 #	define R300_TX_MIRROR_ONCE               5
1465 #       define R300_TX_CLAMP_TO_BORDER           6
1466 #	define R300_TX_MIRROR_ONCE_TO_BORDER     7
1467 #       define R300_TX_WRAP_S_SHIFT              0
1468 #       define R300_TX_WRAP_S_MASK               (7 << 0)
1469 #       define R300_TX_WRAP_T_SHIFT              3
1470 #       define R300_TX_WRAP_T_MASK               (7 << 3)
1471 #       define R300_TX_WRAP_R_SHIFT              6
1472 #       define R300_TX_WRAP_R_MASK               (7 << 6)
1473 #	define R300_TX_MAG_FILTER_4              (0 << 9)
1474 #       define R300_TX_MAG_FILTER_NEAREST        (1 << 9)
1475 #       define R300_TX_MAG_FILTER_LINEAR         (2 << 9)
1476 #       define R300_TX_MAG_FILTER_ANISO          (3 << 9)
1477 #       define R300_TX_MAG_FILTER_MASK           (3 << 9)
1478 #       define R300_TX_MIN_FILTER_NEAREST        (1 << 11)
1479 #       define R300_TX_MIN_FILTER_LINEAR         (2 << 11)
1480 #	define R300_TX_MIN_FILTER_ANISO          (3 << 11)
1481 #	define R300_TX_MIN_FILTER_MASK           (3 << 11)
1482 #	define R300_TX_MIN_FILTER_MIP_NONE       (0 << 13)
1483 #	define R300_TX_MIN_FILTER_MIP_NEAREST    (1 << 13)
1484 #	define R300_TX_MIN_FILTER_MIP_LINEAR     (2 << 13)
1485 #	define R300_TX_MIN_FILTER_MIP_MASK       (3 << 13)
1486 #       define R300_TX_MAX_MIP_LEVEL_SHIFT       17
1487 #       define R300_TX_MAX_MIP_LEVEL_MASK        (0xf << 17)
1488 #	define R300_TX_MAX_ANISO_1_TO_1          (0 << 21)
1489 #	define R300_TX_MAX_ANISO_2_TO_1          (1 << 21)
1490 #	define R300_TX_MAX_ANISO_4_TO_1          (2 << 21)
1491 #	define R300_TX_MAX_ANISO_8_TO_1          (3 << 21)
1492 #	define R300_TX_MAX_ANISO_16_TO_1         (4 << 21)
1493 #	define R300_TX_MAX_ANISO_MASK            (7 << 21)
1494 #       define R300_TX_WRAP_S(x)                 ((x) << 0)
1495 #       define R300_TX_WRAP_T(x)                 ((x) << 3)
1496 #       define R300_TX_MAX_MIP_LEVEL(x)          ((x) << 17)
1497 
1498 #define R300_TX_FILTER1_0                      0x4440
1499 #	define R300_CHROMA_KEY_MODE_DISABLE    0
1500 #	define R300_CHROMA_KEY_FORCE	       1
1501 #	define R300_CHROMA_KEY_BLEND           2
1502 #	define R300_MC_ROUND_NORMAL            (0<<2)
1503 #	define R300_MC_ROUND_MPEG4             (1<<2)
1504 #	define R300_LOD_BIAS_SHIFT             3
1505 #	define R300_LOD_BIAS_MASK	       0x1ff8
1506 #	define R300_EDGE_ANISO_EDGE_DIAG       (0<<13)
1507 #	define R300_EDGE_ANISO_EDGE_ONLY       (1<<13)
1508 #	define R300_MC_COORD_TRUNCATE_DISABLE  (0<<14)
1509 #	define R300_MC_COORD_TRUNCATE_MPEG     (1<<14)
1510 #	define R300_TX_TRI_PERF_0_8            (0<<15)
1511 #	define R300_TX_TRI_PERF_1_8            (1<<15)
1512 #	define R300_TX_TRI_PERF_1_4            (2<<15)
1513 #	define R300_TX_TRI_PERF_3_8            (3<<15)
1514 #	define R300_ANISO_THRESHOLD_MASK       (7<<17)
1515 
1516 #       define R400_DXTC_SWIZZLE_ENABLE        (1<<21)
1517 #	define R500_MACRO_SWITCH               (1<<22)
1518 #       define R500_TX_MAX_ANISO(x)            ((x) << 23)
1519 #       define R500_TX_MAX_ANISO_MASK          (63 << 23)
1520 #       define R500_TX_ANISO_HIGH_QUALITY      (1 << 30)
1521 #	define R500_BORDER_FIX                 (1<<31)
1522 
1523 #define R300_TX_FORMAT0_0                   0x4480
1524 #       define R300_TX_WIDTHMASK_SHIFT           0
1525 #       define R300_TX_WIDTHMASK_MASK            (2047 << 0)
1526 #       define R300_TX_HEIGHTMASK_SHIFT          11
1527 #       define R300_TX_HEIGHTMASK_MASK           (2047 << 11)
1528 #	define R300_TX_DEPTHMASK_SHIFT           22
1529 #	define R300_TX_DEPTHMASK_MASK            (0xf << 22)
1530 #       define R300_TX_SIZE_PROJECTED            (1 << 30)
1531 #       define R300_TX_PITCH_EN                  (1 << 31)
1532 #       define R300_TX_WIDTH(x)                  ((x) << 0)
1533 #       define R300_TX_HEIGHT(x)                 ((x) << 11)
1534 #       define R300_TX_DEPTH(x)                  ((x) << 22)
1535 #       define R300_TX_NUM_LEVELS(x)             ((x) << 26)
1536 
1537 #define R300_TX_FORMAT1_0                   0x44C0
1538 	/* The interpretation of the format word by Wladimir van der Laan */
1539 	/* The X, Y, Z and W refer to the layout of the components.
1540 	   They are given meanings as R, G, B and Alpha by the swizzle
1541 	   specification */
1542 #	define R300_TX_FORMAT_X8		    0x0
1543 #	define R300_TX_FORMAT_X16		    0x1
1544 #	define R300_TX_FORMAT_Y4X4		    0x2
1545 #	define R300_TX_FORMAT_Y8X8		    0x3
1546 #	define R300_TX_FORMAT_Y16X16		    0x4
1547 #	define R300_TX_FORMAT_Z3Y3X2		    0x5
1548 #	define R300_TX_FORMAT_Z5Y6X5		    0x6
1549 #	define R300_TX_FORMAT_Z6Y5X5		    0x7
1550 #	define R300_TX_FORMAT_Z11Y11X10		    0x8
1551 #	define R300_TX_FORMAT_Z10Y11X11		    0x9
1552 #	define R300_TX_FORMAT_W4Z4Y4X4		    0xA
1553 #	define R300_TX_FORMAT_W1Z5Y5X5		    0xB
1554 #	define R300_TX_FORMAT_W8Z8Y8X8		    0xC
1555 #	define R300_TX_FORMAT_W2Z10Y10X10	    0xD
1556 #	define R300_TX_FORMAT_W16Z16Y16X16	    0xE
1557 #	define R300_TX_FORMAT_DXT1	    	    0xF
1558 #	define R300_TX_FORMAT_DXT3	    	    0x10
1559 #	define R300_TX_FORMAT_DXT5	    	    0x11
1560 #	define R300_TX_FORMAT_CxV8U8           	    0x12
1561 #	define R300_TX_FORMAT_AVYU444 	    	    0x13
1562 #	define R300_TX_FORMAT_VYUY422  	    	    0x14
1563 #	define R300_TX_FORMAT_YVYU422  	    	    0x15
1564 #	define R300_TX_FORMAT_16_MPEG  	    	    0x16
1565 #	define R300_TX_FORMAT_16_16_MPEG    	    0x17
1566 #	define R300_TX_FORMAT_16F     	    	    0x18
1567 #	define R300_TX_FORMAT_16F_16F 	    	    0x19
1568 #	define R300_TX_FORMAT_16F_16F_16F_16F  	    0x1A
1569 #	define R300_TX_FORMAT_32F     	    	    0x1B
1570 #	define R300_TX_FORMAT_32F_32F 	    	    0x1C
1571 #	define R300_TX_FORMAT_32F_32F_32F_32F  	    0x1D
1572 #       define R300_TX_FORMAT_W24_FP                0x1E
1573 #       define R400_TX_FORMAT_ATI2N                 0x1F
1574 
1575 /* These need TX_FORMAT2_[0-15].TXFORMAT_MSB set.
1576 
1577    My guess is the 10-bit formats are the 8-bit ones but with filtering being
1578    performed with the precision of 10 bits per channel. This makes sense
1579    with sRGB textures since the conversion to linear space reduces the precision
1580    significantly so the shader gets approximately the 8-bit precision
1581    in the end. It might also improve the quality of HDR rendering where
1582    high-precision filtering is desirable.
1583 
1584    Again, this is guessed, the formats might mean something entirely else.
1585    The others should be fine. */
1586 #       define R500_TX_FORMAT_X1                    0x0
1587 #       define R500_TX_FORMAT_X1_REV                0x1
1588 #       define R500_TX_FORMAT_X10                   0x2
1589 #       define R500_TX_FORMAT_Y10X10                0x3
1590 #       define R500_TX_FORMAT_W10Z10Y10X10          0x4
1591 #       define R500_TX_FORMAT_ATI1N                 0x5
1592 #       define R500_TX_FORMAT_Y8X24                 0x6
1593 
1594 
1595 #       define R300_TX_FORMAT_SIGNED_W             (1 << 5)
1596 #       define R300_TX_FORMAT_SIGNED_Z             (1 << 6)
1597 #       define R300_TX_FORMAT_SIGNED_Y             (1 << 7)
1598 #       define R300_TX_FORMAT_SIGNED_X             (1 << 8)
1599 #       define R300_TX_FORMAT_SIGNED               (0xf << 5)
1600 
1601 #	define R300_TX_FORMAT_3D		   (1 << 25)
1602 #	define R300_TX_FORMAT_CUBIC_MAP		   (2 << 25)
1603 #	define R300_TX_FORMAT_TEX_COORD_TYPE_MASK  (0x3 << 25)
1604 
1605 	/* alpha modes, convenience mostly */
1606 	/* if you have alpha, pick constant appropriate to the
1607 	   number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
1608 # 	define R300_TX_FORMAT_ALPHA_1CH		    0x000
1609 # 	define R300_TX_FORMAT_ALPHA_2CH		    0x200
1610 # 	define R300_TX_FORMAT_ALPHA_4CH		    0x600
1611 # 	define R300_TX_FORMAT_ALPHA_NONE	    0xA00
1612 	/* Swizzling */
1613 	/* constants */
1614 #	define R300_TX_FORMAT_X		0
1615 #	define R300_TX_FORMAT_Y		1
1616 #	define R300_TX_FORMAT_Z		2
1617 #	define R300_TX_FORMAT_W		3
1618 #	define R300_TX_FORMAT_ZERO	4
1619 #	define R300_TX_FORMAT_ONE	5
1620 	/* 2.0*Z, everything above 1.0 is set to 0.0 */
1621 #	define R300_TX_FORMAT_CUT_Z	6
1622 	/* 2.0*W, everything above 1.0 is set to 0.0 */
1623 #	define R300_TX_FORMAT_CUT_W	7
1624 
1625 #	define R300_TX_FORMAT_B_SHIFT	18
1626 #	define R300_TX_FORMAT_G_SHIFT	15
1627 #	define R300_TX_FORMAT_R_SHIFT	12
1628 #	define R300_TX_FORMAT_A_SHIFT	9
1629 	/* Convenience macro to take care of layout and swizzling */
1630 #	define R300_EASY_TX_FORMAT(B, G, R, A, FMT)	(		\
1631 		((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT)		\
1632 		| ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT)	\
1633 		| ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT)	\
1634 		| ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT)	\
1635 		| (R300_TX_FORMAT_##FMT)				\
1636 		)
1637 	/* These can be ORed with result of R300_EASY_TX_FORMAT()
1638 	   We don't really know what they do. Take values from a
1639            constant color ? */
1640 #	define R300_TX_FORMAT_CONST_X		(1<<5)
1641 #	define R300_TX_FORMAT_CONST_Y		(2<<5)
1642 #	define R300_TX_FORMAT_CONST_Z		(4<<5)
1643 #	define R300_TX_FORMAT_CONST_W		(8<<5)
1644 
1645 #       define R300_TX_FORMAT_GAMMA               (1 << 21)
1646 #       define R300_TX_FORMAT_YUV_TO_RGB          (1 << 22)
1647 
1648 #       define R300_TX_CACHE(x)                 ((x) << 27)
1649 #       define R300_TX_CACHE_WHOLE              0
1650 /* reserved */
1651 #       define R300_TX_CACHE_HALF_0             2
1652 #       define R300_TX_CACHE_HALF_1             3
1653 #       define R300_TX_CACHE_FOURTH_0           4
1654 #       define R300_TX_CACHE_FOURTH_1           5
1655 #       define R300_TX_CACHE_FOURTH_2           6
1656 #       define R300_TX_CACHE_FOURTH_3           7
1657 #       define R300_TX_CACHE_EIGHTH_0           8
1658 #       define R300_TX_CACHE_EIGHTH_1           9
1659 #       define R300_TX_CACHE_EIGHTH_2           10
1660 #       define R300_TX_CACHE_EIGHTH_3           11
1661 #       define R300_TX_CACHE_EIGHTH_4           12
1662 #       define R300_TX_CACHE_EIGHTH_5           13
1663 #       define R300_TX_CACHE_EIGHTH_6           14
1664 #       define R300_TX_CACHE_EIGHTH_7           15
1665 #       define R300_TX_CACHE_SIXTEENTH_0        16
1666 #       define R300_TX_CACHE_SIXTEENTH_1        17
1667 #       define R300_TX_CACHE_SIXTEENTH_2        18
1668 #       define R300_TX_CACHE_SIXTEENTH_3        19
1669 #       define R300_TX_CACHE_SIXTEENTH_4        20
1670 #       define R300_TX_CACHE_SIXTEENTH_5        21
1671 #       define R300_TX_CACHE_SIXTEENTH_6        22
1672 #       define R300_TX_CACHE_SIXTEENTH_7        23
1673 #       define R300_TX_CACHE_SIXTEENTH_8        24
1674 #       define R300_TX_CACHE_SIXTEENTH_9        25
1675 #       define R300_TX_CACHE_SIXTEENTH_10       26
1676 #       define R300_TX_CACHE_SIXTEENTH_11       27
1677 #       define R300_TX_CACHE_SIXTEENTH_12       28
1678 #       define R300_TX_CACHE_SIXTEENTH_13       29
1679 #       define R300_TX_CACHE_SIXTEENTH_14       30
1680 #       define R300_TX_CACHE_SIXTEENTH_15       31
1681 
1682 #define R300_TX_FORMAT2_0		    0x4500 /* obvious missing in gap */
1683 #       define R300_TX_PITCHMASK_SHIFT           0
1684 #       define R300_TX_PITCHMASK_MASK            (2047 << 0)
1685 #	define R500_TXFORMAT_MSB		 (1 << 14)
1686 #	define R500_TXWIDTH_BIT11	         (1 << 15)
1687 #	define R500_TXHEIGHT_BIT11	         (1 << 16)
1688 #	define R500_POW2FIX2FLT			 (1 << 17)
1689 #	define R500_SEL_FILTER4_TC0		 (0 << 18)
1690 #	define R500_SEL_FILTER4_TC1		 (1 << 18)
1691 #	define R500_SEL_FILTER4_TC2		 (2 << 18)
1692 #	define R500_SEL_FILTER4_TC3		 (3 << 18)
1693 
1694 #define R300_TX_OFFSET_0                    0x4540
1695 #define R300_TX_OFFSET_1                    0x4544
1696 #define R300_TX_OFFSET_2                    0x4548
1697 #define R300_TX_OFFSET_3                    0x454C
1698 #define R300_TX_OFFSET_4                    0x4550
1699 #define R300_TX_OFFSET_5                    0x4554
1700 #define R300_TX_OFFSET_6                    0x4558
1701 #define R300_TX_OFFSET_7                    0x455C
1702 
1703 #       define R300_TXO_ENDIAN(x)                ((x) << 0)
1704 #       define R300_TXO_MACRO_TILE_LINEAR        (0 << 2)
1705 #       define R300_TXO_MACRO_TILE_TILED         (1 << 2)
1706 #       define R300_TXO_MACRO_TILE(x)            ((x) << 2)
1707 #       define R300_TXO_MICRO_TILE_LINEAR        (0 << 3)
1708 #       define R300_TXO_MICRO_TILE_TILED         (1 << 3)
1709 #       define R300_TXO_MICRO_TILE_TILED_SQUARE  (2 << 3)
1710 #       define R300_TXO_MICRO_TILE(x)            ((x) << 3)
1711 #       define R300_TXO_OFFSET_MASK              0xffffffe0
1712 #       define R300_TXO_OFFSET_SHIFT             5
1713 
1714 /* 32 bit chroma key */
1715 #define R300_TX_CHROMA_KEY_0                      0x4580
1716 #define R300_TX_CHROMA_KEY_1                      0x4584
1717 #define R300_TX_CHROMA_KEY_2                      0x4588
1718 #define R300_TX_CHROMA_KEY_3                      0x458c
1719 #define R300_TX_CHROMA_KEY_4                      0x4590
1720 #define R300_TX_CHROMA_KEY_5                      0x4594
1721 #define R300_TX_CHROMA_KEY_6                      0x4598
1722 #define R300_TX_CHROMA_KEY_7                      0x459c
1723 #define R300_TX_CHROMA_KEY_8                      0x45a0
1724 #define R300_TX_CHROMA_KEY_9                      0x45a4
1725 #define R300_TX_CHROMA_KEY_10                     0x45a8
1726 #define R300_TX_CHROMA_KEY_11                     0x45ac
1727 #define R300_TX_CHROMA_KEY_12                     0x45b0
1728 #define R300_TX_CHROMA_KEY_13                     0x45b4
1729 #define R300_TX_CHROMA_KEY_14                     0x45b8
1730 #define R300_TX_CHROMA_KEY_15                     0x45bc
1731 /* ff00ff00 == { 0, 1.0, 0, 1.0 } */
1732 
1733 /* Border Color */
1734 #define R300_TX_BORDER_COLOR_0              0x45c0
1735 #define R300_TX_BORDER_COLOR_1              0x45c4
1736 #define R300_TX_BORDER_COLOR_2              0x45c8
1737 #define R300_TX_BORDER_COLOR_3              0x45cc
1738 #define R300_TX_BORDER_COLOR_4              0x45d0
1739 #define R300_TX_BORDER_COLOR_5              0x45d4
1740 #define R300_TX_BORDER_COLOR_6              0x45d8
1741 #define R300_TX_BORDER_COLOR_7              0x45dc
1742 #define R300_TX_BORDER_COLOR_8              0x45e0
1743 #define R300_TX_BORDER_COLOR_9              0x45e4
1744 #define R300_TX_BORDER_COLOR_10             0x45e8
1745 #define R300_TX_BORDER_COLOR_11             0x45ec
1746 #define R300_TX_BORDER_COLOR_12             0x45f0
1747 #define R300_TX_BORDER_COLOR_13             0x45f4
1748 #define R300_TX_BORDER_COLOR_14             0x45f8
1749 #define R300_TX_BORDER_COLOR_15             0x45fc
1750 
1751 
1752 /* END: Texture specification */
1753 
1754 /* BEGIN: Fragment program instruction set */
1755 
1756 /* Fragment programs are written directly into register space.
1757  * There are separate instruction streams for texture instructions and ALU
1758  * instructions.
1759  * In order to synchronize these streams, the program is divided into up
1760  * to 4 nodes. Each node begins with a number of TEX operations, followed
1761  * by a number of ALU operations.
1762  * The first node can have zero TEX ops, all subsequent nodes must have at
1763  * least
1764  * one TEX ops.
1765  * All nodes must have at least one ALU op.
1766  *
1767  * The index of the last node is stored in PFS_CNTL_0: A value of 0 means
1768  * 1 node, a value of 3 means 4 nodes.
1769  * The total amount of instructions is defined in PFS_CNTL_2. The offsets are
1770  * offsets into the respective instruction streams, while *_END points to the
1771  * last instruction relative to this offset.
1772  */
1773 #define R300_US_CONFIG                      0x4600
1774 #       define R300_PFS_CNTL_LAST_NODES_SHIFT    0
1775 #       define R300_PFS_CNTL_LAST_NODES_MASK     (3 << 0)
1776 #       define R300_PFS_CNTL_FIRST_NODE_HAS_TEX  (1 << 3)
1777 #define R300_US_PIXSIZE                     0x4604
1778 /* There is an unshifted value here which has so far always been equal to the
1779  * index of the highest used temporary register.
1780  */
1781 #define R300_US_CODE_OFFSET                 0x4608
1782 #       define R300_PFS_CNTL_ALU_OFFSET_SHIFT    0
1783 #       define R300_PFS_CNTL_ALU_OFFSET_MASK     (63 << 0)
1784 #       define R300_PFS_CNTL_ALU_END_SHIFT       6
1785 #       define R300_PFS_CNTL_ALU_END_MASK        (63 << 6)
1786 #       define R300_PFS_CNTL_TEX_OFFSET_SHIFT    13
1787 #       define R300_PFS_CNTL_TEX_OFFSET_MASK     (31 << 13)
1788 #       define R300_PFS_CNTL_TEX_END_SHIFT       18
1789 #       define R300_PFS_CNTL_TEX_END_MASK        (31 << 18)
1790 #       define R400_PFS_CNTL_TEX_OFFSET_MSB_SHIFT 24
1791 #       define R400_PFS_CNTL_TEX_OFFSET_MSB_MASK (0xf << 24)
1792 #       define R400_PFS_CNTL_TEX_END_MSB_SHIFT   28
1793 #       define R400_PFS_CNTL_TEX_END_MSB_MASK    (0xf << 28)
1794 
1795 /* gap */
1796 
1797 /* Nodes are stored backwards. The last active node is always stored in
1798  * PFS_NODE_3.
1799  * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
1800  * first node is stored in NODE_2, the second node is stored in NODE_3.
1801  *
1802  * Offsets are relative to the master offset from PFS_CNTL_2.
1803  */
1804 #define R300_US_CODE_ADDR_0                 0x4610
1805 #define R300_US_CODE_ADDR_1                 0x4614
1806 #define R300_US_CODE_ADDR_2                 0x4618
1807 #define R300_US_CODE_ADDR_3                 0x461C
1808 #       define R300_ALU_START_SHIFT         0
1809 #       define R300_ALU_START_MASK          (63 << 0)
1810 #       define R300_ALU_SIZE_SHIFT          6
1811 #       define R300_ALU_SIZE_MASK           (63 << 6)
1812 #       define R300_TEX_START_SHIFT         12
1813 #       define R300_TEX_START_MASK          (31 << 12)
1814 #       define R300_TEX_SIZE_SHIFT          17
1815 #       define R300_TEX_SIZE_MASK           (31 << 17)
1816 #	define R300_RGBA_OUT                (1 << 22)
1817 #	define R300_W_OUT                   (1 << 23)
1818 #       define R400_TEX_START_MSB_SHIFT     24
1819 #       define R400_TEX_START_MSG_MASK      (0xf << 24)
1820 #       define R400_TEX_SIZE_MSB_SHIFT      28
1821 #       define R400_TEX_SIZE_MSG_MASK       (0xf << 28)
1822 
1823 /* TEX
1824  * As far as I can tell, texture instructions cannot write into output
1825  * registers directly. A subsequent ALU instruction is always necessary,
1826  * even if it's just MAD o0, r0, 1, 0
1827  */
1828 #define R300_US_TEX_INST_0                  0x4620
1829 #	define R300_SRC_ADDR_SHIFT          0
1830 #	define R300_SRC_ADDR_MASK           (31 << 0)
1831 #	define R300_DST_ADDR_SHIFT          6
1832 #	define R300_DST_ADDR_MASK           (31 << 6)
1833 #	define R300_TEX_ID_SHIFT            11
1834 #       define R300_TEX_ID_MASK             (15 << 11)
1835 #	define R300_TEX_INST_SHIFT		15
1836 #		define R300_TEX_OP_NOP	        0
1837 #		define R300_TEX_OP_LD	        1
1838 #		define R300_TEX_OP_KIL	        2
1839 #		define R300_TEX_OP_TXP	        3
1840 #		define R300_TEX_OP_TXB	        4
1841 #	define R300_TEX_INST_MASK               (7 << 15)
1842 #      define R400_SRC_ADDR_EXT_BIT         (1 << 19)
1843 #      define R400_DST_ADDR_EXT_BIT         (1 << 20)
1844 
1845 /* Output format from the unfied shader */
1846 #define R300_US_OUT_FMT_0                   0x46A4
1847 #	define R300_US_OUT_FMT_C4_8         (0 << 0)
1848 #	define R300_US_OUT_FMT_C4_10        (1 << 0)
1849 #	define R300_US_OUT_FMT_C4_10_GAMMA  (2 << 0)
1850 #	define R300_US_OUT_FMT_C_16         (3 << 0)
1851 #	define R300_US_OUT_FMT_C2_16        (4 << 0)
1852 #	define R300_US_OUT_FMT_C4_16        (5 << 0)
1853 #	define R300_US_OUT_FMT_C_16_MPEG    (6 << 0)
1854 #	define R300_US_OUT_FMT_C2_16_MPEG   (7 << 0)
1855 #	define R300_US_OUT_FMT_C2_4         (8 << 0)
1856 #	define R300_US_OUT_FMT_C_3_3_2      (9 << 0)
1857 #	define R300_US_OUT_FMT_C_6_5_6      (10 << 0)
1858 #	define R300_US_OUT_FMT_C_11_11_10   (11 << 0)
1859 #	define R300_US_OUT_FMT_C_10_11_11   (12 << 0)
1860 #	define R300_US_OUT_FMT_C_2_10_10_10 (13 << 0)
1861 /* reserved */
1862 #	define R300_US_OUT_FMT_UNUSED       (15 << 0)
1863 #	define R300_US_OUT_FMT_C_16_FP      (16 << 0)
1864 #	define R300_US_OUT_FMT_C2_16_FP     (17 << 0)
1865 #	define R300_US_OUT_FMT_C4_16_FP     (18 << 0)
1866 #	define R300_US_OUT_FMT_C_32_FP      (19 << 0)
1867 #	define R300_US_OUT_FMT_C2_32_FP     (20 << 0)
1868 #	define R300_US_OUT_FMT_C4_32_FP     (21 << 0)
1869 #   define R300_C0_SEL_A				(0 << 8)
1870 #   define R300_C0_SEL_R				(1 << 8)
1871 #   define R300_C0_SEL_G				(2 << 8)
1872 #   define R300_C0_SEL_B				(3 << 8)
1873 #   define R300_C1_SEL_A				(0 << 10)
1874 #   define R300_C1_SEL_R				(1 << 10)
1875 #   define R300_C1_SEL_G				(2 << 10)
1876 #   define R300_C1_SEL_B				(3 << 10)
1877 #   define R300_C2_SEL_A				(0 << 12)
1878 #   define R300_C2_SEL_R				(1 << 12)
1879 #   define R300_C2_SEL_G				(2 << 12)
1880 #   define R300_C2_SEL_B				(3 << 12)
1881 #   define R300_C3_SEL_A				(0 << 14)
1882 #   define R300_C3_SEL_R				(1 << 14)
1883 #   define R300_C3_SEL_G				(2 << 14)
1884 #   define R300_C3_SEL_B				(3 << 14)
1885 #   define R300_OUT_SIGN(x)				((x) << 16)
1886 #   define R500_ROUND_ADJ				(1 << 20)
1887 
1888 /* ALU
1889  * The ALU instructions register blocks are enumerated according to the order
1890  * in which fglrx. I assume there is space for 64 instructions, since
1891  * each block has space for a maximum of 64 DWORDs, and this matches reported
1892  * native limits.
1893  *
1894  * The basic functional block seems to be one MAD for each color and alpha,
1895  * and an adder that adds all components after the MUL.
1896  *  - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
1897  *  - DP4: Use OUTC_DP4, OUTA_DP4
1898  *  - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
1899  *  - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
1900  *  - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
1901  *  - CMP: If ARG2 < 0, return ARG1, else return ARG0
1902  *  - FLR: use FRC+MAD
1903  *  - XPD: use MAD+MAD
1904  *  - SGE, SLT: use MAD+CMP
1905  *  - RSQ: use ABS modifier for argument
1906  *  - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
1907  *    (e.g. RCP) into color register
1908  *  - apparently, there's no quick DST operation
1909  *  - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
1910  *  - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
1911  *  - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
1912  *
1913  * Operand selection
1914  * First stage selects three sources from the available registers and
1915  * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).
1916  * fglrx sorts the three source fields: Registers before constants,
1917  * lower indices before higher indices; I do not know whether this is
1918  * necessary.
1919  *
1920  * fglrx fills unused sources with "read constant 0"
1921  * According to specs, you cannot select more than two different constants.
1922  *
1923  * Second stage selects the operands from the sources. This is defined in
1924  * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants
1925  * zero and one.
1926  * Swizzling and negation happens in this stage, as well.
1927  *
1928  * Important: Color and alpha seem to be mostly separate, i.e. their sources
1929  * selection appears to be fully independent (the register storage is probably
1930  * physically split into a color and an alpha section).
1931  * However (because of the apparent physical split), there is some interaction
1932  * WRT swizzling. If, for example, you want to load an R component into an
1933  * Alpha operand, this R component is taken from a *color* source, not from
1934  * an alpha source. The corresponding register doesn't even have to appear in
1935  * the alpha sources list. (I hope this all makes sense to you)
1936  *
1937  * Destination selection
1938  * The destination register index is in FPI1 (color) and FPI3 (alpha)
1939  * together with enable bits.
1940  * There are separate enable bits for writing into temporary registers
1941  * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*
1942  * /DSTA_OUTPUT). You can write to both at once, or not write at all (the
1943  * same index must be used for both).
1944  *
1945  * Note: There is a special form for LRP
1946  *  - Argument order is the same as in ARB_fragment_program.
1947  *  - Operation is MAD
1948  *  - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1949  *  - Set FPI0/FPI2_SPECIAL_LRP
1950  * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD
1951  */
1952 #define R300_US_ALU_RGB_ADDR_0                   0x46C0
1953 #       define R300_ALU_SRC0C_SHIFT             0
1954 #       define R300_ALU_SRC0C_MASK              (31 << 0)
1955 #       define R300_ALU_SRC0C_CONST             (1 << 5)
1956 #       define R300_ALU_SRC1C_SHIFT             6
1957 #       define R300_ALU_SRC1C_MASK              (31 << 6)
1958 #       define R300_ALU_SRC1C_CONST             (1 << 11)
1959 #       define R300_ALU_SRC2C_SHIFT             12
1960 #       define R300_ALU_SRC2C_MASK              (31 << 12)
1961 #       define R300_ALU_SRC2C_CONST             (1 << 17)
1962 #       define R300_ALU_SRC_MASK                0x0003ffff
1963 #       define R300_ALU_DSTC_SHIFT              18
1964 #       define R300_ALU_DSTC_MASK               (31 << 18)
1965 #		define R300_ALU_DSTC_REG_MASK_SHIFT     23
1966 #       define R300_ALU_DSTC_REG_X              (1 << 23)
1967 #       define R300_ALU_DSTC_REG_Y              (1 << 24)
1968 #       define R300_ALU_DSTC_REG_Z              (1 << 25)
1969 #		define R300_ALU_DSTC_OUTPUT_MASK_SHIFT  26
1970 #       define R300_ALU_DSTC_OUTPUT_X           (1 << 26)
1971 #       define R300_ALU_DSTC_OUTPUT_Y           (1 << 27)
1972 #       define R300_ALU_DSTC_OUTPUT_Z           (1 << 28)
1973 #       define R300_ALU_DSTC_OUTPUT_XYZ         (7 << 26)
1974 #       define R300_RGB_ADDR0(x)                ((x) << 0)
1975 #       define R300_RGB_ADDR1(x)                ((x) << 6)
1976 #       define R300_RGB_ADDR2(x)                ((x) << 12)
1977 #       define R300_RGB_TARGET(x)               ((x) << 29)
1978 
1979 #define R300_US_ALU_ALPHA_ADDR_0                 0x47C0
1980 #       define R300_ALU_SRC0A_SHIFT             0
1981 #       define R300_ALU_SRC0A_MASK              (31 << 0)
1982 #       define R300_ALU_SRC0A_CONST             (1 << 5)
1983 #       define R300_ALU_SRC1A_SHIFT             6
1984 #       define R300_ALU_SRC1A_MASK              (31 << 6)
1985 #       define R300_ALU_SRC1A_CONST             (1 << 11)
1986 #       define R300_ALU_SRC2A_SHIFT             12
1987 #       define R300_ALU_SRC2A_MASK              (31 << 12)
1988 #       define R300_ALU_SRC2A_CONST             (1 << 17)
1989 #       define R300_ALU_SRC_MASK                0x0003ffff
1990 #       define R300_ALU_DSTA_SHIFT              18
1991 #       define R300_ALU_DSTA_MASK               (31 << 18)
1992 #       define R300_ALU_DSTA_REG                (1 << 23)
1993 #       define R300_ALU_DSTA_OUTPUT             (1 << 24)
1994 #		define R300_ALU_DSTA_DEPTH              (1 << 27)
1995 #       define R300_ALPHA_ADDR0(x)              ((x) << 0)
1996 #       define R300_ALPHA_ADDR1(x)              ((x) << 6)
1997 #       define R300_ALPHA_ADDR2(x)              ((x) << 12)
1998 #       define R300_ALPHA_TARGET(x)             ((x) << 25)
1999 
2000 #define R300_US_ALU_RGB_INST_0                   0x48C0
2001 #       define R300_ALU_ARGC_SRC0C_XYZ          0
2002 #       define R300_ALU_ARGC_SRC0C_XXX          1
2003 #       define R300_ALU_ARGC_SRC0C_YYY          2
2004 #       define R300_ALU_ARGC_SRC0C_ZZZ          3
2005 #       define R300_ALU_ARGC_SRC1C_XYZ          4
2006 #       define R300_ALU_ARGC_SRC1C_XXX          5
2007 #       define R300_ALU_ARGC_SRC1C_YYY          6
2008 #       define R300_ALU_ARGC_SRC1C_ZZZ          7
2009 #       define R300_ALU_ARGC_SRC2C_XYZ          8
2010 #       define R300_ALU_ARGC_SRC2C_XXX          9
2011 #       define R300_ALU_ARGC_SRC2C_YYY          10
2012 #       define R300_ALU_ARGC_SRC2C_ZZZ          11
2013 #       define R300_ALU_ARGC_SRC0A              12
2014 #       define R300_ALU_ARGC_SRC1A              13
2015 #       define R300_ALU_ARGC_SRC2A              14
2016 #       define R300_ALU_ARGC_SRCP_XYZ           15
2017 #       define R300_ALU_ARGC_SRCP_XXX           16
2018 #       define R300_ALU_ARGC_SRCP_YYY           17
2019 #       define R300_ALU_ARGC_SRCP_ZZZ           18
2020 #       define R300_ALU_ARGC_SRCP_WWW           19
2021 #       define R300_ALU_ARGC_ZERO               20
2022 #       define R300_ALU_ARGC_ONE                21
2023 #       define R300_ALU_ARGC_HALF               22
2024 #       define R300_ALU_ARGC_SRC0C_YZX          23
2025 #       define R300_ALU_ARGC_SRC1C_YZX          24
2026 #       define R300_ALU_ARGC_SRC2C_YZX          25
2027 #       define R300_ALU_ARGC_SRC0C_ZXY          26
2028 #       define R300_ALU_ARGC_SRC1C_ZXY          27
2029 #       define R300_ALU_ARGC_SRC2C_ZXY          28
2030 #       define R300_ALU_ARGC_SRC0CA_WZY         29
2031 #       define R300_ALU_ARGC_SRC1CA_WZY         30
2032 #       define R300_ALU_ARGC_SRC2CA_WZY         31
2033 #       define R300_RGB_SWIZA(x)                ((x) << 0)
2034 #       define R300_RGB_SWIZB(x)                ((x) << 7)
2035 #       define R300_RGB_SWIZC(x)                ((x) << 14)
2036 
2037 #       define R300_ALU_ARG0C_SHIFT             0
2038 #       define R300_ALU_ARG0C_MASK              (31 << 0)
2039 #       define R300_ALU_ARG0C_NOP               (0 << 5)
2040 #       define R300_ALU_ARG0C_NEG               (1 << 5)
2041 #       define R300_ALU_ARG0C_ABS               (2 << 5)
2042 #       define R300_ALU_ARG0C_NAB               (3 << 5)
2043 #       define R300_ALU_ARG1C_SHIFT             7
2044 #       define R300_ALU_ARG1C_MASK              (31 << 7)
2045 #       define R300_ALU_ARG1C_NOP               (0 << 12)
2046 #       define R300_ALU_ARG1C_NEG               (1 << 12)
2047 #       define R300_ALU_ARG1C_ABS               (2 << 12)
2048 #       define R300_ALU_ARG1C_NAB               (3 << 12)
2049 #       define R300_ALU_ARG2C_SHIFT             14
2050 #       define R300_ALU_ARG2C_MASK              (31 << 14)
2051 #       define R300_ALU_ARG2C_NOP               (0 << 19)
2052 #       define R300_ALU_ARG2C_NEG               (1 << 19)
2053 #       define R300_ALU_ARG2C_ABS               (2 << 19)
2054 #       define R300_ALU_ARG2C_NAB               (3 << 19)
2055 #       define R300_ALU_SRCP_1_MINUS_2_SRC0     (0 << 21)
2056 #       define R300_ALU_SRCP_SRC1_MINUS_SRC0    (1 << 21)
2057 #       define R300_ALU_SRCP_SRC1_PLUS_SRC0     (2 << 21)
2058 #       define R300_ALU_SRCP_1_MINUS_SRC0       (3 << 21)
2059 
2060 #       define R300_ALU_OUTC_MAD                (0 << 23)
2061 #       define R300_ALU_OUTC_DP3                (1 << 23)
2062 #       define R300_ALU_OUTC_DP4                (2 << 23)
2063 #       define R300_ALU_OUTC_D2A                (3 << 23)
2064 #       define R300_ALU_OUTC_MIN                (4 << 23)
2065 #       define R300_ALU_OUTC_MAX                (5 << 23)
2066 #       define R300_ALU_OUTC_CND                (7 << 23)
2067 #       define R300_ALU_OUTC_CMP                (8 << 23)
2068 #       define R300_ALU_OUTC_FRC                (9 << 23)
2069 #       define R300_ALU_OUTC_REPL_ALPHA         (10 << 23)
2070 
2071 #	define R300_ALU_OUTC_MOD_SHIFT		27
2072 #       define R300_ALU_OUTC_MOD_NOP            (0 << R300_ALU_OUTC_MOD_SHIFT)
2073 #       define R300_ALU_OUTC_MOD_MUL2           (1 << R300_ALU_OUTC_MOD_SHIFT)
2074 #       define R300_ALU_OUTC_MOD_MUL4           (2 << R300_ALU_OUTC_MOD_SHIFT)
2075 #       define R300_ALU_OUTC_MOD_MUL8           (3 << R300_ALU_OUTC_MOD_SHIFT)
2076 #       define R300_ALU_OUTC_MOD_DIV2           (4 << R300_ALU_OUTC_MOD_SHIFT)
2077 #       define R300_ALU_OUTC_MOD_DIV4           (5 << R300_ALU_OUTC_MOD_SHIFT)
2078 #       define R300_ALU_OUTC_MOD_DIV8           (6 << R300_ALU_OUTC_MOD_SHIFT)
2079 
2080 #       define R300_ALU_OUTC_CLAMP              (1 << 30)
2081 #       define R300_ALU_INSERT_NOP              (1 << 31)
2082 
2083 #define R300_US_ALU_ALPHA_INST_0                 0x49C0
2084 #       define R300_ALU_ARGA_SRC0C_X            0
2085 #       define R300_ALU_ARGA_SRC0C_Y            1
2086 #       define R300_ALU_ARGA_SRC0C_Z            2
2087 #       define R300_ALU_ARGA_SRC1C_X            3
2088 #       define R300_ALU_ARGA_SRC1C_Y            4
2089 #       define R300_ALU_ARGA_SRC1C_Z            5
2090 #       define R300_ALU_ARGA_SRC2C_X            6
2091 #       define R300_ALU_ARGA_SRC2C_Y            7
2092 #       define R300_ALU_ARGA_SRC2C_Z            8
2093 #       define R300_ALU_ARGA_SRC0A              9
2094 #       define R300_ALU_ARGA_SRC1A              10
2095 #       define R300_ALU_ARGA_SRC2A              11
2096 #       define R300_ALU_ARGA_SRCP_X             12
2097 #       define R300_ALU_ARGA_SRCP_Y             13
2098 #       define R300_ALU_ARGA_SRCP_Z             14
2099 #       define R300_ALU_ARGA_SRCP_W             15
2100 #       define R300_ALU_ARGA_ZERO               16
2101 #       define R300_ALU_ARGA_ONE                17
2102 #       define R300_ALU_ARGA_HALF               18
2103 #       define R300_ALPHA_SWIZA(x)              ((x) << 0)
2104 #       define R300_ALPHA_SWIZB(x)              ((x) << 7)
2105 #       define R300_ALPHA_SWIZC(x)              ((x) << 14)
2106 
2107 #       define R300_ALU_ARG0A_SHIFT             0
2108 #       define R300_ALU_ARG0A_MASK              (31 << 0)
2109 #       define R300_ALU_ARG0A_NOP               (0 << 5)
2110 #       define R300_ALU_ARG0A_NEG               (1 << 5)
2111 #	define R300_ALU_ARG0A_ABS		 (2 << 5)
2112 #	define R300_ALU_ARG0A_NAB		 (3 << 5)
2113 #       define R300_ALU_ARG1A_SHIFT             7
2114 #       define R300_ALU_ARG1A_MASK              (31 << 7)
2115 #       define R300_ALU_ARG1A_NOP               (0 << 12)
2116 #       define R300_ALU_ARG1A_NEG               (1 << 12)
2117 #	define R300_ALU_ARG1A_ABS		 (2 << 12)
2118 #	define R300_ALU_ARG1A_NAB		 (3 << 12)
2119 #       define R300_ALU_ARG2A_SHIFT             14
2120 #       define R300_ALU_ARG2A_MASK              (31 << 14)
2121 #       define R300_ALU_ARG2A_NOP               (0 << 19)
2122 #       define R300_ALU_ARG2A_NEG               (1 << 19)
2123 #	define R300_ALU_ARG2A_ABS		 (2 << 19)
2124 #	define R300_ALU_ARG2A_NAB		 (3 << 19)
2125 #       define R300_ALU_SRCP_1_MINUS_2_SRC0     (0 << 21)
2126 #       define R300_ALU_SRCP_SRC1_MINUS_SRC0    (1 << 21)
2127 #       define R300_ALU_SRCP_SRC1_PLUS_SRC0     (2 << 21)
2128 #       define R300_ALU_SRCP_1_MINUS_SRC0       (3 << 21)
2129 
2130 #       define R300_ALU_OUTA_MAD                (0 << 23)
2131 #       define R300_ALU_OUTA_DP4                (1 << 23)
2132 #       define R300_ALU_OUTA_MIN                (2 << 23)
2133 #       define R300_ALU_OUTA_MAX                (3 << 23)
2134 #       define R300_ALU_OUTA_CND                (5 << 23)
2135 #       define R300_ALU_OUTA_CMP                (6 << 23)
2136 #       define R300_ALU_OUTA_FRC                (7 << 23)
2137 #       define R300_ALU_OUTA_EX2                (8 << 23)
2138 #       define R300_ALU_OUTA_LG2                (9 << 23)
2139 #       define R300_ALU_OUTA_RCP                (10 << 23)
2140 #       define R300_ALU_OUTA_RSQ                (11 << 23)
2141 
2142 #       define R300_ALU_OUTA_MOD_NOP            (0 << 27)
2143 #       define R300_ALU_OUTA_MOD_MUL2           (1 << 27)
2144 #       define R300_ALU_OUTA_MOD_MUL4           (2 << 27)
2145 #       define R300_ALU_OUTA_MOD_MUL8           (3 << 27)
2146 #       define R300_ALU_OUTA_MOD_DIV2           (4 << 27)
2147 #       define R300_ALU_OUTA_MOD_DIV4           (5 << 27)
2148 #       define R300_ALU_OUTA_MOD_DIV8           (6 << 27)
2149 
2150 #       define R300_ALU_OUTA_CLAMP              (1 << 30)
2151 /* END: Fragment program instruction set */
2152 
2153 /* R4xx extended fragment shader registers. */
2154 #define R400_US_ALU_EXT_ADDR_0              0x4ac0 /* up to 63 (0x4bbc) */
2155 #   define R400_ADDR_EXT_RGB_MSB_BIT(x)     (1 << (x))
2156 #   define R400_ADDRD_EXT_RGB_MSB_BIT       0x08
2157 #   define R400_ADDR_EXT_A_MSB_BIT(x)       (1 << ((x) + 4))
2158 #   define R400_ADDRD_EXT_A_MSB_BIT         0x80
2159 
2160 #define R400_US_CODE_BANK                   0x46b8
2161 #   define R400_BANK_SHIFT                  0
2162 #   define R400_BANK_MASK                   0xf
2163 #   define R400_R390_MODE_ENABLE            (1 << 4)
2164 #define R400_US_CODE_EXT                    0x46bc
2165 #   define R400_ALU_OFFSET_MSB_SHIFT        0
2166 #   define R400_ALU_OFFSET_MSB_MASK         (0x7 << 0)
2167 #   define R400_ALU_SIZE_MSB_SHIFT          3
2168 #   define R400_ALU_SIZE_MSB_MASK           (0x7 << 3)
2169 #   define R400_ALU_START0_MSB_SHIFT        6
2170 #   define R400_ALU_START0_MSB_MASK         (0x7 << 6)
2171 #   define R400_ALU_SIZE0_MSB_SHIFT         9
2172 #   define R400_ALU_SIZE0_MSB_MASK          (0x7 << 9)
2173 #   define R400_ALU_START1_MSB_SHIFT        12
2174 #   define R400_ALU_START1_MSB_MASK         (0x7 << 12)
2175 #   define R400_ALU_SIZE1_MSB_SHIFT         15
2176 #   define R400_ALU_SIZE1_MSB_MASK          (0x7 << 15)
2177 #   define R400_ALU_START2_MSB_SHIFT        18
2178 #   define R400_ALU_START2_MSB_MASK         (0x7 << 18)
2179 #   define R400_ALU_SIZE2_MSB_SHIFT         21
2180 #   define R400_ALU_SIZE2_MSB_MASK          (0x7 << 21)
2181 #   define R400_ALU_START3_MSB_SHIFT        24
2182 #   define R400_ALU_START3_MSB_MASK         (0x7 << 24)
2183 #   define R400_ALU_SIZE3_MSB_SHIFT         27
2184 #   define R400_ALU_SIZE3_MSB_MASK          (0x7 << 27)
2185 /* END: R4xx extended fragment shader registers. */
2186 
2187 /* Fog: Fog Blending Enable */
2188 #define R300_FG_FOG_BLEND                             0x4bc0
2189 #       define R300_FG_FOG_BLEND_DISABLE              (0 << 0)
2190 #       define R300_FG_FOG_BLEND_ENABLE               (1 << 0)
2191 #	define R300_FG_FOG_BLEND_FN_LINEAR            (0 << 1)
2192 #	define R300_FG_FOG_BLEND_FN_EXP               (1 << 1)
2193 #	define R300_FG_FOG_BLEND_FN_EXP2              (2 << 1)
2194 #	define R300_FG_FOG_BLEND_FN_CONSTANT          (3 << 1)
2195 #	define R300_FG_FOG_BLEND_FN_MASK              (3 << 1)
2196 
2197 /* Fog: Red Component of Fog Color */
2198 #define R300_FG_FOG_COLOR_R                           0x4bc8
2199 /* Fog: Green Component of Fog Color */
2200 #define R300_FG_FOG_COLOR_G                           0x4bcc
2201 /* Fog: Blue Component of Fog Color */
2202 #define R300_FG_FOG_COLOR_B                           0x4bd0
2203 #	define R300_FG_FOG_COLOR_MASK 0x000003ff
2204 
2205 /* Fog: Constant Factor for Fog Blending */
2206 #define R300_FG_FOG_FACTOR                            0x4bc4
2207 #	define FG_FOG_FACTOR_MASK 0x000003ff
2208 
2209 /* Fog: Alpha function */
2210 #define R300_FG_ALPHA_FUNC                            0x4bd4
2211 #       define R300_FG_ALPHA_FUNC_VAL_MASK               0x000000ff
2212 #       define R300_FG_ALPHA_FUNC_NEVER                     (0 << 8)
2213 #       define R300_FG_ALPHA_FUNC_LESS                      (1 << 8)
2214 #       define R300_FG_ALPHA_FUNC_EQUAL                     (2 << 8)
2215 #       define R300_FG_ALPHA_FUNC_LE                        (3 << 8)
2216 #       define R300_FG_ALPHA_FUNC_GREATER                   (4 << 8)
2217 #       define R300_FG_ALPHA_FUNC_NOTEQUAL                  (5 << 8)
2218 #       define R300_FG_ALPHA_FUNC_GE                        (6 << 8)
2219 #       define R300_FG_ALPHA_FUNC_ALWAYS                    (7 << 8)
2220 #       define R300_ALPHA_TEST_OP_MASK                      (7 << 8)
2221 #       define R300_FG_ALPHA_FUNC_DISABLE                   (0 << 11)
2222 #       define R300_FG_ALPHA_FUNC_ENABLE                    (1 << 11)
2223 
2224 #       define R500_FG_ALPHA_FUNC_10BIT                     (0 << 12)
2225 #       define R500_FG_ALPHA_FUNC_8BIT                      (1 << 12)
2226 
2227 #       define R300_FG_ALPHA_FUNC_MASK_DISABLE              (0 << 16)
2228 #       define R300_FG_ALPHA_FUNC_MASK_ENABLE               (1 << 16)
2229 #       define R300_FG_ALPHA_FUNC_CFG_2_OF_4                (0 << 17)
2230 #       define R300_FG_ALPHA_FUNC_CFG_3_OF_6                (1 << 17)
2231 
2232 #       define R300_FG_ALPHA_FUNC_DITH_DISABLE              (0 << 20)
2233 #       define R300_FG_ALPHA_FUNC_DITH_ENABLE               (1 << 20)
2234 
2235 #       define R500_FG_ALPHA_FUNC_OFFSET_DISABLE            (0 << 24)
2236 #       define R500_FG_ALPHA_FUNC_OFFSET_ENABLE             (1 << 24) /* Not supported in R520 */
2237 #       define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE    (0 << 25)
2238 #       define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE     (1 << 25)
2239 
2240 #       define R500_FG_ALPHA_FUNC_FP16_DISABLE              (0 << 28)
2241 #       define R500_FG_ALPHA_FUNC_FP16_ENABLE               (1 << 28)
2242 
2243 
2244 /* Fog: Where does the depth come from? */
2245 #define R300_FG_DEPTH_SRC                  0x4bd8
2246 #	define R300_FG_DEPTH_SRC_SCAN   (0 << 0)
2247 #	define R300_FG_DEPTH_SRC_SHADER (1 << 0)
2248 
2249 /* Fog: Alpha Compare Value */
2250 #define R500_FG_ALPHA_VALUE                0x4be0
2251 #	define R500_FG_ALPHA_VALUE_MASK 0x0000ffff
2252 
2253 #define RV530_FG_ZBREG_DEST                 0x4be8
2254 #	define RV530_FG_ZBREG_DEST_PIPE_SELECT_0             (1 << 0)
2255 #	define RV530_FG_ZBREG_DEST_PIPE_SELECT_1             (1 << 1)
2256 #	define RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL           (3 << 0)
2257 /* gap */
2258 
2259 /* Fragment program parameters in 7.16 floating point */
2260 #define R300_PFS_PARAM_0_X                  0x4C00
2261 #define R300_PFS_PARAM_0_Y                  0x4C04
2262 #define R300_PFS_PARAM_0_Z                  0x4C08
2263 #define R300_PFS_PARAM_0_W                  0x4C0C
2264 /* last consts */
2265 #define R300_PFS_PARAM_31_X                 0x4DF0
2266 #define R300_PFS_PARAM_31_Y                 0x4DF4
2267 #define R300_PFS_PARAM_31_Z                 0x4DF8
2268 #define R300_PFS_PARAM_31_W                 0x4DFC
2269 
2270 /* Unpipelined. */
2271 #define R300_RB3D_CCTL                      0x4e00
2272 #	define R300_RB3D_CCTL_NUM_MULTIWRITES(x)       (MAX2(((x)-1), 0) << 5)
2273 #	define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER                (0 << 5)
2274 #	define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS               (1 << 5)
2275 #	define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS               (2 << 5)
2276 #	define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS               (3 << 5)
2277 #	define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE                    (0 << 7)
2278 #	define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE                     (1 << 7)
2279 #	define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE                  (0 << 9)
2280 #	define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE                   (1 << 9)
2281 #	define R300_RB3D_CCTL_CMASK_DISABLE                           (0 << 10)
2282 #	define R300_RB3D_CCTL_CMASK_ENABLE                            (1 << 10)
2283 /* reserved */
2284 #	define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE  (0 << 12)
2285 #	define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE   (1 << 12)
2286 #	define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE                (0 << 13)
2287 #	define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE               (1 << 13)
2288 #	define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE  (0 << 14)
2289 #	define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE   (1 << 14)
2290 
2291 
2292 /* Notes:
2293  * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
2294  *   the application
2295  * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
2296  *    are set to the same
2297  *   function (both registers are always set up completely in any case)
2298  * - Most blend flags are simply copied from R200 and not tested yet
2299  */
2300 #define R300_RB3D_CBLEND                    0x4E04
2301 #define R300_RB3D_ABLEND                    0x4E08
2302 /* the following only appear in CBLEND */
2303 #       define R300_ALPHA_BLEND_ENABLE         (1 << 0)
2304 #       define R300_SEPARATE_ALPHA_ENABLE      (1 << 1)
2305 #       define R300_READ_ENABLE                (1 << 2)
2306 #       define R300_DISCARD_SRC_PIXELS_DIS     (0 << 3)
2307 #       define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0     (1 << 3)
2308 #       define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0     (2 << 3)
2309 #       define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0     (3 << 3)
2310 #       define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1     (4 << 3)
2311 #       define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1     (5 << 3)
2312 #       define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1     (6 << 3)
2313 #       define R500_SRC_ALPHA_0_NO_READ                (1 << 30)
2314 #       define R500_SRC_ALPHA_1_NO_READ                (1 << 31)
2315 
2316 /* the following are shared between CBLEND and ABLEND */
2317 #       define R300_FCN_MASK                         (3  << 12)
2318 #       define R300_COMB_FCN_ADD_CLAMP               (0  << 12)
2319 #       define R300_COMB_FCN_ADD_NOCLAMP             (1  << 12)
2320 #       define R300_COMB_FCN_SUB_CLAMP               (2  << 12)
2321 #       define R300_COMB_FCN_SUB_NOCLAMP             (3  << 12)
2322 #       define R300_COMB_FCN_MIN                     (4  << 12)
2323 #       define R300_COMB_FCN_MAX                     (5  << 12)
2324 #       define R300_COMB_FCN_RSUB_CLAMP              (6  << 12)
2325 #       define R300_COMB_FCN_RSUB_NOCLAMP            (7  << 12)
2326 #       define R300_BLEND_GL_ZERO                    (32)
2327 #       define R300_BLEND_GL_ONE                     (33)
2328 #       define R300_BLEND_GL_SRC_COLOR               (34)
2329 #       define R300_BLEND_GL_ONE_MINUS_SRC_COLOR     (35)
2330 #       define R300_BLEND_GL_DST_COLOR               (36)
2331 #       define R300_BLEND_GL_ONE_MINUS_DST_COLOR     (37)
2332 #       define R300_BLEND_GL_SRC_ALPHA               (38)
2333 #       define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA     (39)
2334 #       define R300_BLEND_GL_DST_ALPHA               (40)
2335 #       define R300_BLEND_GL_ONE_MINUS_DST_ALPHA     (41)
2336 #       define R300_BLEND_GL_SRC_ALPHA_SATURATE      (42)
2337 #       define R300_BLEND_GL_CONST_COLOR             (43)
2338 #       define R300_BLEND_GL_ONE_MINUS_CONST_COLOR   (44)
2339 #       define R300_BLEND_GL_CONST_ALPHA             (45)
2340 #       define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA   (46)
2341 #       define R300_BLEND_MASK                       (63)
2342 #       define R300_SRC_BLEND_SHIFT                  (16)
2343 #       define R300_DST_BLEND_SHIFT                  (24)
2344 
2345 /* Constant color used by the blender. Pipelined through the blender.
2346  * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE,
2347  * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead.
2348  */
2349 #define R300_RB3D_BLEND_COLOR               0x4E10
2350 
2351 
2352 /* 3D Color Channel Mask. If all the channels used in the current color format
2353  * are disabled, then the cb will discard all the incoming quads. Pipelined
2354  * through the blender.
2355  */
2356 #define RB3D_COLOR_CHANNEL_MASK                  0x4E0C
2357 #	define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0  (1 << 0)
2358 #	define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1)
2359 #	define RB3D_COLOR_CHANNEL_MASK_RED_MASK0   (1 << 2)
2360 #	define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3)
2361 #	define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1  (1 << 4)
2362 #	define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5)
2363 #	define RB3D_COLOR_CHANNEL_MASK_RED_MASK1   (1 << 6)
2364 #	define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7)
2365 #	define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2  (1 << 8)
2366 #	define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9)
2367 #	define RB3D_COLOR_CHANNEL_MASK_RED_MASK2   (1 << 10)
2368 #	define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11)
2369 #	define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3  (1 << 12)
2370 #	define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13)
2371 #	define RB3D_COLOR_CHANNEL_MASK_RED_MASK3   (1 << 14)
2372 #	define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15)
2373 
2374 /* Clear color that is used when the color mask is set to 00. Unpipelined.
2375  * Program this register with a 32-bit value in ARGB8888 or ARGB2101010
2376  * formats, ignoring the fields.
2377  */
2378 #define R300_RB3D_COLOR_CLEAR_VALUE                   0x4E14
2379 /* For FP16 AA. */
2380 #define R500_RB3D_COLOR_CLEAR_VALUE_AR                0x46C0
2381 #define R500_RB3D_COLOR_CLEAR_VALUE_GB                0x46C4
2382 
2383 /* gap */
2384 
2385 /* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */
2386 #define RB3D_CLRCMP_CLR                     0x4e20
2387 
2388 /* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */
2389 #define RB3D_CLRCMP_MSK                     0x4e24
2390 
2391 /* Color Buffer Address Offset of multibuffer 0. Unpipelined. */
2392 #define R300_RB3D_COLOROFFSET0              0x4E28
2393 #       define R300_COLOROFFSET_MASK             0xFFFFFFE0
2394 /* Color Buffer Address Offset of multibuffer 1. Unpipelined. */
2395 #define R300_RB3D_COLOROFFSET1              0x4E2C
2396 /* Color Buffer Address Offset of multibuffer 2. Unpipelined. */
2397 #define R300_RB3D_COLOROFFSET2              0x4E30
2398 /* Color Buffer Address Offset of multibuffer 3. Unpipelined. */
2399 #define R300_RB3D_COLOROFFSET3              0x4E34
2400 
2401 /* Color buffer format and tiling control for all the multibuffers and the
2402  * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any
2403  * of the registers are changed.
2404  *
2405  * Bit 16: Larger tiles
2406  * Bit 17: 4x2 tiles
2407  * Bit 18: Extremely weird tile like, but some pixels duplicated?
2408  */
2409 #define R300_RB3D_COLORPITCH0               0x4E38
2410 #       define R300_COLORPITCH_MASK              0x00003FFE
2411 #       define R300_COLOR_TILE_DISABLE            (0 << 16)
2412 #       define R300_COLOR_TILE_ENABLE             (1 << 16)
2413 #       define R300_COLOR_TILE(x)                 ((x) << 16)
2414 #       define R300_COLOR_MICROTILE_DISABLE       (0 << 17)
2415 #       define R300_COLOR_MICROTILE_ENABLE        (1 << 17)
2416 #       define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */
2417 #       define R300_COLOR_MICROTILE(x)            ((x) << 17)
2418 #       define R300_COLOR_ENDIAN(x)               ((x) << 19)
2419 #	define R500_COLOR_FORMAT_ARGB10101010     (0 << 21)
2420 #	define R500_COLOR_FORMAT_UV1010           (1 << 21)
2421 #	define R500_COLOR_FORMAT_CI8              (2 << 21) /* 2D only */
2422 #	define R300_COLOR_FORMAT_ARGB1555         (3 << 21)
2423 #       define R300_COLOR_FORMAT_RGB565           (4 << 21)
2424 #       define R500_COLOR_FORMAT_ARGB2101010      (5 << 21)
2425 #       define R300_COLOR_FORMAT_ARGB8888         (6 << 21)
2426 #       define R300_COLOR_FORMAT_ARGB32323232     (7 << 21)
2427 /* reserved */
2428 #       define R300_COLOR_FORMAT_I8               (9 << 21)
2429 #       define R300_COLOR_FORMAT_ARGB16161616     (10 << 21)
2430 #       define R300_COLOR_FORMAT_VYUY             (11 << 21)
2431 #       define R300_COLOR_FORMAT_YVYU             (12 << 21)
2432 #       define R300_COLOR_FORMAT_UV88             (13 << 21)
2433 #       define R500_COLOR_FORMAT_I10              (14 << 21)
2434 #       define R300_COLOR_FORMAT_ARGB4444         (15 << 21)
2435 #define R300_RB3D_COLORPITCH1               0x4E3C
2436 #define R300_RB3D_COLORPITCH2               0x4E40
2437 #define R300_RB3D_COLORPITCH3               0x4E44
2438 
2439 /* gap */
2440 
2441 /* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then
2442  * a flush or free will not occur upon a write to this register, but a sync
2443  * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE
2444  * are zero but DC_FINISH is one, then a sync will be sent immediately -- the
2445  * cb will not wait for all the previous operations to complete before sending
2446  * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to
2447  * zero.
2448  *
2449  * Set to 0A before 3D operations, set to 02 afterwards.
2450  */
2451 #define R300_RB3D_DSTCACHE_CTLSTAT               0x4e4c
2452 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT         (0 << 0)
2453 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1       (1 << 0)
2454 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D    (2 << 0)
2455 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1  (3 << 0)
2456 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT          (0 << 2)
2457 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1        (1 << 2)
2458 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS       (2 << 2)
2459 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1     (3 << 2)
2460 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL        (0 << 4)
2461 #	define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL           (1 << 4)
2462 
2463 #define R300_RB3D_DITHER_CTL 0x4E50
2464 #	define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE         (0 << 0)
2465 #	define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND            (1 << 0)
2466 #	define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT              (2 << 0)
2467 /* reserved */
2468 #	define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE   (0 << 2)
2469 #	define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND      (1 << 2)
2470 #	define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT        (2 << 2)
2471 /* reserved */
2472 
2473 #define R300_RB3D_CMASK_OFFSET0 0x4E54
2474 #define R300_RB3D_CMASK_OFFSET1 0x4E58
2475 #define R300_RB3D_CMASK_OFFSET2 0x4E5C
2476 #define R300_RB3D_CMASK_OFFSET3 0x4E60
2477 #define R300_RB3D_CMASK_PITCH0  0x4E64
2478 #define R300_RB3D_CMASK_PITCH1  0x4E68
2479 #define R300_RB3D_CMASK_PITCH2  0x4E6C
2480 #define R300_RB3D_CMASK_PITCH3  0x4E70
2481 #define R300_RB3D_CMASK_WRINDEX 0x4E74
2482 #define R300_RB3D_CMASK_DWORD   0x4E78
2483 #define R300_RB3D_CMASK_RDINDEX 0x4E7C
2484 
2485 /* Resolve buffer destination address. The cache must be empty before changing
2486  * this register if the cb is in resolve mode. Unpipelined
2487  */
2488 #define R300_RB3D_AARESOLVE_OFFSET        0x4e80
2489 #	define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5
2490 #	define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */
2491 
2492 /* Resolve Buffer Pitch and Tiling Control. The cache must be empty before
2493  * changing this register if the cb is in resolve mode. Unpipelined
2494  */
2495 #define R300_RB3D_AARESOLVE_PITCH         0x4e84
2496 #	define R300_RB3D_AARESOLVE_PITCH_SHIFT 1
2497 #	define R300_RB3D_AARESOLVE_PITCH_MASK  0x00003ffe /* At least according to the calculations of Christoph Brill */
2498 
2499 /* Resolve Buffer Control. Unpipelined */
2500 #define R300_RB3D_AARESOLVE_CTL           0x4e88
2501 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL   (0 << 0)
2502 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE  (1 << 0)
2503 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10      (0 << 1)
2504 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22      (1 << 1)
2505 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2)
2506 #	define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2)
2507 
2508 
2509 /* Discard src pixels less than or equal to threshold. */
2510 #define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0
2511 /* Discard src pixels greater than or equal to threshold. */
2512 #define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4
2513 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0
2514 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff
2515 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8
2516 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00
2517 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16
2518 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000
2519 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24
2520 #	define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000
2521 
2522 /* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */
2523 #define R300_RB3D_ROPCNTL                             0x4e18
2524 #	define R300_RB3D_ROPCNTL_ROP_ENABLE            0x00000004
2525 #	define R300_RB3D_ROPCNTL_ROP_MASK              (15 << 8)
2526 #	define R300_RB3D_ROPCNTL_ROP_SHIFT             8
2527 
2528 /* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */
2529 #define R300_RB3D_CLRCMP_FLIPE                        0x4e1c
2530 
2531 /* Sets the fifo sizes */
2532 #define R500_RB3D_FIFO_SIZE                           0x4ef4
2533 #	define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL   (0 << 0)
2534 #	define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF   (1 << 0)
2535 #	define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
2536 #	define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0)
2537 
2538 /* Constant color used by the blender. Pipelined through the blender. */
2539 #define R500_RB3D_CONSTANT_COLOR_AR                   0x4ef8
2540 #	define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK    0x0000ffff
2541 #	define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT   0
2542 #	define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK  0xffff0000
2543 #	define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16
2544 
2545 /* Constant color used by the blender. Pipelined through the blender. */
2546 #define R500_RB3D_CONSTANT_COLOR_GB                   0x4efc
2547 #	define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK   0x0000ffff
2548 #	define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT  0
2549 #	define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK  0xffff0000
2550 #	define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16
2551 
2552 /* gap */
2553 /* There seems to be no "write only" setting, so use Z-test = ALWAYS
2554  * for this.
2555  * Bit (1<<8) is the "test" bit. so plain write is 6  - vd
2556  */
2557 #define R300_ZB_CNTL                             0x4F00
2558 #	define R300_STENCIL_ENABLE		 (1 << 0)
2559 #	define R300_Z_ENABLE		         (1 << 1)
2560 #	define R300_Z_WRITE_ENABLE		 (1 << 2)
2561 #	define R300_Z_SIGNED_COMPARE		 (1 << 3)
2562 #	define R300_STENCIL_FRONT_BACK		 (1 << 4)
2563 #   define R500_STENCIL_ZSIGNED_MAGNITUDE (1 << 5)
2564 #   define R500_STENCIL_REFMASK_FRONT_BACK (1 << 6)
2565 
2566 #define R300_ZB_ZSTENCILCNTL                   0x4f04
2567 	/* functions */
2568 #	define R300_ZS_NEVER			0
2569 #	define R300_ZS_LESS			1
2570 #	define R300_ZS_LEQUAL			2
2571 #	define R300_ZS_EQUAL			3
2572 #	define R300_ZS_GEQUAL			4
2573 #	define R300_ZS_GREATER			5
2574 #	define R300_ZS_NOTEQUAL			6
2575 #	define R300_ZS_ALWAYS			7
2576 #       define R300_ZS_MASK                     7
2577 	/* operations */
2578 #	define R300_ZS_KEEP			0
2579 #	define R300_ZS_ZERO			1
2580 #	define R300_ZS_REPLACE			2
2581 #	define R300_ZS_INCR			3
2582 #	define R300_ZS_DECR			4
2583 #	define R300_ZS_INVERT			5
2584 #	define R300_ZS_INCR_WRAP		6
2585 #	define R300_ZS_DECR_WRAP		7
2586 #	define R300_Z_FUNC_SHIFT		0
2587 	/* front and back refer to operations done for front
2588 	   and back faces, i.e. separate stencil function support */
2589 #	define R300_S_FRONT_FUNC_SHIFT	        3
2590 #	define R300_S_FRONT_SFAIL_OP_SHIFT	6
2591 #	define R300_S_FRONT_ZPASS_OP_SHIFT	9
2592 #	define R300_S_FRONT_ZFAIL_OP_SHIFT      12
2593 #	define R300_S_BACK_FUNC_SHIFT           15
2594 #	define R300_S_BACK_SFAIL_OP_SHIFT       18
2595 #	define R300_S_BACK_ZPASS_OP_SHIFT       21
2596 #	define R300_S_BACK_ZFAIL_OP_SHIFT       24
2597 
2598 #define R300_ZB_STENCILREFMASK                        0x4f08
2599 #	define R300_STENCILREF_SHIFT       0
2600 #	define R300_STENCILREF_MASK        0x000000ff
2601 #	define R300_STENCILMASK_SHIFT      8
2602 #	define R300_STENCILMASK_MASK       0x0000ff00
2603 #	define R300_STENCILWRITEMASK_SHIFT 16
2604 #	define R300_STENCILWRITEMASK_MASK  0x00ff0000
2605 
2606 /* gap */
2607 
2608 #define R300_ZB_FORMAT                             0x4f10
2609 #	define R300_DEPTHFORMAT_16BIT_INT_Z   (0 << 0)
2610 #	define R300_DEPTHFORMAT_16BIT_13E3    (1 << 0)
2611 #	define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL   (2 << 0)
2612 /* reserved up to (15 << 0) */
2613 #	define R300_INVERT_13E3_LEADING_ONES  (0 << 4)
2614 #	define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
2615 
2616 #define R300_ZB_ZTOP                             0x4F14
2617 #	define R300_ZTOP_DISABLE                 (0 << 0)
2618 #	define R300_ZTOP_ENABLE                  (1 << 0)
2619 
2620 /* gap */
2621 
2622 #define R300_ZB_ZCACHE_CTLSTAT            0x4f18
2623 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT      (0 << 0)
2624 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
2625 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT       (0 << 1)
2626 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE            (1 << 1)
2627 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE            (0 << 31)
2628 #       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY            (1 << 31)
2629 
2630 #define R300_ZB_BW_CNTL                     0x4f1c
2631 #	define R300_HIZ_DISABLE                              (0 << 0)
2632 #	define R300_HIZ_ENABLE                               (1 << 0)
2633 #	define R300_HIZ_MAX                                  (0 << 1)
2634 #	define R300_HIZ_MIN                                  (1 << 1)
2635 #	define R300_FAST_FILL_DISABLE                        (0 << 2)
2636 #	define R300_FAST_FILL_ENABLE                         (1 << 2)
2637 #	define R300_RD_COMP_DISABLE                          (0 << 3)
2638 #	define R300_RD_COMP_ENABLE                           (1 << 3)
2639 #	define R300_WR_COMP_DISABLE                          (0 << 4)
2640 #	define R300_WR_COMP_ENABLE                           (1 << 4)
2641 #	define R300_ZB_CB_CLEAR_RMW                          (0 << 5)
2642 #	define R300_ZB_CB_CLEAR_CACHE_LINE_WRITE_ONLY        (1 << 5)
2643 #	define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE   (0 << 6)
2644 #	define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE    (1 << 6)
2645 
2646 #	define R500_ZEQUAL_OPTIMIZE_ENABLE                   (0 << 7)
2647 #	define R500_ZEQUAL_OPTIMIZE_DISABLE                  (1 << 7)
2648 #	define R500_SEQUAL_OPTIMIZE_ENABLE                   (0 << 8)
2649 #	define R500_SEQUAL_OPTIMIZE_DISABLE                  (1 << 8)
2650 
2651 #	define R500_BMASK_ENABLE                             (0 << 10)
2652 #	define R500_BMASK_DISABLE                            (1 << 10)
2653 #	define R500_HIZ_EQUAL_REJECT_DISABLE                 (0 << 11)
2654 #	define R500_HIZ_EQUAL_REJECT_ENABLE                  (1 << 11)
2655 #	define R500_HIZ_FP_EXP_BITS_DISABLE                  (0 << 12)
2656 #	define R500_HIZ_FP_EXP_BITS_1                        (1 << 12)
2657 #	define R500_HIZ_FP_EXP_BITS_2                        (2 << 12)
2658 #	define R500_HIZ_FP_EXP_BITS_3                        (3 << 12)
2659 #	define R500_HIZ_FP_EXP_BITS_4                        (4 << 12)
2660 #	define R500_HIZ_FP_EXP_BITS_5                        (5 << 12)
2661 #	define R500_HIZ_FP_INVERT_LEADING_ONES               (0 << 15)
2662 #	define R500_HIZ_FP_INVERT_LEADING_ZEROS              (1 << 15)
2663 #	define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE      (0 << 16)
2664 #	define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE     (1 << 16)
2665 #	define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE           (0 << 17)
2666 #	define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE          (1 << 17)
2667 #	define R500_PEQ_PACKING_DISABLE                      (0 << 18)
2668 #	define R500_PEQ_PACKING_ENABLE                       (1 << 18)
2669 #	define R500_COVERED_PTR_MASKING_DISABLE              (0 << 18)
2670 #	define R500_COVERED_PTR_MASKING_ENABLE               (1 << 18)
2671 
2672 
2673 /* gap */
2674 
2675 /* Z Buffer Address Offset.
2676  * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
2677  */
2678 #define R300_ZB_DEPTHOFFSET               0x4f20
2679 
2680 /* Z Buffer Pitch and Endian Control */
2681 #define R300_ZB_DEPTHPITCH                0x4f24
2682 #       define R300_DEPTHPITCH_MASK              0x00003FFC
2683 #       define R300_DEPTHMACROTILE_DISABLE      (0 << 16)
2684 #       define R300_DEPTHMACROTILE_ENABLE       (1 << 16)
2685 #       define R300_DEPTHMACROTILE(x)           ((x) << 16)
2686 #       define R300_DEPTHMICROTILE_LINEAR       (0 << 17)
2687 #       define R300_DEPTHMICROTILE_TILED        (1 << 17)
2688 #       define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
2689 #       define R300_DEPTHMICROTILE(x)           ((x) << 17)
2690 #       define R300_DEPTHENDIAN(x)              ((x) << 19)
2691 
2692 #define R300_SURF_NO_SWAP         0
2693 #define R300_SURF_WORD_SWAP       1
2694 #define R300_SURF_DWORD_SWAP      2
2695 #define R300_SURF_HALF_DWORD_SWAP 3
2696 
2697 /* Z Buffer Clear Value */
2698 #define R300_ZB_DEPTHCLEARVALUE                  0x4f28
2699 
2700 /* Z Mask RAM is a Z compression buffer.
2701  * Each dword of the Z Mask contains compression info for 16 4x4 pixel blocks,
2702  * that is 2 bits for each block.
2703  * On chips with 2 Z pipes, every other dword maps to a different pipe.
2704  */
2705 
2706 /* The dword offset into Z mask RAM (bits 18:4) */
2707 #define R300_ZB_ZMASK_OFFSET                     0x4f30
2708 
2709 /* Z Mask Pitch. */
2710 #define R300_ZB_ZMASK_PITCH                      0x4f34
2711 
2712 /* Access to Z Mask RAM in a manner similar to HiZ RAM.
2713  * The indices are autoincrementing. */
2714 #define R300_ZB_ZMASK_WRINDEX                    0x4f38
2715 #define R300_ZB_ZMASK_DWORD                      0x4f3c
2716 #define R300_ZB_ZMASK_RDINDEX                    0x4f40
2717 
2718 /* Hierarchical Z Memory Offset */
2719 #define R300_ZB_HIZ_OFFSET                       0x4f44
2720 
2721 /* Hierarchical Z Write Index */
2722 #define R300_ZB_HIZ_WRINDEX                      0x4f48
2723 
2724 /* Hierarchical Z Data */
2725 #define R300_ZB_HIZ_DWORD                        0x4f4c
2726 
2727 /* Hierarchical Z Read Index */
2728 #define R300_ZB_HIZ_RDINDEX                      0x4f50
2729 
2730 /* Hierarchical Z Pitch */
2731 #define R300_ZB_HIZ_PITCH                        0x4f54
2732 
2733 /* Z Buffer Z Pass Counter Data */
2734 #define R300_ZB_ZPASS_DATA                       0x4f58
2735 
2736 /* Z Buffer Z Pass Counter Address */
2737 #define R300_ZB_ZPASS_ADDR                       0x4f5c
2738 
2739 /* Depth buffer X and Y coordinate offset */
2740 #define R300_ZB_DEPTHXY_OFFSET                   0x4f60
2741 #	define R300_DEPTHX_OFFSET_SHIFT  1
2742 #	define R300_DEPTHX_OFFSET_MASK   0x000007FE
2743 #	define R300_DEPTHY_OFFSET_SHIFT  17
2744 #	define R300_DEPTHY_OFFSET_MASK   0x07FE0000
2745 
2746 /* Sets the fifo sizes */
2747 #define R500_ZB_FIFO_SIZE                        0x4fd0
2748 #	define R500_OP_FIFO_SIZE_FULL   (0 << 0)
2749 #	define R500_OP_FIFO_SIZE_HALF   (1 << 0)
2750 #	define R500_OP_FIFO_SIZE_QUATER (2 << 0)
2751 #	define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
2752 
2753 /* Stencil Reference Value and Mask for backfacing quads */
2754 /* R300_ZB_STENCILREFMASK handles front face */
2755 #define R500_ZB_STENCILREFMASK_BF                0x4fd4
2756 #	define R500_STENCILREF_SHIFT       0
2757 #	define R500_STENCILREF_MASK        0x000000ff
2758 #	define R500_STENCILMASK_SHIFT      8
2759 #	define R500_STENCILMASK_MASK       0x0000ff00
2760 #	define R500_STENCILWRITEMASK_SHIFT 16
2761 #	define R500_STENCILWRITEMASK_MASK  0x00ff0000
2762 
2763 /**
2764  * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION
2765  *
2766  * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector
2767  * Engine instruction or a Math Engine instruction.
2768  */
2769 
2770 /*\{*/
2771 
2772 enum {
2773 	/* R3XX */
2774 	VECTOR_NO_OP			= 0,
2775 	VE_DOT_PRODUCT			= 1,
2776 	VE_MULTIPLY			= 2,
2777 	VE_ADD				= 3,
2778 	VE_MULTIPLY_ADD			= 4,
2779 	VE_DISTANCE_VECTOR		= 5,
2780 	VE_FRACTION			= 6,
2781 	VE_MAXIMUM			= 7,
2782 	VE_MINIMUM			= 8,
2783 	VE_SET_GREATER_THAN_EQUAL	= 9,
2784 	VE_SET_LESS_THAN		= 10,
2785 	VE_MULTIPLYX2_ADD		= 11,
2786 	VE_MULTIPLY_CLAMP		= 12,
2787 	VE_FLT2FIX_DX			= 13,
2788 	VE_FLT2FIX_DX_RND		= 14,
2789 	/* R5XX */
2790 	VE_PRED_SET_EQ_PUSH		= 15,
2791 	VE_PRED_SET_GT_PUSH		= 16,
2792 	VE_PRED_SET_GTE_PUSH		= 17,
2793 	VE_PRED_SET_NEQ_PUSH		= 18,
2794 	VE_COND_WRITE_EQ		= 19,
2795 	VE_COND_WRITE_GT		= 20,
2796 	VE_COND_WRITE_GTE		= 21,
2797 	VE_COND_WRITE_NEQ		= 22,
2798 	VE_COND_MUX_EQ			= 23,
2799 	VE_COND_MUX_GT			= 24,
2800 	VE_COND_MUX_GTE			= 25,
2801 	VE_SET_GREATER_THAN		= 26,
2802 	VE_SET_EQUAL			= 27,
2803 	VE_SET_NOT_EQUAL		= 28
2804 };
2805 
2806 enum {
2807 	/* R3XX */
2808 	MATH_NO_OP			= 0,
2809 	ME_EXP_BASE2_DX			= 1,
2810 	ME_LOG_BASE2_DX			= 2,
2811 	ME_EXP_BASEE_FF			= 3,
2812 	ME_LIGHT_COEFF_DX		= 4,
2813 	ME_POWER_FUNC_FF		= 5,
2814 	ME_RECIP_DX			= 6,
2815 	ME_RECIP_FF			= 7,
2816 	ME_RECIP_SQRT_DX		= 8,
2817 	ME_RECIP_SQRT_FF		= 9,
2818 	ME_MULTIPLY			= 10,
2819 	ME_EXP_BASE2_FULL_DX		= 11,
2820 	ME_LOG_BASE2_FULL_DX		= 12,
2821 	ME_POWER_FUNC_FF_CLAMP_B	= 13,
2822 	ME_POWER_FUNC_FF_CLAMP_B1	= 14,
2823 	ME_POWER_FUNC_FF_CLAMP_01	= 15,
2824 	ME_SIN				= 16,
2825 	ME_COS				= 17,
2826 	/* R5XX */
2827 	ME_LOG_BASE2_IEEE		= 18,
2828 	ME_RECIP_IEEE			= 19,
2829 	ME_RECIP_SQRT_IEEE		= 20,
2830 	ME_PRED_SET_EQ			= 21,
2831 	ME_PRED_SET_GT			= 22,
2832 	ME_PRED_SET_GTE			= 23,
2833 	ME_PRED_SET_NEQ			= 24,
2834 	ME_PRED_SET_CLR			= 25,
2835 	ME_PRED_SET_INV			= 26,
2836 	ME_PRED_SET_POP			= 27,
2837 	ME_PRED_SET_RESTORE		= 28
2838 };
2839 
2840 enum {
2841 	/* R3XX */
2842 	PVS_MACRO_OP_2CLK_MADD		= 0,
2843 	PVS_MACRO_OP_2CLK_M2X_ADD	= 1
2844 };
2845 
2846 enum {
2847 	PVS_SRC_REG_TEMPORARY		= 0,	/* Intermediate Storage */
2848 	PVS_SRC_REG_INPUT		= 1,	/* Input Vertex Storage */
2849 	PVS_SRC_REG_CONSTANT		= 2,	/* Constant State Storage */
2850 	PVS_SRC_REG_ALT_TEMPORARY	= 3	/* Alternate Intermediate Storage */
2851 };
2852 
2853 enum {
2854 	PVS_DST_REG_TEMPORARY		= 0,	/* Intermediate Storage */
2855 	PVS_DST_REG_A0			= 1,	/* Address Register Storage */
2856 	PVS_DST_REG_OUT			= 2,	/* Output Memory. Used for all outputs */
2857 	PVS_DST_REG_OUT_REPL_X		= 3,	/* Output Memory & Replicate X to all channels */
2858 	PVS_DST_REG_ALT_TEMPORARY	= 4,	/* Alternate Intermediate Storage */
2859 	PVS_DST_REG_INPUT		= 5	/* Output Memory & Replicate X to all channels */
2860 };
2861 
2862 enum {
2863 	PVS_SRC_SELECT_X		= 0,	/* Select X Component */
2864 	PVS_SRC_SELECT_Y		= 1,	/* Select Y Component */
2865 	PVS_SRC_SELECT_Z		= 2,	/* Select Z Component */
2866 	PVS_SRC_SELECT_W		= 3,	/* Select W Component */
2867 	PVS_SRC_SELECT_FORCE_0		= 4,	/* Force Component to 0.0 */
2868 	PVS_SRC_SELECT_FORCE_1		= 5	/* Force Component to 1.0 */
2869 };
2870 
2871 /* PVS Opcode & Destination Operand Description */
2872 
2873 enum {
2874 	PVS_DST_OPCODE_MASK		= 0x3f,
2875 	PVS_DST_OPCODE_SHIFT		= 0,
2876 	PVS_DST_MATH_INST_MASK		= 0x1,
2877 	PVS_DST_MATH_INST_SHIFT		= 6,
2878 	PVS_DST_MACRO_INST_MASK		= 0x1,
2879 	PVS_DST_MACRO_INST_SHIFT	= 7,
2880 	PVS_DST_REG_TYPE_MASK		= 0xf,
2881 	PVS_DST_REG_TYPE_SHIFT		= 8,
2882 	PVS_DST_ADDR_MODE_1_MASK	= 0x1,
2883 	PVS_DST_ADDR_MODE_1_SHIFT	= 12,
2884 	PVS_DST_OFFSET_MASK		= 0x7f,
2885 	PVS_DST_OFFSET_SHIFT		= 13,
2886 	PVS_DST_WE_X_MASK		= 0x1,
2887 	PVS_DST_WE_X_SHIFT		= 20,
2888 	PVS_DST_WE_Y_MASK		= 0x1,
2889 	PVS_DST_WE_Y_SHIFT		= 21,
2890 	PVS_DST_WE_Z_MASK		= 0x1,
2891 	PVS_DST_WE_Z_SHIFT		= 22,
2892 	PVS_DST_WE_W_MASK		= 0x1,
2893 	PVS_DST_WE_W_SHIFT		= 23,
2894 	PVS_DST_VE_SAT_MASK		= 0x1,
2895 	PVS_DST_VE_SAT_SHIFT		= 24,
2896 	PVS_DST_ME_SAT_MASK		= 0x1,
2897 	PVS_DST_ME_SAT_SHIFT		= 25,
2898 	PVS_DST_PRED_ENABLE_MASK	= 0x1,
2899 	PVS_DST_PRED_ENABLE_SHIFT	= 26,
2900 	PVS_DST_PRED_SENSE_MASK		= 0x1,
2901 	PVS_DST_PRED_SENSE_SHIFT	= 27,
2902 	PVS_DST_DUAL_MATH_OP_MASK	= 0x3,
2903 	PVS_DST_DUAL_MATH_OP_SHIFT	= 27,
2904 	PVS_DST_ADDR_SEL_MASK		= 0x3,
2905 	PVS_DST_ADDR_SEL_SHIFT		= 29,
2906 	PVS_DST_ADDR_MODE_0_MASK	= 0x1,
2907 	PVS_DST_ADDR_MODE_0_SHIFT	= 31
2908 };
2909 
2910 /* PVS Source Operand Description */
2911 
2912 enum {
2913 	PVS_SRC_REG_TYPE_MASK		= 0x3,
2914 	PVS_SRC_REG_TYPE_SHIFT		= 0,
2915 	SPARE_0_MASK			= 0x1,
2916 	SPARE_0_SHIFT			= 2,
2917 	PVS_SRC_ABS_XYZW_MASK		= 0x1,
2918 	PVS_SRC_ABS_XYZW_SHIFT		= 3,
2919 	PVS_SRC_ADDR_MODE_0_MASK	= 0x1,
2920 	PVS_SRC_ADDR_MODE_0_SHIFT	= 4,
2921 	PVS_SRC_OFFSET_MASK		= 0xff,
2922 	PVS_SRC_OFFSET_SHIFT		= 5,
2923 	PVS_SRC_SWIZZLE_X_MASK		= 0x7,
2924 	PVS_SRC_SWIZZLE_X_SHIFT		= 13,
2925 	PVS_SRC_SWIZZLE_Y_MASK		= 0x7,
2926 	PVS_SRC_SWIZZLE_Y_SHIFT		= 16,
2927 	PVS_SRC_SWIZZLE_Z_MASK		= 0x7,
2928 	PVS_SRC_SWIZZLE_Z_SHIFT		= 19,
2929 	PVS_SRC_SWIZZLE_W_MASK		= 0x7,
2930 	PVS_SRC_SWIZZLE_W_SHIFT		= 22,
2931 	PVS_SRC_MODIFIER_X_MASK		= 0x1,
2932 	PVS_SRC_MODIFIER_X_SHIFT	= 25,
2933 	PVS_SRC_MODIFIER_Y_MASK		= 0x1,
2934 	PVS_SRC_MODIFIER_Y_SHIFT	= 26,
2935 	PVS_SRC_MODIFIER_Z_MASK		= 0x1,
2936 	PVS_SRC_MODIFIER_Z_SHIFT	= 27,
2937 	PVS_SRC_MODIFIER_W_MASK		= 0x1,
2938 	PVS_SRC_MODIFIER_W_SHIFT	= 28,
2939 	PVS_SRC_ADDR_SEL_MASK		= 0x3,
2940 	PVS_SRC_ADDR_SEL_SHIFT		= 29,
2941 	PVS_SRC_ADDR_MODE_1_MASK	= 0x0,
2942 	PVS_SRC_ADDR_MODE_1_SHIFT	= 32
2943 };
2944 
2945 /*\}*/
2946 
2947 #define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, saturate)	\
2948 	 (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT)	\
2949 	 | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT)	\
2950 	 | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT)	\
2951 	 | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT)	\
2952 	 | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT)	/* X Y Z W */	\
2953 	 | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) \
2954          | ((math_inst) ? (((saturate) & PVS_DST_ME_SAT_MASK) << PVS_DST_ME_SAT_SHIFT) : \
2955                           (((saturate) & PVS_DST_VE_SAT_MASK) << PVS_DST_VE_SAT_SHIFT))
2956 
2957 #define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate)	\
2958 	(((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT)				\
2959 	 | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT)			\
2960 	 | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT)			\
2961 	 | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT)			\
2962 	 | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT)			\
2963 	 | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT)	/* X Y Z W */				\
2964 	 | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT))
2965 
2966 /* BEGIN: Packet 3 commands */
2967 
2968 /* A primitive emission dword. */
2969 #define R300_PRIM_TYPE_NONE                     (0 << 0)
2970 #define R300_PRIM_TYPE_POINT                    (1 << 0)
2971 #define R300_PRIM_TYPE_LINE                     (2 << 0)
2972 #define R300_PRIM_TYPE_LINE_STRIP               (3 << 0)
2973 #define R300_PRIM_TYPE_TRI_LIST                 (4 << 0)
2974 #define R300_PRIM_TYPE_TRI_FAN                  (5 << 0)
2975 #define R300_PRIM_TYPE_TRI_STRIP                (6 << 0)
2976 #define R300_PRIM_TYPE_TRI_TYPE2                (7 << 0)
2977 #define R300_PRIM_TYPE_RECT_LIST                (8 << 0)
2978 #define R300_PRIM_TYPE_3VRT_POINT_LIST          (9 << 0)
2979 #define R300_PRIM_TYPE_3VRT_LINE_LIST           (10 << 0)
2980 	/* GUESS (based on r200) */
2981 #define R300_PRIM_TYPE_POINT_SPRITES            (11 << 0)
2982 #define R300_PRIM_TYPE_LINE_LOOP                (12 << 0)
2983 #define R300_PRIM_TYPE_QUADS                    (13 << 0)
2984 #define R300_PRIM_TYPE_QUAD_STRIP               (14 << 0)
2985 #define R300_PRIM_TYPE_POLYGON                  (15 << 0)
2986 #define R300_PRIM_TYPE_MASK                     0xF
2987 #define R300_PRIM_WALK_IND                      (1 << 4)
2988 #define R300_PRIM_WALK_LIST                     (2 << 4)
2989 #define R300_PRIM_WALK_RING                     (3 << 4)
2990 #define R300_PRIM_WALK_MASK                     (3 << 4)
2991 	/* GUESS (based on r200) */
2992 #define R300_PRIM_COLOR_ORDER_BGRA              (0 << 6)
2993 #define R300_PRIM_COLOR_ORDER_RGBA              (1 << 6)
2994 #define R300_PRIM_NUM_VERTICES_SHIFT            16
2995 #define R300_PRIM_NUM_VERTICES_MASK             0xffff
2996 
2997 
2998 
2999 /*
3000  * The R500 unified shader (US) registers come in banks of 512 each, one
3001  * for each instruction slot in the shader.  You can't touch them directly.
3002  * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive
3003  * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the
3004  * instruction is fully specified.
3005  */
3006 #define R500_US_ALU_ALPHA_INST_0			0xa800
3007 #   define R500_ALPHA_OP_MAD				0
3008 #   define R500_ALPHA_OP_DP				1
3009 #   define R500_ALPHA_OP_MIN				2
3010 #   define R500_ALPHA_OP_MAX				3
3011 /* #define R500_ALPHA_OP_RESERVED			4 */
3012 #   define R500_ALPHA_OP_CND				5
3013 #   define R500_ALPHA_OP_CMP				6
3014 #   define R500_ALPHA_OP_FRC				7
3015 #   define R500_ALPHA_OP_EX2				8
3016 #   define R500_ALPHA_OP_LN2				9
3017 #   define R500_ALPHA_OP_RCP				10
3018 #   define R500_ALPHA_OP_RSQ				11
3019 #   define R500_ALPHA_OP_SIN				12
3020 #   define R500_ALPHA_OP_COS				13
3021 #   define R500_ALPHA_OP_MDH				14
3022 #   define R500_ALPHA_OP_MDV				15
3023 #   define R500_ALPHA_ADDRD(x)				((x) << 4)
3024 #   define R500_ALPHA_ADDRD_REL				(1 << 11)
3025 #  define R500_ALPHA_SEL_A_SHIFT			12
3026 #   define R500_ALPHA_SEL_A_SRC0			(0 << 12)
3027 #   define R500_ALPHA_SEL_A_SRC1			(1 << 12)
3028 #   define R500_ALPHA_SEL_A_SRC2			(2 << 12)
3029 #   define R500_ALPHA_SEL_A_SRCP			(3 << 12)
3030 #   define R500_ALPHA_SWIZ_A_R				(0 << 14)
3031 #   define R500_ALPHA_SWIZ_A_G				(1 << 14)
3032 #   define R500_ALPHA_SWIZ_A_B				(2 << 14)
3033 #   define R500_ALPHA_SWIZ_A_A				(3 << 14)
3034 #   define R500_ALPHA_SWIZ_A_0				(4 << 14)
3035 #   define R500_ALPHA_SWIZ_A_HALF			(5 << 14)
3036 #   define R500_ALPHA_SWIZ_A_1				(6 << 14)
3037 /* #define R500_ALPHA_SWIZ_A_UNUSED			(7 << 14) */
3038 #   define R500_ALPHA_MOD_A_NOP				(0 << 17)
3039 #   define R500_ALPHA_MOD_A_NEG				(1 << 17)
3040 #   define R500_ALPHA_MOD_A_ABS				(2 << 17)
3041 #   define R500_ALPHA_MOD_A_NAB				(3 << 17)
3042 #  define R500_ALPHA_SEL_B_SHIFT			19
3043 #   define R500_ALPHA_SEL_B_SRC0			(0 << 19)
3044 #   define R500_ALPHA_SEL_B_SRC1			(1 << 19)
3045 #   define R500_ALPHA_SEL_B_SRC2			(2 << 19)
3046 #   define R500_ALPHA_SEL_B_SRCP			(3 << 19)
3047 #   define R500_ALPHA_SWIZ_B_R				(0 << 21)
3048 #   define R500_ALPHA_SWIZ_B_G				(1 << 21)
3049 #   define R500_ALPHA_SWIZ_B_B				(2 << 21)
3050 #   define R500_ALPHA_SWIZ_B_A				(3 << 21)
3051 #   define R500_ALPHA_SWIZ_B_0				(4 << 21)
3052 #   define R500_ALPHA_SWIZ_B_HALF			(5 << 21)
3053 #   define R500_ALPHA_SWIZ_B_1				(6 << 21)
3054 /* #define R500_ALPHA_SWIZ_B_UNUSED			(7 << 21) */
3055 #   define R500_ALPHA_MOD_B_NOP				(0 << 24)
3056 #   define R500_ALPHA_MOD_B_NEG				(1 << 24)
3057 #   define R500_ALPHA_MOD_B_ABS				(2 << 24)
3058 #   define R500_ALPHA_MOD_B_NAB				(3 << 24)
3059 #   define R500_ALPHA_OMOD_SHIFT		26
3060 #   define R500_ALPHA_OMOD_IDENTITY		(0 << R500_ALPHA_OMOD_SHIFT)
3061 #   define R500_ALPHA_OMOD_MUL_2		(1 << R500_ALPHA_OMOD_SHIFT)
3062 #   define R500_ALPHA_OMOD_MUL_4		(2 << R500_ALPHA_OMOD_SHIFT)
3063 #   define R500_ALPHA_OMOD_MUL_8		(3 << R500_ALPHA_OMOD_SHIFT)
3064 #   define R500_ALPHA_OMOD_DIV_2		(4 << R500_ALPHA_OMOD_SHIFT)
3065 #   define R500_ALPHA_OMOD_DIV_4		(5 << R500_ALPHA_OMOD_SHIFT)
3066 #   define R500_ALPHA_OMOD_DIV_8		(6 << R500_ALPHA_OMOD_SHIFT)
3067 #   define R500_ALPHA_OMOD_DISABLE		(7 << R500_ALPHA_OMOD_SHIFT)
3068 #   define R500_ALPHA_TARGET(x)				((x) << 29)
3069 #   define R500_ALPHA_W_OMASK				(1 << 31)
3070 #define R500_US_ALU_ALPHA_ADDR_0			0x9800
3071 #   define R500_ALPHA_ADDR0(x)				((x) << 0)
3072 #   define R500_ALPHA_ADDR0_CONST			(1 << 8)
3073 #   define R500_ALPHA_ADDR0_REL				(1 << 9)
3074 #   define R500_ALPHA_ADDR1(x)				((x) << 10)
3075 #   define R500_ALPHA_ADDR1_CONST			(1 << 18)
3076 #   define R500_ALPHA_ADDR1_REL				(1 << 19)
3077 #   define R500_ALPHA_ADDR2(x)				((x) << 20)
3078 #   define R500_ALPHA_ADDR2_CONST			(1 << 28)
3079 #   define R500_ALPHA_ADDR2_REL				(1 << 29)
3080 #   define R500_ALPHA_SRCP_OP_1_MINUS_2A0		(0 << 30)
3081 #   define R500_ALPHA_SRCP_OP_A1_MINUS_A0		(1 << 30)
3082 #   define R500_ALPHA_SRCP_OP_A1_PLUS_A0		(2 << 30)
3083 #   define R500_ALPHA_SRCP_OP_1_MINUS_A0		(3 << 30)
3084 #define R500_US_ALU_RGBA_INST_0				0xb000
3085 #   define R500_ALU_RGBA_OP_MAD				(0 << 0)
3086 #   define R500_ALU_RGBA_OP_DP3				(1 << 0)
3087 #   define R500_ALU_RGBA_OP_DP4				(2 << 0)
3088 #   define R500_ALU_RGBA_OP_D2A				(3 << 0)
3089 #   define R500_ALU_RGBA_OP_MIN				(4 << 0)
3090 #   define R500_ALU_RGBA_OP_MAX				(5 << 0)
3091 /* #define R500_ALU_RGBA_OP_RESERVED			(6 << 0) */
3092 #   define R500_ALU_RGBA_OP_CND				(7 << 0)
3093 #   define R500_ALU_RGBA_OP_CMP				(8 << 0)
3094 #   define R500_ALU_RGBA_OP_FRC				(9 << 0)
3095 #   define R500_ALU_RGBA_OP_SOP				(10 << 0)
3096 #   define R500_ALU_RGBA_OP_MDH				(11 << 0)
3097 #   define R500_ALU_RGBA_OP_MDV				(12 << 0)
3098 #   define R500_ALU_RGBA_ADDRD(x)			((x) << 4)
3099 #   define R500_ALU_RGBA_ADDRD_REL			(1 << 11)
3100 #  define R500_ALU_RGBA_SEL_C_SHIFT			12
3101 #   define R500_ALU_RGBA_SEL_C_SRC0			(0 << 12)
3102 #   define R500_ALU_RGBA_SEL_C_SRC1			(1 << 12)
3103 #   define R500_ALU_RGBA_SEL_C_SRC2			(2 << 12)
3104 #   define R500_ALU_RGBA_SEL_C_SRCP			(3 << 12)
3105 #   define R500_ALU_RGBA_R_SWIZ_R			(0 << 14)
3106 #   define R500_ALU_RGBA_R_SWIZ_G			(1 << 14)
3107 #   define R500_ALU_RGBA_R_SWIZ_B			(2 << 14)
3108 #   define R500_ALU_RGBA_R_SWIZ_A			(3 << 14)
3109 #   define R500_ALU_RGBA_R_SWIZ_0			(4 << 14)
3110 #   define R500_ALU_RGBA_R_SWIZ_HALF			(5 << 14)
3111 #   define R500_ALU_RGBA_R_SWIZ_1			(6 << 14)
3112 /* #define R500_ALU_RGBA_R_SWIZ_UNUSED			(7 << 14) */
3113 #   define R500_ALU_RGBA_G_SWIZ_R			(0 << 17)
3114 #   define R500_ALU_RGBA_G_SWIZ_G			(1 << 17)
3115 #   define R500_ALU_RGBA_G_SWIZ_B			(2 << 17)
3116 #   define R500_ALU_RGBA_G_SWIZ_A			(3 << 17)
3117 #   define R500_ALU_RGBA_G_SWIZ_0			(4 << 17)
3118 #   define R500_ALU_RGBA_G_SWIZ_HALF			(5 << 17)
3119 #   define R500_ALU_RGBA_G_SWIZ_1			(6 << 17)
3120 /* #define R500_ALU_RGBA_G_SWIZ_UNUSED			(7 << 17) */
3121 #   define R500_ALU_RGBA_B_SWIZ_R			(0 << 20)
3122 #   define R500_ALU_RGBA_B_SWIZ_G			(1 << 20)
3123 #   define R500_ALU_RGBA_B_SWIZ_B			(2 << 20)
3124 #   define R500_ALU_RGBA_B_SWIZ_A			(3 << 20)
3125 #   define R500_ALU_RGBA_B_SWIZ_0			(4 << 20)
3126 #   define R500_ALU_RGBA_B_SWIZ_HALF			(5 << 20)
3127 #   define R500_ALU_RGBA_B_SWIZ_1			(6 << 20)
3128 /* #define R500_ALU_RGBA_B_SWIZ_UNUSED			(7 << 20) */
3129 #   define R500_ALU_RGBA_MOD_C_NOP			(0 << 23)
3130 #   define R500_ALU_RGBA_MOD_C_NEG			(1 << 23)
3131 #   define R500_ALU_RGBA_MOD_C_ABS			(2 << 23)
3132 #   define R500_ALU_RGBA_MOD_C_NAB			(3 << 23)
3133 #  define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT		25
3134 #   define R500_ALU_RGBA_ALPHA_SEL_C_SRC0		(0 << 25)
3135 #   define R500_ALU_RGBA_ALPHA_SEL_C_SRC1		(1 << 25)
3136 #   define R500_ALU_RGBA_ALPHA_SEL_C_SRC2		(2 << 25)
3137 #   define R500_ALU_RGBA_ALPHA_SEL_C_SRCP		(3 << 25)
3138 #   define R500_ALU_RGBA_A_SWIZ_R			(0 << 27)
3139 #   define R500_ALU_RGBA_A_SWIZ_G			(1 << 27)
3140 #   define R500_ALU_RGBA_A_SWIZ_B			(2 << 27)
3141 #   define R500_ALU_RGBA_A_SWIZ_A			(3 << 27)
3142 #   define R500_ALU_RGBA_A_SWIZ_0			(4 << 27)
3143 #   define R500_ALU_RGBA_A_SWIZ_HALF			(5 << 27)
3144 #   define R500_ALU_RGBA_A_SWIZ_1			(6 << 27)
3145 /* #define R500_ALU_RGBA_A_SWIZ_UNUSED			(7 << 27) */
3146 #   define R500_ALU_RGBA_ALPHA_MOD_C_NOP		(0 << 30)
3147 #   define R500_ALU_RGBA_ALPHA_MOD_C_NEG		(1 << 30)
3148 #   define R500_ALU_RGBA_ALPHA_MOD_C_ABS		(2 << 30)
3149 #   define R500_ALU_RGBA_ALPHA_MOD_C_NAB		(3 << 30)
3150 #define R500_US_ALU_RGB_INST_0				0xa000
3151 #  define R500_ALU_RGB_SEL_A_SHIFT			0
3152 #   define R500_ALU_RGB_SEL_A_SRC0			(0 << 0)
3153 #   define R500_ALU_RGB_SEL_A_SRC1			(1 << 0)
3154 #   define R500_ALU_RGB_SEL_A_SRC2			(2 << 0)
3155 #   define R500_ALU_RGB_SEL_A_SRCP			(3 << 0)
3156 #   define R500_ALU_RGB_R_SWIZ_A_R			(0 << 2)
3157 #   define R500_ALU_RGB_R_SWIZ_A_G			(1 << 2)
3158 #   define R500_ALU_RGB_R_SWIZ_A_B			(2 << 2)
3159 #   define R500_ALU_RGB_R_SWIZ_A_A			(3 << 2)
3160 #   define R500_ALU_RGB_R_SWIZ_A_0			(4 << 2)
3161 #   define R500_ALU_RGB_R_SWIZ_A_HALF			(5 << 2)
3162 #   define R500_ALU_RGB_R_SWIZ_A_1			(6 << 2)
3163 /* #define R500_ALU_RGB_R_SWIZ_A_UNUSED			(7 << 2) */
3164 #   define R500_ALU_RGB_G_SWIZ_A_R			(0 << 5)
3165 #   define R500_ALU_RGB_G_SWIZ_A_G			(1 << 5)
3166 #   define R500_ALU_RGB_G_SWIZ_A_B			(2 << 5)
3167 #   define R500_ALU_RGB_G_SWIZ_A_A			(3 << 5)
3168 #   define R500_ALU_RGB_G_SWIZ_A_0			(4 << 5)
3169 #   define R500_ALU_RGB_G_SWIZ_A_HALF			(5 << 5)
3170 #   define R500_ALU_RGB_G_SWIZ_A_1			(6 << 5)
3171 /* #define R500_ALU_RGB_G_SWIZ_A_UNUSED			(7 << 5) */
3172 #   define R500_ALU_RGB_B_SWIZ_A_R			(0 << 8)
3173 #   define R500_ALU_RGB_B_SWIZ_A_G			(1 << 8)
3174 #   define R500_ALU_RGB_B_SWIZ_A_B			(2 << 8)
3175 #   define R500_ALU_RGB_B_SWIZ_A_A			(3 << 8)
3176 #   define R500_ALU_RGB_B_SWIZ_A_0			(4 << 8)
3177 #   define R500_ALU_RGB_B_SWIZ_A_HALF			(5 << 8)
3178 #   define R500_ALU_RGB_B_SWIZ_A_1			(6 << 8)
3179 /* #define R500_ALU_RGB_B_SWIZ_A_UNUSED			(7 << 8) */
3180 #   define R500_ALU_RGB_MOD_A_NOP			(0 << 11)
3181 #   define R500_ALU_RGB_MOD_A_NEG			(1 << 11)
3182 #   define R500_ALU_RGB_MOD_A_ABS			(2 << 11)
3183 #   define R500_ALU_RGB_MOD_A_NAB			(3 << 11)
3184 #  define R500_ALU_RGB_SEL_B_SHIFT			13
3185 #   define R500_ALU_RGB_SEL_B_SRC0			(0 << 13)
3186 #   define R500_ALU_RGB_SEL_B_SRC1			(1 << 13)
3187 #   define R500_ALU_RGB_SEL_B_SRC2			(2 << 13)
3188 #   define R500_ALU_RGB_SEL_B_SRCP			(3 << 13)
3189 #   define R500_ALU_RGB_R_SWIZ_B_R			(0 << 15)
3190 #   define R500_ALU_RGB_R_SWIZ_B_G			(1 << 15)
3191 #   define R500_ALU_RGB_R_SWIZ_B_B			(2 << 15)
3192 #   define R500_ALU_RGB_R_SWIZ_B_A			(3 << 15)
3193 #   define R500_ALU_RGB_R_SWIZ_B_0			(4 << 15)
3194 #   define R500_ALU_RGB_R_SWIZ_B_HALF			(5 << 15)
3195 #   define R500_ALU_RGB_R_SWIZ_B_1			(6 << 15)
3196 /* #define R500_ALU_RGB_R_SWIZ_B_UNUSED			(7 << 15) */
3197 #   define R500_ALU_RGB_G_SWIZ_B_R			(0 << 18)
3198 #   define R500_ALU_RGB_G_SWIZ_B_G			(1 << 18)
3199 #   define R500_ALU_RGB_G_SWIZ_B_B			(2 << 18)
3200 #   define R500_ALU_RGB_G_SWIZ_B_A			(3 << 18)
3201 #   define R500_ALU_RGB_G_SWIZ_B_0			(4 << 18)
3202 #   define R500_ALU_RGB_G_SWIZ_B_HALF			(5 << 18)
3203 #   define R500_ALU_RGB_G_SWIZ_B_1			(6 << 18)
3204 /* #define R500_ALU_RGB_G_SWIZ_B_UNUSED			(7 << 18) */
3205 #   define R500_ALU_RGB_B_SWIZ_B_R			(0 << 21)
3206 #   define R500_ALU_RGB_B_SWIZ_B_G			(1 << 21)
3207 #   define R500_ALU_RGB_B_SWIZ_B_B			(2 << 21)
3208 #   define R500_ALU_RGB_B_SWIZ_B_A			(3 << 21)
3209 #   define R500_ALU_RGB_B_SWIZ_B_0			(4 << 21)
3210 #   define R500_ALU_RGB_B_SWIZ_B_HALF			(5 << 21)
3211 #   define R500_ALU_RGB_B_SWIZ_B_1			(6 << 21)
3212 /* #define R500_ALU_RGB_B_SWIZ_B_UNUSED			(7 << 21) */
3213 #   define R500_ALU_RGB_MOD_B_NOP			(0 << 24)
3214 #   define R500_ALU_RGB_MOD_B_NEG			(1 << 24)
3215 #   define R500_ALU_RGB_MOD_B_ABS			(2 << 24)
3216 #   define R500_ALU_RGB_MOD_B_NAB			(3 << 24)
3217 #   define R500_ALU_RGB_OMOD_SHIFT		26
3218 #   define R500_ALU_RGB_OMOD_IDENTITY		(0 << R500_ALU_RGB_OMOD_SHIFT)
3219 #   define R500_ALU_RGB_OMOD_MUL_2		(1 << R500_ALU_RGB_OMOD_SHIFT)
3220 #   define R500_ALU_RGB_OMOD_MUL_4		(2 << R500_ALU_RGB_OMOD_SHIFT)
3221 #   define R500_ALU_RGB_OMOD_MUL_8		(3 << R500_ALU_RGB_OMOD_SHIFT)
3222 #   define R500_ALU_RGB_OMOD_DIV_2		(4 << R500_ALU_RGB_OMOD_SHIFT)
3223 #   define R500_ALU_RGB_OMOD_DIV_4		(5 << R500_ALU_RGB_OMOD_SHIFT)
3224 #   define R500_ALU_RGB_OMOD_DIV_8		(6 << R500_ALU_RGB_OMOD_SHIFT)
3225 #   define R500_ALU_RGB_OMOD_DISABLE		(7 << R500_ALU_RGB_OMOD_SHIFT)
3226 #   define R500_ALU_RGB_TARGET(x)			((x) << 29)
3227 #   define R500_ALU_RGB_WMASK				(1 << 31)
3228 #define R500_US_ALU_RGB_ADDR_0				0x9000
3229 #   define R500_RGB_ADDR0(x)				((x) << 0)
3230 #   define R500_RGB_ADDR0_CONST				(1 << 8)
3231 #   define R500_RGB_ADDR0_REL				(1 << 9)
3232 #   define R500_RGB_ADDR1(x)				((x) << 10)
3233 #   define R500_RGB_ADDR1_CONST				(1 << 18)
3234 #   define R500_RGB_ADDR1_REL				(1 << 19)
3235 #   define R500_RGB_ADDR2(x)				((x) << 20)
3236 #   define R500_RGB_ADDR2_CONST				(1 << 28)
3237 #   define R500_RGB_ADDR2_REL				(1 << 29)
3238 #   define R500_RGB_SRCP_OP_1_MINUS_2RGB0		(0 << 30)
3239 #   define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0		(1 << 30)
3240 #   define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0		(2 << 30)
3241 #   define R500_RGB_SRCP_OP_1_MINUS_RGB0		(3 << 30)
3242 #define R500_US_CMN_INST_0				0xb800
3243 #  define R500_INST_TYPE_MASK				(3 << 0)
3244 #   define R500_INST_TYPE_ALU				(0 << 0)
3245 #   define R500_INST_TYPE_OUT				(1 << 0)
3246 #   define R500_INST_TYPE_FC				(2 << 0)
3247 #   define R500_INST_TYPE_TEX				(3 << 0)
3248 #   define R500_INST_TEX_SEM_WAIT_SHIFT			2
3249 #   define R500_INST_TEX_SEM_WAIT			(1 << R500_INST_TEX_SEM_WAIT_SHIFT)
3250 #   define R500_INST_RGB_PRED_SEL_NONE			(0 << 3)
3251 #   define R500_INST_RGB_PRED_SEL_RGBA			(1 << 3)
3252 #   define R500_INST_RGB_PRED_SEL_RRRR			(2 << 3)
3253 #   define R500_INST_RGB_PRED_SEL_GGGG			(3 << 3)
3254 #   define R500_INST_RGB_PRED_SEL_BBBB			(4 << 3)
3255 #   define R500_INST_RGB_PRED_SEL_AAAA			(5 << 3)
3256 #   define R500_INST_RGB_PRED_INV			(1 << 6)
3257 #   define R500_INST_WRITE_INACTIVE			(1 << 7)
3258 #   define R500_INST_LAST				(1 << 8)
3259 #   define R500_INST_NOP				(1 << 9)
3260 #   define R500_INST_ALU_WAIT				(1 << 10)
3261 #   define R500_INST_RGB_WMASK_R			(1 << 11)
3262 #   define R500_INST_RGB_WMASK_G			(1 << 12)
3263 #   define R500_INST_RGB_WMASK_B			(1 << 13)
3264 #   define R500_INST_RGB_WMASK_RGB			(7 << 11)
3265 #   define R500_INST_ALPHA_WMASK			(1 << 14)
3266 #   define R500_INST_RGB_OMASK_R			(1 << 15)
3267 #   define R500_INST_RGB_OMASK_G			(1 << 16)
3268 #   define R500_INST_RGB_OMASK_B			(1 << 17)
3269 #   define R500_INST_RGB_OMASK_RGB			(7 << 15)
3270 #   define R500_INST_ALPHA_OMASK			(1 << 18)
3271 #   define R500_INST_RGB_CLAMP				(1 << 19)
3272 #   define R500_INST_ALPHA_CLAMP			(1 << 20)
3273 #   define R500_INST_ALU_RESULT_SEL			(1 << 21)
3274 #   define R500_INST_ALU_RESULT_SEL_RED			(0 << 21)
3275 #   define R500_INST_ALU_RESULT_SEL_ALPHA		(1 << 21)
3276 #   define R500_INST_ALPHA_PRED_INV			(1 << 22)
3277 #   define R500_INST_ALU_RESULT_OP_EQ			(0 << 23)
3278 #   define R500_INST_ALU_RESULT_OP_LT			(1 << 23)
3279 #   define R500_INST_ALU_RESULT_OP_GE			(2 << 23)
3280 #   define R500_INST_ALU_RESULT_OP_NE			(3 << 23)
3281 #   define R500_INST_ALPHA_PRED_SEL_NONE		(0 << 25)
3282 #   define R500_INST_ALPHA_PRED_SEL_RGBA		(1 << 25)
3283 #   define R500_INST_ALPHA_PRED_SEL_RRRR		(2 << 25)
3284 #   define R500_INST_ALPHA_PRED_SEL_GGGG		(3 << 25)
3285 #   define R500_INST_ALPHA_PRED_SEL_BBBB		(4 << 25)
3286 #   define R500_INST_ALPHA_PRED_SEL_AAAA		(5 << 25)
3287 /* Next four are guessed, documentation doesn't mention order. */
3288 #   define R500_INST_STAT_WE_R				(1 << 28)
3289 #   define R500_INST_STAT_WE_G				(1 << 29)
3290 #   define R500_INST_STAT_WE_B				(1 << 30)
3291 #   define R500_INST_STAT_WE_A				(1 << 31)
3292 
3293 /* note that these are 8 bit lengths, despite the offsets, at least for R500 */
3294 #define R500_US_CODE_ADDR				0x4630
3295 #   define R500_US_CODE_START_ADDR(x)			((x) << 0)
3296 #   define R500_US_CODE_END_ADDR(x)			((x) << 16)
3297 #define R500_US_CODE_OFFSET				0x4638
3298 #   define R500_US_CODE_OFFSET_ADDR(x)			((x) << 0)
3299 #define R500_US_CODE_RANGE				0x4634
3300 #   define R500_US_CODE_RANGE_ADDR(x)			((x) << 0)
3301 #   define R500_US_CODE_RANGE_SIZE(x)			((x) << 16)
3302 #define R500_US_CONFIG					0x4600
3303 #   define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO		(1 << 1)
3304 #define R500_US_FC_ADDR_0				0xa000
3305 #   define R500_FC_BOOL_ADDR(x)				((x) << 0)
3306 #   define R500_FC_INT_ADDR(x)				((x) << 8)
3307 #   define R500_FC_JUMP_ADDR(x)				((x) << 16)
3308 #   define R500_FC_JUMP_GLOBAL				(1 << 31)
3309 #define R500_US_FC_BOOL_CONST				0x4620
3310 #   define R500_FC_KBOOL(x)				(x)
3311 #define R500_US_FC_CTRL					0x4624
3312 #   define R500_FC_TEST_EN				(1 << 30)
3313 #   define R500_FC_FULL_FC_EN				(1 << 31)
3314 #define R500_US_FC_INST_0				0x9800
3315 #   define R500_FC_OP_JUMP				(0 << 0)
3316 #   define R500_FC_OP_LOOP				(1 << 0)
3317 #   define R500_FC_OP_ENDLOOP				(2 << 0)
3318 #   define R500_FC_OP_REP				(3 << 0)
3319 #   define R500_FC_OP_ENDREP				(4 << 0)
3320 #   define R500_FC_OP_BREAKLOOP				(5 << 0)
3321 #   define R500_FC_OP_BREAKREP				(6 << 0)
3322 #   define R500_FC_OP_CONTINUE				(7 << 0)
3323 #   define R500_FC_B_ELSE				(1 << 4)
3324 #   define R500_FC_JUMP_ANY				(1 << 5)
3325 #   define R500_FC_A_OP_NONE				(0 << 6)
3326 #   define R500_FC_A_OP_POP				(1 << 6)
3327 #   define R500_FC_A_OP_PUSH				(2 << 6)
3328 #   define R500_FC_JUMP_FUNC(x)				((x) << 8)
3329 #   define R500_FC_B_POP_CNT(x)				((x) << 16)
3330 #   define R500_FC_B_OP0_NONE				(0 << 24)
3331 #   define R500_FC_B_OP0_DECR				(1 << 24)
3332 #   define R500_FC_B_OP0_INCR				(2 << 24)
3333 #   define R500_FC_B_OP1_NONE				(0 << 26)
3334 #   define R500_FC_B_OP1_DECR				(1 << 26)
3335 #   define R500_FC_B_OP1_INCR				(2 << 26)
3336 #   define R500_FC_IGNORE_UNCOVERED			(1 << 28)
3337 #define R500_US_FC_INT_CONST_0				0x4c00
3338 #   define R500_FC_INT_CONST_KR(x)			((x) << 0)
3339 #   define R500_FC_INT_CONST_KG(x)			((x) << 8)
3340 #   define R500_FC_INT_CONST_KB(x)			((x) << 16)
3341 /* _0 through _15 */
3342 #define R500_US_FORMAT0_0				0x4640
3343 #   define R500_FORMAT_TXWIDTH(x)			((x) << 0)
3344 #   define R500_FORMAT_TXHEIGHT(x)			((x) << 11)
3345 #   define R500_FORMAT_TXDEPTH(x)			((x) << 22)
3346 #define R500_US_PIXSIZE					0x4604
3347 #   define R500_PIX_SIZE(x)				(x)
3348 #define R500_US_TEX_ADDR_0				0x9800
3349 #   define R500_TEX_SRC_ADDR(x)				((x) << 0)
3350 #   define R500_TEX_SRC_ADDR_REL			(1 << 7)
3351 #   define R500_TEX_SRC_S_SWIZ_R			(0 << 8)
3352 #   define R500_TEX_SRC_S_SWIZ_G			(1 << 8)
3353 #   define R500_TEX_SRC_S_SWIZ_B			(2 << 8)
3354 #   define R500_TEX_SRC_S_SWIZ_A			(3 << 8)
3355 #   define R500_TEX_SRC_T_SWIZ_R			(0 << 10)
3356 #   define R500_TEX_SRC_T_SWIZ_G			(1 << 10)
3357 #   define R500_TEX_SRC_T_SWIZ_B			(2 << 10)
3358 #   define R500_TEX_SRC_T_SWIZ_A			(3 << 10)
3359 #   define R500_TEX_SRC_R_SWIZ_R			(0 << 12)
3360 #   define R500_TEX_SRC_R_SWIZ_G			(1 << 12)
3361 #   define R500_TEX_SRC_R_SWIZ_B			(2 << 12)
3362 #   define R500_TEX_SRC_R_SWIZ_A			(3 << 12)
3363 #   define R500_TEX_SRC_Q_SWIZ_R			(0 << 14)
3364 #   define R500_TEX_SRC_Q_SWIZ_G			(1 << 14)
3365 #   define R500_TEX_SRC_Q_SWIZ_B			(2 << 14)
3366 #   define R500_TEX_SRC_Q_SWIZ_A			(3 << 14)
3367 #   define R500_TEX_DST_ADDR(x)				((x) << 16)
3368 #   define R500_TEX_DST_ADDR_REL			(1 << 23)
3369 #   define R500_TEX_DST_R_SWIZ_R			(0 << 24)
3370 #   define R500_TEX_DST_R_SWIZ_G			(1 << 24)
3371 #   define R500_TEX_DST_R_SWIZ_B			(2 << 24)
3372 #   define R500_TEX_DST_R_SWIZ_A			(3 << 24)
3373 #   define R500_TEX_DST_G_SWIZ_R			(0 << 26)
3374 #   define R500_TEX_DST_G_SWIZ_G			(1 << 26)
3375 #   define R500_TEX_DST_G_SWIZ_B			(2 << 26)
3376 #   define R500_TEX_DST_G_SWIZ_A			(3 << 26)
3377 #   define R500_TEX_DST_B_SWIZ_R			(0 << 28)
3378 #   define R500_TEX_DST_B_SWIZ_G			(1 << 28)
3379 #   define R500_TEX_DST_B_SWIZ_B			(2 << 28)
3380 #   define R500_TEX_DST_B_SWIZ_A			(3 << 28)
3381 #   define R500_TEX_DST_A_SWIZ_R			(0 << 30)
3382 #   define R500_TEX_DST_A_SWIZ_G			(1 << 30)
3383 #   define R500_TEX_DST_A_SWIZ_B			(2 << 30)
3384 #   define R500_TEX_DST_A_SWIZ_A			(3 << 30)
3385 #define R500_US_TEX_ADDR_DXDY_0				0xa000
3386 #   define R500_DX_ADDR(x)				((x) << 0)
3387 #   define R500_DX_ADDR_REL				(1 << 7)
3388 #   define R500_DX_S_SWIZ_R				(0 << 8)
3389 #   define R500_DX_S_SWIZ_G				(1 << 8)
3390 #   define R500_DX_S_SWIZ_B				(2 << 8)
3391 #   define R500_DX_S_SWIZ_A				(3 << 8)
3392 #   define R500_DX_T_SWIZ_R				(0 << 10)
3393 #   define R500_DX_T_SWIZ_G				(1 << 10)
3394 #   define R500_DX_T_SWIZ_B				(2 << 10)
3395 #   define R500_DX_T_SWIZ_A				(3 << 10)
3396 #   define R500_DX_R_SWIZ_R				(0 << 12)
3397 #   define R500_DX_R_SWIZ_G				(1 << 12)
3398 #   define R500_DX_R_SWIZ_B				(2 << 12)
3399 #   define R500_DX_R_SWIZ_A				(3 << 12)
3400 #   define R500_DX_Q_SWIZ_R				(0 << 14)
3401 #   define R500_DX_Q_SWIZ_G				(1 << 14)
3402 #   define R500_DX_Q_SWIZ_B				(2 << 14)
3403 #   define R500_DX_Q_SWIZ_A				(3 << 14)
3404 #   define R500_DY_ADDR(x)				((x) << 16)
3405 #   define R500_DY_ADDR_REL				(1 << 17)
3406 #   define R500_DY_S_SWIZ_R				(0 << 24)
3407 #   define R500_DY_S_SWIZ_G				(1 << 24)
3408 #   define R500_DY_S_SWIZ_B				(2 << 24)
3409 #   define R500_DY_S_SWIZ_A				(3 << 24)
3410 #   define R500_DY_T_SWIZ_R				(0 << 26)
3411 #   define R500_DY_T_SWIZ_G				(1 << 26)
3412 #   define R500_DY_T_SWIZ_B				(2 << 26)
3413 #   define R500_DY_T_SWIZ_A				(3 << 26)
3414 #   define R500_DY_R_SWIZ_R				(0 << 28)
3415 #   define R500_DY_R_SWIZ_G				(1 << 28)
3416 #   define R500_DY_R_SWIZ_B				(2 << 28)
3417 #   define R500_DY_R_SWIZ_A				(3 << 28)
3418 #   define R500_DY_Q_SWIZ_R				(0 << 30)
3419 #   define R500_DY_Q_SWIZ_G				(1 << 30)
3420 #   define R500_DY_Q_SWIZ_B				(2 << 30)
3421 #   define R500_DY_Q_SWIZ_A				(3 << 30)
3422 #define R500_US_TEX_INST_0				0x9000
3423 #   define R500_TEX_ID(x)				((x) << 16)
3424 #   define R500_TEX_INST_NOP				(0 << 22)
3425 #   define R500_TEX_INST_LD				(1 << 22)
3426 #   define R500_TEX_INST_TEXKILL			(2 << 22)
3427 #   define R500_TEX_INST_PROJ				(3 << 22)
3428 #   define R500_TEX_INST_LODBIAS			(4 << 22)
3429 #   define R500_TEX_INST_LOD				(5 << 22)
3430 #   define R500_TEX_INST_DXDY				(6 << 22)
3431 #   define R500_TEX_SEM_ACQUIRE_SHIFT			25
3432 #   define R500_TEX_SEM_ACQUIRE				(1 << R500_TEX_SEM_ACQUIRE_SHIFT)
3433 #   define R500_TEX_IGNORE_UNCOVERED			(1 << 26)
3434 #   define R500_TEX_UNSCALED				(1 << 27)
3435 #define R300_US_W_FMT					0x46b4
3436 #   define R300_W_FMT_W0				(0 << 0)
3437 #   define R300_W_FMT_W24				(1 << 0)
3438 #   define R300_W_FMT_W24FP				(2 << 0)
3439 #   define R300_W_SRC_US				(0 << 2)
3440 #   define R300_W_SRC_RAS				(1 << 2)
3441 
3442 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.
3443  * Two parameter dwords:
3444  * 0. VAP_VTX_FMT: The first parameter is not written to hardware
3445  * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
3446  */
3447 #define R300_PACKET3_3D_DRAW_VBUF           0x00002800
3448 
3449 /* Draw a primitive from immediate vertices in this packet
3450  * Up to 16382 dwords:
3451  * 0. VAP_VTX_FMT: The first parameter is not written to hardware
3452  * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
3453  * 2 to end: Up to 16380 dwords of vertex data.
3454  */
3455 #define R300_PACKET3_3D_DRAW_IMMD           0x00002900
3456 
3457 /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and
3458  * immediate vertices in this packet
3459  * Up to 16382 dwords:
3460  * 0. VAP_VTX_FMT: The first parameter is not written to hardware
3461  * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword.
3462  * 2 to end: Up to 16380 dwords of vertex data.
3463  */
3464 #define R300_PACKET3_3D_DRAW_INDX           0x00002A00
3465 
3466 
3467 /* Specify the full set of vertex arrays as (address, stride).
3468  * The first parameter is the number of vertex arrays specified.
3469  * The rest of the command is a variable length list of blocks, where
3470  * each block is three dwords long and specifies two arrays.
3471  * The first dword of a block is split into two words, the lower significant
3472  * word refers to the first array, the more significant word to the second
3473  * array in the block.
3474  * The low byte of each word contains the size of an array entry in dwords,
3475  * the high byte contains the stride of the array.
3476  * The second dword of a block contains the pointer to the first array,
3477  * the third dword of a block contains the pointer to the second array.
3478  * Note that if the total number of arrays is odd, the third dword of
3479  * the last block is omitted.
3480  */
3481 #define R300_PACKET3_3D_LOAD_VBPNTR         0x00002F00
3482 #   define R300_VC_FORCE_PREFETCH  (1 << 5)
3483 #   define R300_VBPNTR_SIZE0(x)    ((x) >> 2)
3484 #   define R300_VBPNTR_STRIDE0(x)  (((x) >> 2) << 8)
3485 #   define R300_VBPNTR_SIZE1(x)    (((x) >> 2) << 16)
3486 #   define R300_VBPNTR_STRIDE1(x)  (((x) >> 2) << 24)
3487 
3488 #define R300_PACKET3_3D_CLEAR_ZMASK         0x00003200
3489 #define R300_PACKET3_INDX_BUFFER            0x00003300
3490 #    define R300_INDX_BUFFER_DST_SHIFT          0
3491 #    define R300_INDX_BUFFER_SKIP_SHIFT         16
3492 #    define R300_INDX_BUFFER_ONE_REG_WR		(1<<31)
3493 
3494 /* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */
3495 #define R300_PACKET3_3D_DRAW_VBUF_2         0x00003400
3496 /* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */
3497 #define R300_PACKET3_3D_DRAW_IMMD_2         0x00003500
3498 /* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */
3499 #define R300_PACKET3_3D_DRAW_INDX_2         0x00003600
3500 
3501 /* Clears a portion of hierachical Z RAM
3502  * 3 dword parameters
3503  * 0. START
3504  * 1. COUNT: 13:0 (max is 0x3FFF)
3505  * 2. CLEAR_VALUE: Value to write into HIZ RAM.
3506  */
3507 #define R300_PACKET3_3D_CLEAR_HIZ           0x00003700
3508 #define R300_PACKET3_3D_CLEAR_CMASK         0x00003800
3509 
3510 /* Draws a set of primitives using vertex buffers pointed by the state data.
3511  * At least 2 Parameters:
3512  * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword.
3513  * 2 to end: Data or indices (see other 3D_DRAW_* packets for details)
3514  */
3515 #define R300_PACKET3_3D_DRAW_128            0x00003900
3516 
3517 /* END: Packet 3 commands */
3518 
3519 
3520 /* Color formats for 2d packets
3521  */
3522 #define R300_CP_COLOR_FORMAT_CI8	2
3523 #define R300_CP_COLOR_FORMAT_ARGB1555	3
3524 #define R300_CP_COLOR_FORMAT_RGB565	4
3525 #define R300_CP_COLOR_FORMAT_ARGB8888	6
3526 #define R300_CP_COLOR_FORMAT_RGB332	7
3527 #define R300_CP_COLOR_FORMAT_RGB8	9
3528 #define R300_CP_COLOR_FORMAT_ARGB4444	15
3529 
3530 /*
3531  * CP type-3 packets
3532  */
3533 #define RADEON_WAIT_UNTIL                   0x1720
3534 #       define RADEON_WAIT_CRTC_PFLIP       (1 << 0)
3535 #       define RADEON_WAIT_2D_IDLECLEAN     (1 << 16)
3536 #       define RADEON_WAIT_3D_IDLECLEAN     (1 << 17)
3537 #       define RADEON_WAIT_HOST_IDLECLEAN   (1 << 18)
3538 
3539 #define RADEON_CP_PACKET0                           0x00000000
3540 #define RADEON_CP_PACKET3                           0xC0000000
3541 
3542 #define RADEON_ONE_REG_WR        (1 << 15)
3543 
3544 #define CP_PACKET0(register, count) \
3545     (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2))
3546 
3547 #define CP_PACKET3(op, count) \
3548     (RADEON_CP_PACKET3 | (op) | ((count) << 16))
3549 
3550 #endif /* _R300_REG_H */
3551 
3552 /* *INDENT-ON* */
3553 
3554 /* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */
3555