| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 213 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local
283 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 154 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
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| D | SIInstrInfo.cpp | 4319 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
4328 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
7052 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
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| D | AMDGPUISelDAGToDAG.cpp | 600 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 134 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
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| D | SIInstrInfo.cpp | 3829 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
3840 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
6278 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD() local
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| D | AMDGPUISelDAGToDAG.cpp | 595 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1203 unsigned RCID; in getRegClassConstraint() local
1828 unsigned RCID = 0; in print() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 1083 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()
1139 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 900 unsigned RCID; in getRegClassConstraint() local
1747 unsigned RCID = 0; in print() local
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| D | TargetInstrInfo.cpp | 1401 unsigned RCID = 0; in createMIROperandComment() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 856 unsigned RCID; in getRegClassConstraint() local
1631 unsigned RCID = 0; in print() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1529 unsigned RCID; in handleSpecialFP() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1467 unsigned RCID; in handleSpecialFP() local
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1532 unsigned RCID; in handleSpecialFP() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 1255 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth()
1327 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 386 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1860 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
1881 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
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| D | AMDGPUISelDAGToDAG.cpp | 207 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in getOperandRegClass() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 246 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()
369 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()
2130 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 277 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods()
405 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods()
2286 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 932 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 669 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 579 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
|