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Searched defs:SrcVec (Results 1 – 25 of 29) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIcePhiLoweringImpl.h65 auto *SrcVec = llvm::cast<VariableVecOn32>(Src); in prelowerPhis32Bit() local
DIceTargetLoweringMIPS32.cpp5476 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
5492 auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); in lowerRet() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
DSIISelLowering.cpp3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp209 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
DAMDGPUInstructionSelector.cpp2810 Register SrcVec = normalizeVOP3PMask(Mask, Src0Reg, Src1Reg, ShufMask); in selectG_SHUFFLE_VECTOR() local
DSIISelLowering.cpp3754 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst() local
6718 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, in LowerINTRINSIC_WO_CHAIN() local
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp187 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg(); in RebuildVector() local
DSILowerControlFlow.cpp633 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in indirectSrc() local
/external/llvm/lib/IR/
DVerifier.cpp2318 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2341 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2364 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2387 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DVerifier.cpp2662 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2685 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2708 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2731 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/external/llvm-project/llvm/lib/IR/
DVerifier.cpp2804 bool SrcVec = SrcTy->isVectorTy(); in visitUIToFPInst() local
2827 bool SrcVec = SrcTy->isVectorTy(); in visitSIToFPInst() local
2850 bool SrcVec = SrcTy->isVectorTy(); in visitFPToUIInst() local
2873 bool SrcVec = SrcTy->isVectorTy(); in visitFPToSIInst() local
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2449 Register SrcVec = MI.getOperand(1).getReg(); in bitcastExtractVectorElt() local
2588 Register SrcVec = MI.getOperand(1).getReg(); in bitcastInsertVectorElt() local
3653 Register SrcVec = MI.getOperand(1).getReg(); in fewerElementsVectorExtractInsertVectorElt() local
5638 Register SrcVec = MI.getOperand(1).getReg(); in lowerExtractInsertVectorElt() local
5733 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp320 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
/external/llvm-project/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp337 Value *SrcVec = EI.getVectorOperand(); in visitExtractElementInst() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp419 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
/external/llvm-project/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1549 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1501 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp1553 GenericValue TempDst, TempSrc, SrcVec; in executeBitCastInst() local
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp546 SmallVectorImpl<int> &SrcIdx) { in buildHvxVectorReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp4239 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; in lowerShuffleVector() local
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5686 SDValue SrcVec = V1; in LowerVECTOR_SHUFFLE() local
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp10351 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp7325 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
9549 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute()
9808 SDValue SrcVec, IndicesVec; in LowerBUILD_VECTORAsVariablePermute() local
40345 SDValue SrcVec = N->getOperand(0).getOperand(0); in combineAnd() local
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp7617 SDValue SrcVec = SrcExtract.getOperand(0); in getFauxShuffleMask() local
9833 static SDValue createVariablePermute(MVT VT, SDValue SrcVec, SDValue IndicesVec, in createVariablePermute()
10094 SDValue SrcVec, IndicesVec; in LowerBUILD_VECTORAsVariablePermute() local
43636 SDValue SrcVec = N->getOperand(0).getOperand(0); in combineAnd() local

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