1 /************************************************************************** 2 * 3 * Copyright 2008 VMware, Inc. 4 * Copyright 2009-2010 VMware, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 **************************************************************************/ 28 29 #ifndef P_SHADER_TOKENS_H 30 #define P_SHADER_TOKENS_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 struct tgsi_header 38 { 39 unsigned HeaderSize : 8; 40 unsigned BodySize : 24; 41 }; 42 43 struct tgsi_processor 44 { 45 unsigned Processor : 4; /* PIPE_SHADER_ */ 46 unsigned Padding : 28; 47 }; 48 49 enum tgsi_token_type { 50 TGSI_TOKEN_TYPE_DECLARATION, 51 TGSI_TOKEN_TYPE_IMMEDIATE, 52 TGSI_TOKEN_TYPE_INSTRUCTION, 53 TGSI_TOKEN_TYPE_PROPERTY, 54 }; 55 56 struct tgsi_token 57 { 58 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_x */ 59 unsigned NrTokens : 8; /**< UINT */ 60 unsigned Padding : 20; 61 }; 62 63 enum tgsi_file_type { 64 TGSI_FILE_NULL, 65 TGSI_FILE_CONSTANT, 66 TGSI_FILE_INPUT, 67 TGSI_FILE_OUTPUT, 68 TGSI_FILE_TEMPORARY, 69 TGSI_FILE_SAMPLER, 70 TGSI_FILE_ADDRESS, 71 TGSI_FILE_IMMEDIATE, 72 TGSI_FILE_SYSTEM_VALUE, 73 TGSI_FILE_IMAGE, 74 TGSI_FILE_SAMPLER_VIEW, 75 TGSI_FILE_BUFFER, 76 TGSI_FILE_MEMORY, 77 TGSI_FILE_CONSTBUF, 78 TGSI_FILE_HW_ATOMIC, 79 TGSI_FILE_COUNT, /**< how many TGSI_FILE_ types */ 80 }; 81 82 83 #define TGSI_WRITEMASK_NONE 0x00 84 #define TGSI_WRITEMASK_X 0x01 85 #define TGSI_WRITEMASK_Y 0x02 86 #define TGSI_WRITEMASK_XY 0x03 87 #define TGSI_WRITEMASK_Z 0x04 88 #define TGSI_WRITEMASK_XZ 0x05 89 #define TGSI_WRITEMASK_YZ 0x06 90 #define TGSI_WRITEMASK_XYZ 0x07 91 #define TGSI_WRITEMASK_W 0x08 92 #define TGSI_WRITEMASK_XW 0x09 93 #define TGSI_WRITEMASK_YW 0x0A 94 #define TGSI_WRITEMASK_XYW 0x0B 95 #define TGSI_WRITEMASK_ZW 0x0C 96 #define TGSI_WRITEMASK_XZW 0x0D 97 #define TGSI_WRITEMASK_YZW 0x0E 98 #define TGSI_WRITEMASK_XYZW 0x0F 99 100 enum tgsi_interpolate_mode { 101 TGSI_INTERPOLATE_CONSTANT, 102 TGSI_INTERPOLATE_LINEAR, 103 TGSI_INTERPOLATE_PERSPECTIVE, 104 TGSI_INTERPOLATE_COLOR, /* special color case for smooth/flat */ 105 TGSI_INTERPOLATE_COUNT, 106 }; 107 108 enum tgsi_interpolate_loc { 109 TGSI_INTERPOLATE_LOC_CENTER, 110 TGSI_INTERPOLATE_LOC_CENTROID, 111 TGSI_INTERPOLATE_LOC_SAMPLE, 112 TGSI_INTERPOLATE_LOC_COUNT, 113 }; 114 115 #define TGSI_CYLINDRICAL_WRAP_X (1 << 0) 116 #define TGSI_CYLINDRICAL_WRAP_Y (1 << 1) 117 #define TGSI_CYLINDRICAL_WRAP_Z (1 << 2) 118 #define TGSI_CYLINDRICAL_WRAP_W (1 << 3) 119 120 enum tgsi_memory_type { 121 TGSI_MEMORY_TYPE_GLOBAL, /* OpenCL global */ 122 TGSI_MEMORY_TYPE_SHARED, /* OpenCL local / GLSL shared */ 123 TGSI_MEMORY_TYPE_PRIVATE, /* OpenCL private */ 124 TGSI_MEMORY_TYPE_INPUT, /* OpenCL kernel input params */ 125 TGSI_MEMORY_TYPE_COUNT, 126 }; 127 128 struct tgsi_declaration 129 { 130 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_DECLARATION */ 131 unsigned NrTokens : 8; /**< UINT */ 132 unsigned File : 4; /**< one of TGSI_FILE_x */ 133 unsigned UsageMask : 4; /**< bitmask of TGSI_WRITEMASK_x flags */ 134 unsigned Dimension : 1; /**< any extra dimension info? */ 135 unsigned Semantic : 1; /**< BOOL, any semantic info? */ 136 unsigned Interpolate : 1; /**< any interpolation info? */ 137 unsigned Invariant : 1; /**< invariant optimization? */ 138 unsigned Local : 1; /**< optimize as subroutine local variable? */ 139 unsigned Array : 1; /**< extra array info? */ 140 unsigned Atomic : 1; /**< atomic only? for TGSI_FILE_BUFFER */ 141 unsigned MemType : 2; /**< TGSI_MEMORY_TYPE_x for TGSI_FILE_MEMORY */ 142 unsigned Padding : 3; 143 }; 144 145 struct tgsi_declaration_range 146 { 147 unsigned First : 16; /**< UINT */ 148 unsigned Last : 16; /**< UINT */ 149 }; 150 151 struct tgsi_declaration_dimension 152 { 153 unsigned Index2D:16; /**< UINT */ 154 unsigned Padding:16; 155 }; 156 157 struct tgsi_declaration_interp 158 { 159 unsigned Interpolate : 4; /**< one of TGSI_INTERPOLATE_x */ 160 unsigned Location : 2; /**< one of TGSI_INTERPOLATE_LOC_x */ 161 unsigned CylindricalWrap:4; /**< TGSI_CYLINDRICAL_WRAP_x flags */ 162 unsigned Padding : 22; 163 }; 164 165 enum tgsi_semantic { 166 TGSI_SEMANTIC_POSITION, 167 TGSI_SEMANTIC_COLOR, 168 TGSI_SEMANTIC_BCOLOR, /**< back-face color */ 169 TGSI_SEMANTIC_FOG, 170 TGSI_SEMANTIC_PSIZE, 171 TGSI_SEMANTIC_GENERIC, 172 TGSI_SEMANTIC_NORMAL, 173 TGSI_SEMANTIC_FACE, 174 TGSI_SEMANTIC_EDGEFLAG, 175 TGSI_SEMANTIC_PRIMID, 176 TGSI_SEMANTIC_INSTANCEID, /**< doesn't include start_instance */ 177 TGSI_SEMANTIC_VERTEXID, 178 TGSI_SEMANTIC_STENCIL, 179 TGSI_SEMANTIC_CLIPDIST, 180 TGSI_SEMANTIC_CLIPVERTEX, 181 TGSI_SEMANTIC_GRID_SIZE, /**< grid size in blocks */ 182 TGSI_SEMANTIC_BLOCK_ID, /**< id of the current block */ 183 TGSI_SEMANTIC_BLOCK_SIZE, /**< block size in threads */ 184 TGSI_SEMANTIC_THREAD_ID, /**< block-relative id of the current thread */ 185 TGSI_SEMANTIC_TEXCOORD, /**< texture or sprite coordinates */ 186 TGSI_SEMANTIC_PCOORD, /**< point sprite coordinate */ 187 TGSI_SEMANTIC_VIEWPORT_INDEX, /**< viewport index */ 188 TGSI_SEMANTIC_LAYER, /**< layer (rendertarget index) */ 189 TGSI_SEMANTIC_SAMPLEID, 190 TGSI_SEMANTIC_SAMPLEPOS, 191 TGSI_SEMANTIC_SAMPLEMASK, 192 TGSI_SEMANTIC_INVOCATIONID, 193 TGSI_SEMANTIC_VERTEXID_NOBASE, 194 TGSI_SEMANTIC_BASEVERTEX, 195 TGSI_SEMANTIC_PATCH, /**< generic per-patch semantic */ 196 TGSI_SEMANTIC_TESSCOORD, /**< coordinate being processed by tess */ 197 TGSI_SEMANTIC_TESSOUTER, /**< outer tessellation levels */ 198 TGSI_SEMANTIC_TESSINNER, /**< inner tessellation levels */ 199 TGSI_SEMANTIC_VERTICESIN, /**< number of input vertices */ 200 TGSI_SEMANTIC_HELPER_INVOCATION, /**< current invocation is helper */ 201 TGSI_SEMANTIC_BASEINSTANCE, 202 TGSI_SEMANTIC_DRAWID, 203 TGSI_SEMANTIC_WORK_DIM, /**< opencl get_work_dim value */ 204 TGSI_SEMANTIC_SUBGROUP_SIZE, 205 TGSI_SEMANTIC_SUBGROUP_INVOCATION, 206 TGSI_SEMANTIC_SUBGROUP_EQ_MASK, 207 TGSI_SEMANTIC_SUBGROUP_GE_MASK, 208 TGSI_SEMANTIC_SUBGROUP_GT_MASK, 209 TGSI_SEMANTIC_SUBGROUP_LE_MASK, 210 TGSI_SEMANTIC_SUBGROUP_LT_MASK, 211 TGSI_SEMANTIC_CS_USER_DATA_AMD, 212 TGSI_SEMANTIC_VIEWPORT_MASK, 213 TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL, /**< from set_tess_state */ 214 TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL, /**< from set_tess_state */ 215 TGSI_SEMANTIC_COUNT, /**< number of semantic values */ 216 }; 217 218 struct tgsi_declaration_semantic 219 { 220 unsigned Name : 8; /**< one of TGSI_SEMANTIC_x */ 221 unsigned Index : 16; /**< UINT */ 222 unsigned StreamX : 2; /**< vertex stream (for GS output) */ 223 unsigned StreamY : 2; 224 unsigned StreamZ : 2; 225 unsigned StreamW : 2; 226 }; 227 228 struct tgsi_declaration_image { 229 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 230 unsigned Raw : 1; 231 unsigned Writable : 1; 232 unsigned Format : 10; /**< one of PIPE_FORMAT_ */ 233 unsigned Padding : 12; 234 }; 235 236 enum tgsi_return_type { 237 TGSI_RETURN_TYPE_UNORM = 0, 238 TGSI_RETURN_TYPE_SNORM, 239 TGSI_RETURN_TYPE_SINT, 240 TGSI_RETURN_TYPE_UINT, 241 TGSI_RETURN_TYPE_FLOAT, 242 TGSI_RETURN_TYPE_UNKNOWN, 243 TGSI_RETURN_TYPE_COUNT 244 }; 245 246 struct tgsi_declaration_sampler_view { 247 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 248 unsigned ReturnTypeX : 6; /**< one of enum tgsi_return_type */ 249 unsigned ReturnTypeY : 6; /**< one of enum tgsi_return_type */ 250 unsigned ReturnTypeZ : 6; /**< one of enum tgsi_return_type */ 251 unsigned ReturnTypeW : 6; /**< one of enum tgsi_return_type */ 252 }; 253 254 struct tgsi_declaration_array { 255 unsigned ArrayID : 10; 256 unsigned Padding : 22; 257 }; 258 259 enum tgsi_imm_type { 260 TGSI_IMM_FLOAT32, 261 TGSI_IMM_UINT32, 262 TGSI_IMM_INT32, 263 TGSI_IMM_FLOAT64, 264 TGSI_IMM_UINT64, 265 TGSI_IMM_INT64, 266 }; 267 268 struct tgsi_immediate 269 { 270 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */ 271 unsigned NrTokens : 14; /**< UINT */ 272 unsigned DataType : 4; /**< one of TGSI_IMM_x */ 273 unsigned Padding : 10; 274 }; 275 276 union tgsi_immediate_data 277 { 278 float Float; 279 unsigned Uint; 280 int Int; 281 }; 282 283 enum tgsi_property_name { 284 TGSI_PROPERTY_GS_INPUT_PRIM, 285 TGSI_PROPERTY_GS_OUTPUT_PRIM, 286 TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES, 287 TGSI_PROPERTY_FS_COORD_ORIGIN, 288 TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, 289 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 290 TGSI_PROPERTY_FS_DEPTH_LAYOUT, 291 TGSI_PROPERTY_VS_PROHIBIT_UCPS, 292 TGSI_PROPERTY_GS_INVOCATIONS, 293 TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, 294 TGSI_PROPERTY_TCS_VERTICES_OUT, 295 TGSI_PROPERTY_TES_PRIM_MODE, 296 TGSI_PROPERTY_TES_SPACING, 297 TGSI_PROPERTY_TES_VERTEX_ORDER_CW, 298 TGSI_PROPERTY_TES_POINT_MODE, 299 TGSI_PROPERTY_NUM_CLIPDIST_ENABLED, 300 TGSI_PROPERTY_NUM_CULLDIST_ENABLED, 301 TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 302 TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 303 TGSI_PROPERTY_NEXT_SHADER, 304 TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 305 TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 306 TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 307 TGSI_PROPERTY_MUL_ZERO_WINS, 308 TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, 309 TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, 310 TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE, 311 TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED, 312 TGSI_PROPERTY_COUNT, 313 }; 314 315 struct tgsi_property { 316 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_PROPERTY */ 317 unsigned NrTokens : 8; /**< UINT */ 318 unsigned PropertyName : 8; /**< one of TGSI_PROPERTY */ 319 unsigned Padding : 12; 320 }; 321 322 enum tgsi_fs_coord_origin { 323 TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 324 TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 325 }; 326 327 enum tgsi_fs_coord_pixcenter { 328 TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 329 TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 330 }; 331 332 enum tgsi_fs_depth_layout { 333 TGSI_FS_DEPTH_LAYOUT_NONE, 334 TGSI_FS_DEPTH_LAYOUT_ANY, 335 TGSI_FS_DEPTH_LAYOUT_GREATER, 336 TGSI_FS_DEPTH_LAYOUT_LESS, 337 TGSI_FS_DEPTH_LAYOUT_UNCHANGED, 338 }; 339 340 struct tgsi_property_data { 341 unsigned Data; 342 }; 343 344 /* TGSI opcodes. 345 * 346 * For more information on semantics of opcodes and 347 * which APIs are known to use which opcodes, see 348 * gallium/docs/source/tgsi.rst 349 */ 350 enum tgsi_opcode { 351 TGSI_OPCODE_ARL = 0, 352 TGSI_OPCODE_MOV = 1, 353 TGSI_OPCODE_LIT = 2, 354 TGSI_OPCODE_RCP = 3, 355 TGSI_OPCODE_RSQ = 4, 356 TGSI_OPCODE_EXP = 5, 357 TGSI_OPCODE_LOG = 6, 358 TGSI_OPCODE_MUL = 7, 359 TGSI_OPCODE_ADD = 8, 360 TGSI_OPCODE_DP3 = 9, 361 TGSI_OPCODE_DP4 = 10, 362 TGSI_OPCODE_DST = 11, 363 TGSI_OPCODE_MIN = 12, 364 TGSI_OPCODE_MAX = 13, 365 TGSI_OPCODE_SLT = 14, 366 TGSI_OPCODE_SGE = 15, 367 TGSI_OPCODE_MAD = 16, 368 TGSI_OPCODE_TEX_LZ = 17, 369 TGSI_OPCODE_LRP = 18, 370 TGSI_OPCODE_FMA = 19, 371 TGSI_OPCODE_SQRT = 20, 372 TGSI_OPCODE_LDEXP = 21, 373 TGSI_OPCODE_F2U64 = 22, 374 TGSI_OPCODE_F2I64 = 23, 375 TGSI_OPCODE_FRC = 24, 376 TGSI_OPCODE_TXF_LZ = 25, 377 TGSI_OPCODE_FLR = 26, 378 TGSI_OPCODE_ROUND = 27, 379 TGSI_OPCODE_EX2 = 28, 380 TGSI_OPCODE_LG2 = 29, 381 TGSI_OPCODE_POW = 30, 382 TGSI_OPCODE_DEMOTE = 31, 383 TGSI_OPCODE_U2I64 = 32, 384 TGSI_OPCODE_CLOCK = 33, 385 TGSI_OPCODE_I2I64 = 34, 386 TGSI_OPCODE_READ_HELPER = 35, 387 TGSI_OPCODE_COS = 36, 388 TGSI_OPCODE_DDX = 37, 389 TGSI_OPCODE_DDY = 38, 390 TGSI_OPCODE_KILL = 39 /* unconditional */, 391 TGSI_OPCODE_PK2H = 40, 392 TGSI_OPCODE_PK2US = 41, 393 TGSI_OPCODE_PK4B = 42, 394 TGSI_OPCODE_PK4UB = 43, 395 TGSI_OPCODE_D2U64 = 44, 396 TGSI_OPCODE_SEQ = 45, 397 TGSI_OPCODE_D2I64 = 46, 398 TGSI_OPCODE_SGT = 47, 399 TGSI_OPCODE_SIN = 48, 400 TGSI_OPCODE_SLE = 49, 401 TGSI_OPCODE_SNE = 50, 402 TGSI_OPCODE_U642D = 51, 403 TGSI_OPCODE_TEX = 52, 404 TGSI_OPCODE_TXD = 53, 405 TGSI_OPCODE_TXP = 54, 406 TGSI_OPCODE_UP2H = 55, 407 TGSI_OPCODE_UP2US = 56, 408 TGSI_OPCODE_UP4B = 57, 409 TGSI_OPCODE_UP4UB = 58, 410 TGSI_OPCODE_U642F = 59, 411 TGSI_OPCODE_I642F = 60, 412 TGSI_OPCODE_ARR = 61, 413 TGSI_OPCODE_I642D = 62, 414 TGSI_OPCODE_CAL = 63, 415 TGSI_OPCODE_RET = 64, 416 TGSI_OPCODE_SSG = 65 /* SGN */, 417 TGSI_OPCODE_CMP = 66, 418 /* gap */ 419 TGSI_OPCODE_TXB = 68, 420 TGSI_OPCODE_FBFETCH = 69, 421 TGSI_OPCODE_DIV = 70, 422 TGSI_OPCODE_DP2 = 71, 423 TGSI_OPCODE_TXL = 72, 424 TGSI_OPCODE_BRK = 73, 425 TGSI_OPCODE_IF = 74, 426 TGSI_OPCODE_UIF = 75, 427 TGSI_OPCODE_READ_INVOC = 76, 428 TGSI_OPCODE_ELSE = 77, 429 TGSI_OPCODE_ENDIF = 78, 430 TGSI_OPCODE_DDX_FINE = 79, 431 TGSI_OPCODE_DDY_FINE = 80, 432 /* gap */ 433 TGSI_OPCODE_CEIL = 83, 434 TGSI_OPCODE_I2F = 84, 435 TGSI_OPCODE_NOT = 85, 436 TGSI_OPCODE_TRUNC = 86, 437 TGSI_OPCODE_SHL = 87, 438 TGSI_OPCODE_BALLOT = 88, 439 TGSI_OPCODE_AND = 89, 440 TGSI_OPCODE_OR = 90, 441 TGSI_OPCODE_MOD = 91, 442 TGSI_OPCODE_XOR = 92, 443 /* gap */ 444 TGSI_OPCODE_TXF = 94, 445 TGSI_OPCODE_TXQ = 95, 446 TGSI_OPCODE_CONT = 96, 447 TGSI_OPCODE_EMIT = 97, 448 TGSI_OPCODE_ENDPRIM = 98, 449 TGSI_OPCODE_BGNLOOP = 99, 450 TGSI_OPCODE_BGNSUB = 100, 451 TGSI_OPCODE_ENDLOOP = 101, 452 TGSI_OPCODE_ENDSUB = 102, 453 TGSI_OPCODE_ATOMFADD = 103, 454 TGSI_OPCODE_TXQS = 104, 455 TGSI_OPCODE_RESQ = 105, 456 TGSI_OPCODE_READ_FIRST = 106, 457 TGSI_OPCODE_NOP = 107, 458 459 TGSI_OPCODE_FSEQ = 108, 460 TGSI_OPCODE_FSGE = 109, 461 TGSI_OPCODE_FSLT = 110, 462 TGSI_OPCODE_FSNE = 111, 463 464 TGSI_OPCODE_MEMBAR = 112, 465 /* gap */ 466 TGSI_OPCODE_KILL_IF = 116 /* conditional kill */, 467 TGSI_OPCODE_END = 117 /* aka HALT */, 468 TGSI_OPCODE_DFMA = 118, 469 TGSI_OPCODE_F2I = 119, 470 TGSI_OPCODE_IDIV = 120, 471 TGSI_OPCODE_IMAX = 121, 472 TGSI_OPCODE_IMIN = 122, 473 TGSI_OPCODE_INEG = 123, 474 TGSI_OPCODE_ISGE = 124, 475 TGSI_OPCODE_ISHR = 125, 476 TGSI_OPCODE_ISLT = 126, 477 TGSI_OPCODE_F2U = 127, 478 TGSI_OPCODE_U2F = 128, 479 TGSI_OPCODE_UADD = 129, 480 TGSI_OPCODE_UDIV = 130, 481 TGSI_OPCODE_UMAD = 131, 482 TGSI_OPCODE_UMAX = 132, 483 TGSI_OPCODE_UMIN = 133, 484 TGSI_OPCODE_UMOD = 134, 485 TGSI_OPCODE_UMUL = 135, 486 TGSI_OPCODE_USEQ = 136, 487 TGSI_OPCODE_USGE = 137, 488 TGSI_OPCODE_USHR = 138, 489 TGSI_OPCODE_USLT = 139, 490 TGSI_OPCODE_USNE = 140, 491 TGSI_OPCODE_SWITCH = 141, 492 TGSI_OPCODE_CASE = 142, 493 TGSI_OPCODE_DEFAULT = 143, 494 TGSI_OPCODE_ENDSWITCH = 144, 495 496 /* resource related opcodes */ 497 TGSI_OPCODE_SAMPLE = 145, 498 TGSI_OPCODE_SAMPLE_I = 146, 499 TGSI_OPCODE_SAMPLE_I_MS = 147, 500 TGSI_OPCODE_SAMPLE_B = 148, 501 TGSI_OPCODE_SAMPLE_C = 149, 502 TGSI_OPCODE_SAMPLE_C_LZ = 150, 503 TGSI_OPCODE_SAMPLE_D = 151, 504 TGSI_OPCODE_SAMPLE_L = 152, 505 TGSI_OPCODE_GATHER4 = 153, 506 TGSI_OPCODE_SVIEWINFO = 154, 507 TGSI_OPCODE_SAMPLE_POS = 155, 508 TGSI_OPCODE_SAMPLE_INFO = 156, 509 510 TGSI_OPCODE_UARL = 157, 511 TGSI_OPCODE_UCMP = 158, 512 TGSI_OPCODE_IABS = 159, 513 TGSI_OPCODE_ISSG = 160, 514 515 TGSI_OPCODE_LOAD = 161, 516 TGSI_OPCODE_STORE = 162, 517 TGSI_OPCODE_IMG2HND = 163, 518 TGSI_OPCODE_SAMP2HND = 164, 519 /* gap */ 520 TGSI_OPCODE_BARRIER = 166, 521 522 TGSI_OPCODE_ATOMUADD = 167, 523 TGSI_OPCODE_ATOMXCHG = 168, 524 TGSI_OPCODE_ATOMCAS = 169, 525 TGSI_OPCODE_ATOMAND = 170, 526 TGSI_OPCODE_ATOMOR = 171, 527 TGSI_OPCODE_ATOMXOR = 172, 528 TGSI_OPCODE_ATOMUMIN = 173, 529 TGSI_OPCODE_ATOMUMAX = 174, 530 TGSI_OPCODE_ATOMIMIN = 175, 531 TGSI_OPCODE_ATOMIMAX = 176, 532 533 /* to be used for shadow cube map compares */ 534 TGSI_OPCODE_TEX2 = 177, 535 TGSI_OPCODE_TXB2 = 178, 536 TGSI_OPCODE_TXL2 = 179, 537 538 TGSI_OPCODE_IMUL_HI = 180, 539 TGSI_OPCODE_UMUL_HI = 181, 540 541 TGSI_OPCODE_TG4 = 182, 542 543 TGSI_OPCODE_LODQ = 183, 544 545 TGSI_OPCODE_IBFE = 184, 546 TGSI_OPCODE_UBFE = 185, 547 TGSI_OPCODE_BFI = 186, 548 TGSI_OPCODE_BREV = 187, 549 TGSI_OPCODE_POPC = 188, 550 TGSI_OPCODE_LSB = 189, 551 TGSI_OPCODE_IMSB = 190, 552 TGSI_OPCODE_UMSB = 191, 553 554 TGSI_OPCODE_INTERP_CENTROID = 192, 555 TGSI_OPCODE_INTERP_SAMPLE = 193, 556 TGSI_OPCODE_INTERP_OFFSET = 194, 557 558 /* sm5 marked opcodes are supported in D3D11 optionally - also DMOV, DMOVC */ 559 TGSI_OPCODE_F2D = 195 /* SM5 */, 560 TGSI_OPCODE_D2F = 196, 561 TGSI_OPCODE_DABS = 197, 562 TGSI_OPCODE_DNEG = 198 /* SM5 */, 563 TGSI_OPCODE_DADD = 199 /* SM5 */, 564 TGSI_OPCODE_DMUL = 200 /* SM5 */, 565 TGSI_OPCODE_DMAX = 201 /* SM5 */, 566 TGSI_OPCODE_DMIN = 202 /* SM5 */, 567 TGSI_OPCODE_DSLT = 203 /* SM5 */, 568 TGSI_OPCODE_DSGE = 204 /* SM5 */, 569 TGSI_OPCODE_DSEQ = 205 /* SM5 */, 570 TGSI_OPCODE_DSNE = 206 /* SM5 */, 571 TGSI_OPCODE_DRCP = 207 /* eg, cayman */, 572 TGSI_OPCODE_DSQRT = 208 /* eg, cayman also has DRSQ */, 573 TGSI_OPCODE_DMAD = 209, 574 TGSI_OPCODE_DFRAC = 210 /* eg, cayman */, 575 TGSI_OPCODE_DLDEXP = 211 /* eg, cayman */, 576 TGSI_OPCODE_DFRACEXP = 212 /* eg, cayman */, 577 TGSI_OPCODE_D2I = 213, 578 TGSI_OPCODE_I2D = 214, 579 TGSI_OPCODE_D2U = 215, 580 TGSI_OPCODE_U2D = 216, 581 TGSI_OPCODE_DRSQ = 217 /* eg, cayman also has DRSQ */, 582 TGSI_OPCODE_DTRUNC = 218 /* nvc0 */, 583 TGSI_OPCODE_DCEIL = 219 /* nvc0 */, 584 TGSI_OPCODE_DFLR = 220 /* nvc0 */, 585 TGSI_OPCODE_DROUND = 221 /* nvc0 */, 586 TGSI_OPCODE_DSSG = 222, 587 588 TGSI_OPCODE_VOTE_ANY = 223, 589 TGSI_OPCODE_VOTE_ALL = 224, 590 TGSI_OPCODE_VOTE_EQ = 225, 591 592 TGSI_OPCODE_U64SEQ = 226, 593 TGSI_OPCODE_U64SNE = 227, 594 TGSI_OPCODE_I64SLT = 228, 595 TGSI_OPCODE_U64SLT = 229, 596 TGSI_OPCODE_I64SGE = 230, 597 TGSI_OPCODE_U64SGE = 231, 598 599 TGSI_OPCODE_I64MIN = 232, 600 TGSI_OPCODE_U64MIN = 233, 601 TGSI_OPCODE_I64MAX = 234, 602 TGSI_OPCODE_U64MAX = 235, 603 604 TGSI_OPCODE_I64ABS = 236, 605 TGSI_OPCODE_I64SSG = 237, 606 TGSI_OPCODE_I64NEG = 238, 607 608 TGSI_OPCODE_U64ADD = 239, 609 TGSI_OPCODE_U64MUL = 240, 610 TGSI_OPCODE_U64SHL = 241, 611 TGSI_OPCODE_I64SHR = 242, 612 TGSI_OPCODE_U64SHR = 243, 613 614 TGSI_OPCODE_I64DIV = 244, 615 TGSI_OPCODE_U64DIV = 245, 616 TGSI_OPCODE_I64MOD = 246, 617 TGSI_OPCODE_U64MOD = 247, 618 619 TGSI_OPCODE_DDIV = 248, 620 621 TGSI_OPCODE_LOD = 249, 622 623 TGSI_OPCODE_ATOMINC_WRAP = 250, 624 TGSI_OPCODE_ATOMDEC_WRAP = 251, 625 626 TGSI_OPCODE_LAST = 252, 627 }; 628 629 630 /** 631 * Opcode is the operation code to execute. A given operation defines the 632 * semantics how the source registers (if any) are interpreted and what is 633 * written to the destination registers (if any) as a result of execution. 634 * 635 * NumDstRegs and NumSrcRegs is the number of destination and source registers, 636 * respectively. For a given operation code, those numbers are fixed and are 637 * present here only for convenience. 638 * 639 * Saturate controls how are final results in destination registers modified. 640 */ 641 642 struct tgsi_instruction 643 { 644 unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */ 645 unsigned NrTokens : 8; /* UINT */ 646 unsigned Opcode : 8; /* TGSI_OPCODE_ */ 647 unsigned Saturate : 1; /* BOOL */ 648 unsigned NumDstRegs : 2; /* UINT */ 649 unsigned NumSrcRegs : 4; /* UINT */ 650 unsigned Label : 1; 651 unsigned Texture : 1; 652 unsigned Memory : 1; 653 unsigned Precise : 1; 654 unsigned Padding : 1; 655 }; 656 657 /* 658 * If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows. 659 * 660 * If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows. 661 * if texture instruction has a number of offsets, 662 * then tgsi_instruction::Texture::NumOffset of tgsi_texture_offset follow. 663 * 664 * Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow. 665 * 666 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow. 667 * 668 * tgsi_instruction::NrTokens contains the total number of words that make the 669 * instruction, including the instruction word. 670 */ 671 672 enum tgsi_swizzle { 673 TGSI_SWIZZLE_X, 674 TGSI_SWIZZLE_Y, 675 TGSI_SWIZZLE_Z, 676 TGSI_SWIZZLE_W, 677 }; 678 679 struct tgsi_instruction_label 680 { 681 unsigned Label : 24; /* UINT */ 682 unsigned Padding : 8; 683 }; 684 685 enum tgsi_texture_type { 686 TGSI_TEXTURE_BUFFER, 687 TGSI_TEXTURE_1D, 688 TGSI_TEXTURE_2D, 689 TGSI_TEXTURE_3D, 690 TGSI_TEXTURE_CUBE, 691 TGSI_TEXTURE_RECT, 692 TGSI_TEXTURE_SHADOW1D, 693 TGSI_TEXTURE_SHADOW2D, 694 TGSI_TEXTURE_SHADOWRECT, 695 TGSI_TEXTURE_1D_ARRAY, 696 TGSI_TEXTURE_2D_ARRAY, 697 TGSI_TEXTURE_SHADOW1D_ARRAY, 698 TGSI_TEXTURE_SHADOW2D_ARRAY, 699 TGSI_TEXTURE_SHADOWCUBE, 700 TGSI_TEXTURE_2D_MSAA, 701 TGSI_TEXTURE_2D_ARRAY_MSAA, 702 TGSI_TEXTURE_CUBE_ARRAY, 703 TGSI_TEXTURE_SHADOWCUBE_ARRAY, 704 TGSI_TEXTURE_UNKNOWN, 705 TGSI_TEXTURE_COUNT, 706 }; 707 708 struct tgsi_instruction_texture 709 { 710 unsigned Texture : 8; /* TGSI_TEXTURE_ */ 711 unsigned NumOffsets : 4; 712 unsigned ReturnType : 3; /* TGSI_RETURN_TYPE_x */ 713 unsigned Padding : 17; 714 }; 715 716 /* for texture offsets in GLSL and DirectX. 717 * Generally these always come from TGSI_FILE_IMMEDIATE, 718 * however DX11 appears to have the capability to do 719 * non-constant texture offsets. 720 */ 721 struct tgsi_texture_offset 722 { 723 int Index : 16; 724 unsigned File : 4; /**< one of TGSI_FILE_x */ 725 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */ 726 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */ 727 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */ 728 unsigned Padding : 6; 729 }; 730 731 /** 732 * File specifies the register array to access. 733 * 734 * Index specifies the element number of a register in the register file. 735 * 736 * If Indirect is TRUE, Index should be offset by the X component of the indirect 737 * register that follows. The register can be now fetched into local storage 738 * for further processing. 739 * 740 * If Negate is TRUE, all components of the fetched register are negated. 741 * 742 * The fetched register components are swizzled according to SwizzleX, SwizzleY, 743 * SwizzleZ and SwizzleW. 744 * 745 */ 746 747 struct tgsi_src_register 748 { 749 unsigned File : 4; /* TGSI_FILE_ */ 750 unsigned Indirect : 1; /* BOOL */ 751 unsigned Dimension : 1; /* BOOL */ 752 int Index : 16; /* SINT */ 753 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */ 754 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */ 755 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */ 756 unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */ 757 unsigned Absolute : 1; /* BOOL */ 758 unsigned Negate : 1; /* BOOL */ 759 }; 760 761 /** 762 * If tgsi_src_register::Indirect is TRUE, tgsi_ind_register follows. 763 * 764 * File, Index and Swizzle are handled the same as in tgsi_src_register. 765 * 766 * If ArrayID is zero the whole register file might be indirectly addressed, 767 * if not only the Declaration with this ArrayID is accessed by this operand. 768 * 769 */ 770 771 struct tgsi_ind_register 772 { 773 unsigned File : 4; /* TGSI_FILE_ */ 774 int Index : 16; /* SINT */ 775 unsigned Swizzle : 2; /* TGSI_SWIZZLE_ */ 776 unsigned ArrayID : 10; /* UINT */ 777 }; 778 779 /** 780 * If tgsi_src_register::Dimension is TRUE, tgsi_dimension follows. 781 */ 782 783 struct tgsi_dimension 784 { 785 unsigned Indirect : 1; /* BOOL */ 786 unsigned Dimension : 1; /* BOOL */ 787 unsigned Padding : 14; 788 int Index : 16; /* SINT */ 789 }; 790 791 struct tgsi_dst_register 792 { 793 unsigned File : 4; /* TGSI_FILE_ */ 794 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */ 795 unsigned Indirect : 1; /* BOOL */ 796 unsigned Dimension : 1; /* BOOL */ 797 int Index : 16; /* SINT */ 798 unsigned Padding : 6; 799 }; 800 801 #define TGSI_MEMORY_COHERENT (1 << 0) 802 #define TGSI_MEMORY_RESTRICT (1 << 1) 803 #define TGSI_MEMORY_VOLATILE (1 << 2) 804 /* The "stream" cache policy will minimize memory cache usage if other 805 * memory operations need the cache. 806 */ 807 #define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3) 808 809 /** 810 * Specifies the type of memory access to do for the LOAD/STORE instruction. 811 */ 812 struct tgsi_instruction_memory 813 { 814 unsigned Qualifier : 4; /* TGSI_MEMORY_ */ 815 unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */ 816 unsigned Format : 10; /* only for images: PIPE_FORMAT_ */ 817 unsigned Padding : 10; 818 }; 819 820 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0) 821 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1) 822 #define TGSI_MEMBAR_SHADER_IMAGE (1 << 2) 823 #define TGSI_MEMBAR_SHARED (1 << 3) 824 #define TGSI_MEMBAR_THREAD_GROUP (1 << 4) 825 826 #ifdef __cplusplus 827 } 828 #endif 829 830 #endif /* P_SHADER_TOKENS_H */ 831