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Searched defs:TRC (Results 1 – 25 of 55) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp133 const TargetRegisterClass *TRC) { in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
435 const TargetRegisterClass *TRC) { in createExtractSubreg()
/external/llvm-project/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp133 const TargetRegisterClass *TRC) { in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
435 const TargetRegisterClass *TRC) { in createExtractSubreg()
DARMLoadStoreOptimizer.cpp2384 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2735 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp136 const TargetRegisterClass *TRC) { in usesRegClass()
278 const TargetRegisterClass *TRC = in optimizeSDPattern() local
447 const TargetRegisterClass *TRC) { in createExtractSubreg()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyAsmPrinter.cpp61 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp494 const TargetRegisterClass *TRC = in EmitSubregNode() local
628 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp498 const TargetRegisterClass *TRC = in EmitSubregNode() local
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp499 const TargetRegisterClass *TRC = in EmitSubregNode() local
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp430 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
DRegAllocPBQP.cpp576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
/external/llvm-project/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
DRegAllocPBQP.cpp617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
DRegAllocPBQP.cpp604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp()
/external/llvm-project/llvm/lib/Target/X86/
DX86AvoidStoreForwardingBlocks.cpp564 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2531 const TargetRegisterClass *TRC; in Select() local
2566 const TargetRegisterClass *TRC; in Select() local
/external/llvm-project/clang/include/clang/AST/
DASTNodeTraverser.h404 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h1055 const TargetRegisterClass &TRC, in isOfRegClass()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h1095 const TargetRegisterClass &TRC, in isOfRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp776 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp()

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