1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 #include "AMDGPUAsmUtils.h" 9 #include "SIDefines.h" 10 11 namespace llvm { 12 namespace AMDGPU { 13 namespace SendMsg { 14 15 // This must be in sync with llvm::AMDGPU::SendMsg::Id enum members, see SIDefines.h. 16 const char* const IdSymbolic[] = { 17 nullptr, 18 "MSG_INTERRUPT", 19 "MSG_GS", 20 "MSG_GS_DONE", 21 nullptr, 22 nullptr, 23 nullptr, 24 nullptr, 25 nullptr, 26 "MSG_GS_ALLOC_REQ", 27 "MSG_GET_DOORBELL", 28 nullptr, 29 nullptr, 30 nullptr, 31 nullptr, 32 "MSG_SYSMSG" 33 }; 34 35 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h. 36 const char* const OpSysSymbolic[] = { 37 nullptr, 38 "SYSMSG_OP_ECC_ERR_INTERRUPT", 39 "SYSMSG_OP_REG_RD", 40 "SYSMSG_OP_HOST_TRAP_ACK", 41 "SYSMSG_OP_TTRACE_PC" 42 }; 43 44 const char* const OpGsSymbolic[] = { 45 "GS_OP_NOP", 46 "GS_OP_CUT", 47 "GS_OP_EMIT", 48 "GS_OP_EMIT_CUT" 49 }; 50 51 } // namespace SendMsg 52 53 namespace Hwreg { 54 55 // This must be in sync with llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_/LAST_, see SIDefines.h. 56 const char* const IdSymbolic[] = { 57 nullptr, 58 "HW_REG_MODE", 59 "HW_REG_STATUS", 60 "HW_REG_TRAPSTS", 61 "HW_REG_HW_ID", 62 "HW_REG_GPR_ALLOC", 63 "HW_REG_LDS_ALLOC", 64 "HW_REG_IB_STS", 65 nullptr, 66 nullptr, 67 nullptr, 68 nullptr, 69 nullptr, 70 nullptr, 71 nullptr, 72 "HW_REG_SH_MEM_BASES", 73 "HW_REG_TBA_LO", 74 "HW_REG_TBA_HI", 75 "HW_REG_TMA_LO", 76 "HW_REG_TMA_HI", 77 "HW_REG_FLAT_SCR_LO", 78 "HW_REG_FLAT_SCR_HI", 79 "HW_REG_XNACK_MASK", 80 nullptr, // HW_ID1, no predictable values 81 nullptr, // HW_ID2, no predictable values 82 "HW_REG_POPS_PACKER", 83 nullptr, 84 nullptr, 85 nullptr, 86 "HW_REG_SHADER_CYCLES" 87 }; 88 89 } // namespace Hwreg 90 91 namespace MTBUFFormat { 92 93 StringLiteral const DfmtSymbolic[] = { 94 "BUF_DATA_FORMAT_INVALID", 95 "BUF_DATA_FORMAT_8", 96 "BUF_DATA_FORMAT_16", 97 "BUF_DATA_FORMAT_8_8", 98 "BUF_DATA_FORMAT_32", 99 "BUF_DATA_FORMAT_16_16", 100 "BUF_DATA_FORMAT_10_11_11", 101 "BUF_DATA_FORMAT_11_11_10", 102 "BUF_DATA_FORMAT_10_10_10_2", 103 "BUF_DATA_FORMAT_2_10_10_10", 104 "BUF_DATA_FORMAT_8_8_8_8", 105 "BUF_DATA_FORMAT_32_32", 106 "BUF_DATA_FORMAT_16_16_16_16", 107 "BUF_DATA_FORMAT_32_32_32", 108 "BUF_DATA_FORMAT_32_32_32_32", 109 "BUF_DATA_FORMAT_RESERVED_15" 110 }; 111 112 StringLiteral const NfmtSymbolicGFX10[] = { 113 "BUF_NUM_FORMAT_UNORM", 114 "BUF_NUM_FORMAT_SNORM", 115 "BUF_NUM_FORMAT_USCALED", 116 "BUF_NUM_FORMAT_SSCALED", 117 "BUF_NUM_FORMAT_UINT", 118 "BUF_NUM_FORMAT_SINT", 119 "", 120 "BUF_NUM_FORMAT_FLOAT" 121 }; 122 123 StringLiteral const NfmtSymbolicSICI[] = { 124 "BUF_NUM_FORMAT_UNORM", 125 "BUF_NUM_FORMAT_SNORM", 126 "BUF_NUM_FORMAT_USCALED", 127 "BUF_NUM_FORMAT_SSCALED", 128 "BUF_NUM_FORMAT_UINT", 129 "BUF_NUM_FORMAT_SINT", 130 "BUF_NUM_FORMAT_SNORM_OGL", 131 "BUF_NUM_FORMAT_FLOAT" 132 }; 133 134 StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9 135 "BUF_NUM_FORMAT_UNORM", 136 "BUF_NUM_FORMAT_SNORM", 137 "BUF_NUM_FORMAT_USCALED", 138 "BUF_NUM_FORMAT_SSCALED", 139 "BUF_NUM_FORMAT_UINT", 140 "BUF_NUM_FORMAT_SINT", 141 "BUF_NUM_FORMAT_RESERVED_6", 142 "BUF_NUM_FORMAT_FLOAT" 143 }; 144 145 StringLiteral const UfmtSymbolic[] = { 146 "BUF_FMT_INVALID", 147 148 "BUF_FMT_8_UNORM", 149 "BUF_FMT_8_SNORM", 150 "BUF_FMT_8_USCALED", 151 "BUF_FMT_8_SSCALED", 152 "BUF_FMT_8_UINT", 153 "BUF_FMT_8_SINT", 154 155 "BUF_FMT_16_UNORM", 156 "BUF_FMT_16_SNORM", 157 "BUF_FMT_16_USCALED", 158 "BUF_FMT_16_SSCALED", 159 "BUF_FMT_16_UINT", 160 "BUF_FMT_16_SINT", 161 "BUF_FMT_16_FLOAT", 162 163 "BUF_FMT_8_8_UNORM", 164 "BUF_FMT_8_8_SNORM", 165 "BUF_FMT_8_8_USCALED", 166 "BUF_FMT_8_8_SSCALED", 167 "BUF_FMT_8_8_UINT", 168 "BUF_FMT_8_8_SINT", 169 170 "BUF_FMT_32_UINT", 171 "BUF_FMT_32_SINT", 172 "BUF_FMT_32_FLOAT", 173 174 "BUF_FMT_16_16_UNORM", 175 "BUF_FMT_16_16_SNORM", 176 "BUF_FMT_16_16_USCALED", 177 "BUF_FMT_16_16_SSCALED", 178 "BUF_FMT_16_16_UINT", 179 "BUF_FMT_16_16_SINT", 180 "BUF_FMT_16_16_FLOAT", 181 182 "BUF_FMT_10_11_11_UNORM", 183 "BUF_FMT_10_11_11_SNORM", 184 "BUF_FMT_10_11_11_USCALED", 185 "BUF_FMT_10_11_11_SSCALED", 186 "BUF_FMT_10_11_11_UINT", 187 "BUF_FMT_10_11_11_SINT", 188 "BUF_FMT_10_11_11_FLOAT", 189 190 "BUF_FMT_11_11_10_UNORM", 191 "BUF_FMT_11_11_10_SNORM", 192 "BUF_FMT_11_11_10_USCALED", 193 "BUF_FMT_11_11_10_SSCALED", 194 "BUF_FMT_11_11_10_UINT", 195 "BUF_FMT_11_11_10_SINT", 196 "BUF_FMT_11_11_10_FLOAT", 197 198 "BUF_FMT_10_10_10_2_UNORM", 199 "BUF_FMT_10_10_10_2_SNORM", 200 "BUF_FMT_10_10_10_2_USCALED", 201 "BUF_FMT_10_10_10_2_SSCALED", 202 "BUF_FMT_10_10_10_2_UINT", 203 "BUF_FMT_10_10_10_2_SINT", 204 205 "BUF_FMT_2_10_10_10_UNORM", 206 "BUF_FMT_2_10_10_10_SNORM", 207 "BUF_FMT_2_10_10_10_USCALED", 208 "BUF_FMT_2_10_10_10_SSCALED", 209 "BUF_FMT_2_10_10_10_UINT", 210 "BUF_FMT_2_10_10_10_SINT", 211 212 "BUF_FMT_8_8_8_8_UNORM", 213 "BUF_FMT_8_8_8_8_SNORM", 214 "BUF_FMT_8_8_8_8_USCALED", 215 "BUF_FMT_8_8_8_8_SSCALED", 216 "BUF_FMT_8_8_8_8_UINT", 217 "BUF_FMT_8_8_8_8_SINT", 218 219 "BUF_FMT_32_32_UINT", 220 "BUF_FMT_32_32_SINT", 221 "BUF_FMT_32_32_FLOAT", 222 223 "BUF_FMT_16_16_16_16_UNORM", 224 "BUF_FMT_16_16_16_16_SNORM", 225 "BUF_FMT_16_16_16_16_USCALED", 226 "BUF_FMT_16_16_16_16_SSCALED", 227 "BUF_FMT_16_16_16_16_UINT", 228 "BUF_FMT_16_16_16_16_SINT", 229 "BUF_FMT_16_16_16_16_FLOAT", 230 231 "BUF_FMT_32_32_32_UINT", 232 "BUF_FMT_32_32_32_SINT", 233 "BUF_FMT_32_32_32_FLOAT", 234 "BUF_FMT_32_32_32_32_UINT", 235 "BUF_FMT_32_32_32_32_SINT", 236 "BUF_FMT_32_32_32_32_FLOAT" 237 }; 238 239 unsigned const DfmtNfmt2UFmt[] = { 240 DFMT_INVALID | (NFMT_UNORM << NFMT_SHIFT), 241 242 DFMT_8 | (NFMT_UNORM << NFMT_SHIFT), 243 DFMT_8 | (NFMT_SNORM << NFMT_SHIFT), 244 DFMT_8 | (NFMT_USCALED << NFMT_SHIFT), 245 DFMT_8 | (NFMT_SSCALED << NFMT_SHIFT), 246 DFMT_8 | (NFMT_UINT << NFMT_SHIFT), 247 DFMT_8 | (NFMT_SINT << NFMT_SHIFT), 248 249 DFMT_16 | (NFMT_UNORM << NFMT_SHIFT), 250 DFMT_16 | (NFMT_SNORM << NFMT_SHIFT), 251 DFMT_16 | (NFMT_USCALED << NFMT_SHIFT), 252 DFMT_16 | (NFMT_SSCALED << NFMT_SHIFT), 253 DFMT_16 | (NFMT_UINT << NFMT_SHIFT), 254 DFMT_16 | (NFMT_SINT << NFMT_SHIFT), 255 DFMT_16 | (NFMT_FLOAT << NFMT_SHIFT), 256 257 DFMT_8_8 | (NFMT_UNORM << NFMT_SHIFT), 258 DFMT_8_8 | (NFMT_SNORM << NFMT_SHIFT), 259 DFMT_8_8 | (NFMT_USCALED << NFMT_SHIFT), 260 DFMT_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 261 DFMT_8_8 | (NFMT_UINT << NFMT_SHIFT), 262 DFMT_8_8 | (NFMT_SINT << NFMT_SHIFT), 263 264 DFMT_32 | (NFMT_UINT << NFMT_SHIFT), 265 DFMT_32 | (NFMT_SINT << NFMT_SHIFT), 266 DFMT_32 | (NFMT_FLOAT << NFMT_SHIFT), 267 268 DFMT_16_16 | (NFMT_UNORM << NFMT_SHIFT), 269 DFMT_16_16 | (NFMT_SNORM << NFMT_SHIFT), 270 DFMT_16_16 | (NFMT_USCALED << NFMT_SHIFT), 271 DFMT_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 272 DFMT_16_16 | (NFMT_UINT << NFMT_SHIFT), 273 DFMT_16_16 | (NFMT_SINT << NFMT_SHIFT), 274 DFMT_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 275 276 DFMT_10_11_11 | (NFMT_UNORM << NFMT_SHIFT), 277 DFMT_10_11_11 | (NFMT_SNORM << NFMT_SHIFT), 278 DFMT_10_11_11 | (NFMT_USCALED << NFMT_SHIFT), 279 DFMT_10_11_11 | (NFMT_SSCALED << NFMT_SHIFT), 280 DFMT_10_11_11 | (NFMT_UINT << NFMT_SHIFT), 281 DFMT_10_11_11 | (NFMT_SINT << NFMT_SHIFT), 282 DFMT_10_11_11 | (NFMT_FLOAT << NFMT_SHIFT), 283 284 DFMT_11_11_10 | (NFMT_UNORM << NFMT_SHIFT), 285 DFMT_11_11_10 | (NFMT_SNORM << NFMT_SHIFT), 286 DFMT_11_11_10 | (NFMT_USCALED << NFMT_SHIFT), 287 DFMT_11_11_10 | (NFMT_SSCALED << NFMT_SHIFT), 288 DFMT_11_11_10 | (NFMT_UINT << NFMT_SHIFT), 289 DFMT_11_11_10 | (NFMT_SINT << NFMT_SHIFT), 290 DFMT_11_11_10 | (NFMT_FLOAT << NFMT_SHIFT), 291 292 DFMT_10_10_10_2 | (NFMT_UNORM << NFMT_SHIFT), 293 DFMT_10_10_10_2 | (NFMT_SNORM << NFMT_SHIFT), 294 DFMT_10_10_10_2 | (NFMT_USCALED << NFMT_SHIFT), 295 DFMT_10_10_10_2 | (NFMT_SSCALED << NFMT_SHIFT), 296 DFMT_10_10_10_2 | (NFMT_UINT << NFMT_SHIFT), 297 DFMT_10_10_10_2 | (NFMT_SINT << NFMT_SHIFT), 298 299 DFMT_2_10_10_10 | (NFMT_UNORM << NFMT_SHIFT), 300 DFMT_2_10_10_10 | (NFMT_SNORM << NFMT_SHIFT), 301 DFMT_2_10_10_10 | (NFMT_USCALED << NFMT_SHIFT), 302 DFMT_2_10_10_10 | (NFMT_SSCALED << NFMT_SHIFT), 303 DFMT_2_10_10_10 | (NFMT_UINT << NFMT_SHIFT), 304 DFMT_2_10_10_10 | (NFMT_SINT << NFMT_SHIFT), 305 306 DFMT_8_8_8_8 | (NFMT_UNORM << NFMT_SHIFT), 307 DFMT_8_8_8_8 | (NFMT_SNORM << NFMT_SHIFT), 308 DFMT_8_8_8_8 | (NFMT_USCALED << NFMT_SHIFT), 309 DFMT_8_8_8_8 | (NFMT_SSCALED << NFMT_SHIFT), 310 DFMT_8_8_8_8 | (NFMT_UINT << NFMT_SHIFT), 311 DFMT_8_8_8_8 | (NFMT_SINT << NFMT_SHIFT), 312 313 DFMT_32_32 | (NFMT_UINT << NFMT_SHIFT), 314 DFMT_32_32 | (NFMT_SINT << NFMT_SHIFT), 315 DFMT_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 316 317 DFMT_16_16_16_16 | (NFMT_UNORM << NFMT_SHIFT), 318 DFMT_16_16_16_16 | (NFMT_SNORM << NFMT_SHIFT), 319 DFMT_16_16_16_16 | (NFMT_USCALED << NFMT_SHIFT), 320 DFMT_16_16_16_16 | (NFMT_SSCALED << NFMT_SHIFT), 321 DFMT_16_16_16_16 | (NFMT_UINT << NFMT_SHIFT), 322 DFMT_16_16_16_16 | (NFMT_SINT << NFMT_SHIFT), 323 DFMT_16_16_16_16 | (NFMT_FLOAT << NFMT_SHIFT), 324 325 DFMT_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 326 DFMT_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 327 DFMT_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT), 328 DFMT_32_32_32_32 | (NFMT_UINT << NFMT_SHIFT), 329 DFMT_32_32_32_32 | (NFMT_SINT << NFMT_SHIFT), 330 DFMT_32_32_32_32 | (NFMT_FLOAT << NFMT_SHIFT) 331 }; 332 333 } // namespace MTBUFFormat 334 335 namespace Swizzle { 336 337 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h. 338 const char* const IdSymbolic[] = { 339 "QUAD_PERM", 340 "BITMASK_PERM", 341 "SWAP", 342 "REVERSE", 343 "BROADCAST", 344 }; 345 346 } // namespace Swizzle 347 348 namespace VGPRIndexMode { 349 350 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h. 351 const char* const IdSymbolic[] = { 352 "SRC0", 353 "SRC1", 354 "SRC2", 355 "DST", 356 }; 357 358 } // namespace VGPRIndexMode 359 360 } // namespace AMDGPU 361 } // namespace llvm 362