1 // Copyright 2017 Google LLC 2 // Copyright 2020 Intel Corporation 3 // 4 // Licensed under the Apache License, Version 2.0 (the "License"); 5 // you may not use this file except in compliance with the License. 6 // You may obtain a copy of the License at 7 // 8 // http://www.apache.org/licenses/LICENSE-2.0 9 // 10 // Unless required by applicable law or agreed to in writing, software 11 // distributed under the License is distributed on an "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 // See the License for the specific language governing permissions and 14 // limitations under the License. 15 16 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 17 #define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 18 19 #include "cpu_features_cache_info.h" 20 #include "cpu_features_macros.h" 21 22 CPU_FEATURES_START_CPP_NAMESPACE 23 24 // See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features. 25 // The field names are based on the short name provided in the wikipedia tables. 26 typedef struct { 27 int fpu : 1; 28 int tsc : 1; 29 int cx8 : 1; 30 int clfsh : 1; 31 int mmx : 1; 32 int aes : 1; 33 int erms : 1; 34 int f16c : 1; 35 int fma4 : 1; 36 int fma3 : 1; 37 int vaes : 1; 38 int vpclmulqdq : 1; 39 int bmi1 : 1; 40 int hle : 1; 41 int bmi2 : 1; 42 int rtm : 1; 43 int rdseed : 1; 44 int clflushopt : 1; 45 int clwb : 1; 46 47 int sse : 1; 48 int sse2 : 1; 49 int sse3 : 1; 50 int ssse3 : 1; 51 int sse4_1 : 1; 52 int sse4_2 : 1; 53 int sse4a : 1; 54 55 int avx : 1; 56 int avx2 : 1; 57 58 int avx512f : 1; 59 int avx512cd : 1; 60 int avx512er : 1; 61 int avx512pf : 1; 62 int avx512bw : 1; 63 int avx512dq : 1; 64 int avx512vl : 1; 65 int avx512ifma : 1; 66 int avx512vbmi : 1; 67 int avx512vbmi2 : 1; 68 int avx512vnni : 1; 69 int avx512bitalg : 1; 70 int avx512vpopcntdq : 1; 71 int avx512_4vnniw : 1; 72 int avx512_4vbmi2 : 1; 73 int avx512_second_fma : 1; 74 int avx512_4fmaps : 1; 75 int avx512_bf16 : 1; 76 int avx512_vp2intersect : 1; 77 int amx_bf16 : 1; 78 int amx_tile : 1; 79 int amx_int8 : 1; 80 81 int pclmulqdq : 1; 82 int smx : 1; 83 int sgx : 1; 84 int cx16 : 1; // aka. CMPXCHG16B 85 int sha : 1; 86 int popcnt : 1; 87 int movbe : 1; 88 int rdrnd : 1; 89 90 int dca : 1; 91 int ss : 1; 92 // Make sure to update X86FeaturesEnum below if you add a field here. 93 } X86Features; 94 95 typedef struct { 96 X86Features features; 97 int family; 98 int model; 99 int stepping; 100 char vendor[13]; // 0 terminated string 101 } X86Info; 102 103 // Calls cpuid and returns an initialized X86info. 104 // This function is guaranteed to be malloc, memset and memcpy free. 105 X86Info GetX86Info(void); 106 107 // Returns cache hierarchy informations. 108 // Can call cpuid multiple times. 109 // Only works on Intel CPU at the moment. 110 // This function is guaranteed to be malloc, memset and memcpy free. 111 CacheInfo GetX86CacheInfo(void); 112 113 typedef enum { 114 X86_UNKNOWN, 115 INTEL_CORE, // CORE 116 INTEL_PNR, // PENRYN 117 INTEL_NHM, // NEHALEM 118 INTEL_ATOM_BNL, // BONNELL 119 INTEL_WSM, // WESTMERE 120 INTEL_SNB, // SANDYBRIDGE 121 INTEL_IVB, // IVYBRIDGE 122 INTEL_ATOM_SMT, // SILVERMONT 123 INTEL_HSW, // HASWELL 124 INTEL_BDW, // BROADWELL 125 INTEL_SKL, // SKYLAKE 126 INTEL_ATOM_GMT, // GOLDMONT 127 INTEL_KBL, // KABY LAKE 128 INTEL_CFL, // COFFEE LAKE 129 INTEL_WHL, // WHISKEY LAKE 130 INTEL_CNL, // CANNON LAKE 131 INTEL_ICL, // ICE LAKE 132 INTEL_TGL, // TIGER LAKE 133 INTEL_SPR, // SAPPHIRE RAPIDS 134 AMD_HAMMER, // K8 135 AMD_K10, // K10 136 AMD_BOBCAT, // K14 137 AMD_BULLDOZER, // K15 138 AMD_JAGUAR, // K16 139 AMD_ZEN, // K17 140 } X86Microarchitecture; 141 142 // Returns the underlying microarchitecture by looking at X86Info's vendor, 143 // family and model. 144 X86Microarchitecture GetX86Microarchitecture(const X86Info* info); 145 146 // Calls cpuid and fills the brand_string. 147 // - brand_string *must* be of size 49 (beware of array decaying). 148 // - brand_string will be zero terminated. 149 // - This function calls memcpy. 150 void FillX86BrandString(char brand_string[49]); 151 152 //////////////////////////////////////////////////////////////////////////////// 153 // Introspection functions 154 155 typedef enum { 156 X86_FPU, 157 X86_TSC, 158 X86_CX8, 159 X86_CLFSH, 160 X86_MMX, 161 X86_AES, 162 X86_ERMS, 163 X86_F16C, 164 X86_FMA4, 165 X86_FMA3, 166 X86_VAES, 167 X86_VPCLMULQDQ, 168 X86_BMI1, 169 X86_HLE, 170 X86_BMI2, 171 X86_RTM, 172 X86_RDSEED, 173 X86_CLFLUSHOPT, 174 X86_CLWB, 175 X86_SSE, 176 X86_SSE2, 177 X86_SSE3, 178 X86_SSSE3, 179 X86_SSE4_1, 180 X86_SSE4_2, 181 X86_SSE4A, 182 X86_AVX, 183 X86_AVX2, 184 X86_AVX512F, 185 X86_AVX512CD, 186 X86_AVX512ER, 187 X86_AVX512PF, 188 X86_AVX512BW, 189 X86_AVX512DQ, 190 X86_AVX512VL, 191 X86_AVX512IFMA, 192 X86_AVX512VBMI, 193 X86_AVX512VBMI2, 194 X86_AVX512VNNI, 195 X86_AVX512BITALG, 196 X86_AVX512VPOPCNTDQ, 197 X86_AVX512_4VNNIW, 198 X86_AVX512_4VBMI2, 199 X86_AVX512_SECOND_FMA, 200 X86_AVX512_4FMAPS, 201 X86_AVX512_BF16, 202 X86_AVX512_VP2INTERSECT, 203 X86_AMX_BF16, 204 X86_AMX_TILE, 205 X86_AMX_INT8, 206 X86_PCLMULQDQ, 207 X86_SMX, 208 X86_SGX, 209 X86_CX16, 210 X86_SHA, 211 X86_POPCNT, 212 X86_MOVBE, 213 X86_RDRND, 214 X86_DCA, 215 X86_SS, 216 X86_LAST_, 217 } X86FeaturesEnum; 218 219 int GetX86FeaturesEnumValue(const X86Features* features, X86FeaturesEnum value); 220 221 const char* GetX86FeaturesEnumName(X86FeaturesEnum); 222 223 const char* GetX86MicroarchitectureName(X86Microarchitecture); 224 225 CPU_FEATURES_END_CPP_NAMESPACE 226 227 #if !defined(CPU_FEATURES_ARCH_X86) 228 #error "Including cpuinfo_x86.h from a non-x86 target." 229 #endif 230 231 #endif // CPU_FEATURES_INCLUDE_CPUINFO_X86_H_ 232