1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25
26 #include "dev/gen_device_info.h"
27 #include "common/gen_sample_positions.h"
28 #include "genxml/gen_macros.h"
29 #include "common/gen_guardband.h"
30
31 #include "main/bufferobj.h"
32 #include "main/context.h"
33 #include "main/enums.h"
34 #include "main/macros.h"
35 #include "main/state.h"
36
37 #include "genX_boilerplate.h"
38
39 #include "brw_context.h"
40 #include "brw_cs.h"
41 #include "brw_draw.h"
42 #include "brw_multisample_state.h"
43 #include "brw_state.h"
44 #include "brw_wm.h"
45 #include "brw_util.h"
46
47 #include "intel_batchbuffer.h"
48 #include "intel_buffer_objects.h"
49 #include "intel_fbo.h"
50
51 #include "main/enums.h"
52 #include "main/fbobject.h"
53 #include "main/framebuffer.h"
54 #include "main/glformats.h"
55 #include "main/samplerobj.h"
56 #include "main/shaderapi.h"
57 #include "main/stencil.h"
58 #include "main/transformfeedback.h"
59 #include "main/varray.h"
60 #include "main/viewport.h"
61 #include "util/half_float.h"
62
63 #if GEN_GEN == 4
64 static struct brw_address
KSP(struct brw_context * brw,uint32_t offset)65 KSP(struct brw_context *brw, uint32_t offset)
66 {
67 return ro_bo(brw->cache.bo, offset);
68 }
69 #else
70 static uint32_t
KSP(UNUSED struct brw_context * brw,uint32_t offset)71 KSP(UNUSED struct brw_context *brw, uint32_t offset)
72 {
73 return offset;
74 }
75 #endif
76
77 #if GEN_GEN >= 7
78 static void
emit_lrm(struct brw_context * brw,uint32_t reg,struct brw_address addr)79 emit_lrm(struct brw_context *brw, uint32_t reg, struct brw_address addr)
80 {
81 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_MEM), lrm) {
82 lrm.RegisterAddress = reg;
83 lrm.MemoryAddress = addr;
84 }
85 }
86 #endif
87
88 #if GEN_GEN == 7
89 static void
emit_lri(struct brw_context * brw,uint32_t reg,uint32_t imm)90 emit_lri(struct brw_context *brw, uint32_t reg, uint32_t imm)
91 {
92 brw_batch_emit(brw, GENX(MI_LOAD_REGISTER_IMM), lri) {
93 lri.RegisterOffset = reg;
94 lri.DataDWord = imm;
95 }
96 }
97 #endif
98
99 /**
100 * Polygon stipple packet
101 */
102 static void
genX(upload_polygon_stipple)103 genX(upload_polygon_stipple)(struct brw_context *brw)
104 {
105 struct gl_context *ctx = &brw->ctx;
106
107 /* _NEW_POLYGON */
108 if (!ctx->Polygon.StippleFlag)
109 return;
110
111 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
112 /* Polygon stipple is provided in OpenGL order, i.e. bottom
113 * row first. If we're rendering to a window (i.e. the
114 * default frame buffer object, 0), then we need to invert
115 * it to match our pixel layout. But if we're rendering
116 * to a FBO (i.e. any named frame buffer object), we *don't*
117 * need to invert - we already match the layout.
118 */
119 if (ctx->DrawBuffer->FlipY) {
120 for (unsigned i = 0; i < 32; i++)
121 poly.PatternRow[i] = ctx->PolygonStipple[31 - i]; /* invert */
122 } else {
123 for (unsigned i = 0; i < 32; i++)
124 poly.PatternRow[i] = ctx->PolygonStipple[i];
125 }
126 }
127 }
128
129 static const struct brw_tracked_state genX(polygon_stipple) = {
130 .dirty = {
131 .mesa = _NEW_POLYGON |
132 _NEW_POLYGONSTIPPLE,
133 .brw = BRW_NEW_CONTEXT,
134 },
135 .emit = genX(upload_polygon_stipple),
136 };
137
138 /**
139 * Polygon stipple offset packet
140 */
141 static void
genX(upload_polygon_stipple_offset)142 genX(upload_polygon_stipple_offset)(struct brw_context *brw)
143 {
144 struct gl_context *ctx = &brw->ctx;
145
146 /* _NEW_POLYGON */
147 if (!ctx->Polygon.StippleFlag)
148 return;
149
150 brw_batch_emit(brw, GENX(3DSTATE_POLY_STIPPLE_OFFSET), poly) {
151 /* _NEW_BUFFERS
152 *
153 * If we're drawing to a system window we have to invert the Y axis
154 * in order to match the OpenGL pixel coordinate system, and our
155 * offset must be matched to the window position. If we're drawing
156 * to a user-created FBO then our native pixel coordinate system
157 * works just fine, and there's no window system to worry about.
158 */
159 if (ctx->DrawBuffer->FlipY) {
160 poly.PolygonStippleYOffset =
161 (32 - (_mesa_geometric_height(ctx->DrawBuffer) & 31)) & 31;
162 }
163 }
164 }
165
166 static const struct brw_tracked_state genX(polygon_stipple_offset) = {
167 .dirty = {
168 .mesa = _NEW_BUFFERS |
169 _NEW_POLYGON,
170 .brw = BRW_NEW_CONTEXT,
171 },
172 .emit = genX(upload_polygon_stipple_offset),
173 };
174
175 /**
176 * Line stipple packet
177 */
178 static void
genX(upload_line_stipple)179 genX(upload_line_stipple)(struct brw_context *brw)
180 {
181 struct gl_context *ctx = &brw->ctx;
182
183 if (!ctx->Line.StippleFlag)
184 return;
185
186 brw_batch_emit(brw, GENX(3DSTATE_LINE_STIPPLE), line) {
187 line.LineStipplePattern = ctx->Line.StipplePattern;
188
189 line.LineStippleInverseRepeatCount = 1.0f / ctx->Line.StippleFactor;
190 line.LineStippleRepeatCount = ctx->Line.StippleFactor;
191 }
192 }
193
194 static const struct brw_tracked_state genX(line_stipple) = {
195 .dirty = {
196 .mesa = _NEW_LINE,
197 .brw = BRW_NEW_CONTEXT,
198 },
199 .emit = genX(upload_line_stipple),
200 };
201
202 /* Constant single cliprect for framebuffer object or DRI2 drawing */
203 static void
genX(upload_drawing_rect)204 genX(upload_drawing_rect)(struct brw_context *brw)
205 {
206 struct gl_context *ctx = &brw->ctx;
207 const struct gl_framebuffer *fb = ctx->DrawBuffer;
208 const unsigned int fb_width = _mesa_geometric_width(fb);
209 const unsigned int fb_height = _mesa_geometric_height(fb);
210
211 brw_batch_emit(brw, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
212 rect.ClippedDrawingRectangleXMax = fb_width - 1;
213 rect.ClippedDrawingRectangleYMax = fb_height - 1;
214 }
215 }
216
217 static const struct brw_tracked_state genX(drawing_rect) = {
218 .dirty = {
219 .mesa = _NEW_BUFFERS,
220 .brw = BRW_NEW_BLORP |
221 BRW_NEW_CONTEXT,
222 },
223 .emit = genX(upload_drawing_rect),
224 };
225
226 static uint32_t *
genX(emit_vertex_buffer_state)227 genX(emit_vertex_buffer_state)(struct brw_context *brw,
228 uint32_t *dw,
229 unsigned buffer_nr,
230 struct brw_bo *bo,
231 unsigned start_offset,
232 UNUSED unsigned end_offset,
233 unsigned stride,
234 UNUSED unsigned step_rate)
235 {
236 struct GENX(VERTEX_BUFFER_STATE) buf_state = {
237 .VertexBufferIndex = buffer_nr,
238 .BufferPitch = stride,
239
240 /* The VF cache designers apparently cut corners, and made the cache
241 * only consider the bottom 32 bits of memory addresses. If you happen
242 * to have two vertex buffers which get placed exactly 4 GiB apart and
243 * use them in back-to-back draw calls, you can get collisions. To work
244 * around this problem, we restrict vertex buffers to the low 32 bits of
245 * the address space.
246 */
247 .BufferStartingAddress = ro_32_bo(bo, start_offset),
248 #if GEN_GEN >= 8
249 .BufferSize = end_offset - start_offset,
250 #endif
251
252 #if GEN_GEN >= 7
253 .AddressModifyEnable = true,
254 #endif
255
256 #if GEN_GEN < 8
257 .BufferAccessType = step_rate ? INSTANCEDATA : VERTEXDATA,
258 .InstanceDataStepRate = step_rate,
259 #if GEN_GEN >= 5
260 .EndAddress = ro_bo(bo, end_offset - 1),
261 #endif
262 #endif
263
264 #if GEN_GEN == 11
265 .MOCS = ICL_MOCS_WB,
266 #elif GEN_GEN == 10
267 .MOCS = CNL_MOCS_WB,
268 #elif GEN_GEN == 9
269 .MOCS = SKL_MOCS_WB,
270 #elif GEN_GEN == 8
271 .MOCS = BDW_MOCS_WB,
272 #elif GEN_GEN == 7
273 .MOCS = GEN7_MOCS_L3,
274 #endif
275 };
276
277 GENX(VERTEX_BUFFER_STATE_pack)(brw, dw, &buf_state);
278 return dw + GENX(VERTEX_BUFFER_STATE_length);
279 }
280
281 UNUSED static bool
is_passthru_format(uint32_t format)282 is_passthru_format(uint32_t format)
283 {
284 switch (format) {
285 case ISL_FORMAT_R64_PASSTHRU:
286 case ISL_FORMAT_R64G64_PASSTHRU:
287 case ISL_FORMAT_R64G64B64_PASSTHRU:
288 case ISL_FORMAT_R64G64B64A64_PASSTHRU:
289 return true;
290 default:
291 return false;
292 }
293 }
294
295 UNUSED static int
uploads_needed(uint32_t format,bool is_dual_slot)296 uploads_needed(uint32_t format,
297 bool is_dual_slot)
298 {
299 if (!is_passthru_format(format))
300 return 1;
301
302 if (is_dual_slot)
303 return 2;
304
305 switch (format) {
306 case ISL_FORMAT_R64_PASSTHRU:
307 case ISL_FORMAT_R64G64_PASSTHRU:
308 return 1;
309 case ISL_FORMAT_R64G64B64_PASSTHRU:
310 case ISL_FORMAT_R64G64B64A64_PASSTHRU:
311 return 2;
312 default:
313 unreachable("not reached");
314 }
315 }
316
317 /*
318 * Returns the format that we are finally going to use when upload a vertex
319 * element. It will only change if we are using *64*PASSTHRU formats, as for
320 * gen < 8 they need to be splitted on two *32*FLOAT formats.
321 *
322 * @upload points in which upload we are. Valid values are [0,1]
323 */
324 static uint32_t
downsize_format_if_needed(uint32_t format,int upload)325 downsize_format_if_needed(uint32_t format,
326 int upload)
327 {
328 assert(upload == 0 || upload == 1);
329
330 if (!is_passthru_format(format))
331 return format;
332
333 /* ISL_FORMAT_R64_PASSTHRU and ISL_FORMAT_R64G64_PASSTHRU with an upload ==
334 * 1 means that we have been forced to do 2 uploads for a size <= 2. This
335 * happens with gen < 8 and dvec3 or dvec4 vertex shader input
336 * variables. In those cases, we return ISL_FORMAT_R32_FLOAT as a way of
337 * flagging that we want to fill with zeroes this second forced upload.
338 */
339 switch (format) {
340 case ISL_FORMAT_R64_PASSTHRU:
341 return upload == 0 ? ISL_FORMAT_R32G32_FLOAT
342 : ISL_FORMAT_R32_FLOAT;
343 case ISL_FORMAT_R64G64_PASSTHRU:
344 return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
345 : ISL_FORMAT_R32_FLOAT;
346 case ISL_FORMAT_R64G64B64_PASSTHRU:
347 return upload == 0 ? ISL_FORMAT_R32G32B32A32_FLOAT
348 : ISL_FORMAT_R32G32_FLOAT;
349 case ISL_FORMAT_R64G64B64A64_PASSTHRU:
350 return ISL_FORMAT_R32G32B32A32_FLOAT;
351 default:
352 unreachable("not reached");
353 }
354 }
355
356 /*
357 * Returns the number of componentes associated with a format that is used on
358 * a 64 to 32 format split. See downsize_format()
359 */
360 static int
upload_format_size(uint32_t upload_format)361 upload_format_size(uint32_t upload_format)
362 {
363 switch (upload_format) {
364 case ISL_FORMAT_R32_FLOAT:
365
366 /* downsized_format has returned this one in order to flag that we are
367 * performing a second upload which we want to have filled with
368 * zeroes. This happens with gen < 8, a size <= 2, and dvec3 or dvec4
369 * vertex shader input variables.
370 */
371
372 return 0;
373 case ISL_FORMAT_R32G32_FLOAT:
374 return 2;
375 case ISL_FORMAT_R32G32B32A32_FLOAT:
376 return 4;
377 default:
378 unreachable("not reached");
379 }
380 }
381
382 static UNUSED uint16_t
pinned_bo_high_bits(struct brw_bo * bo)383 pinned_bo_high_bits(struct brw_bo *bo)
384 {
385 return (bo->kflags & EXEC_OBJECT_PINNED) ? bo->gtt_offset >> 32ull : 0;
386 }
387
388 /* The VF cache designers apparently cut corners, and made the cache key's
389 * <VertexBufferIndex, Memory Address> tuple only consider the bottom 32 bits
390 * of the address. If you happen to have two vertex buffers which get placed
391 * exactly 4 GiB apart and use them in back-to-back draw calls, you can get
392 * collisions. (These collisions can happen within a single batch.)
393 *
394 * In the soft-pin world, we'd like to assign addresses up front, and never
395 * move buffers. So, we need to do a VF cache invalidate if the buffer for
396 * a particular VB slot has different [48:32] address bits than the last one.
397 *
398 * In the relocation world, we have no idea what the addresses will be, so
399 * we can't apply this workaround. Instead, we tell the kernel to move it
400 * to the low 4GB regardless.
401 *
402 * This HW issue is gone on Gen11+.
403 */
404 static void
vf_invalidate_for_vb_48bit_transitions(UNUSED struct brw_context * brw)405 vf_invalidate_for_vb_48bit_transitions(UNUSED struct brw_context *brw)
406 {
407 #if GEN_GEN >= 8 && GEN_GEN < 11
408 bool need_invalidate = false;
409
410 for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
411 uint16_t high_bits = pinned_bo_high_bits(brw->vb.buffers[i].bo);
412
413 if (high_bits != brw->vb.last_bo_high_bits[i]) {
414 need_invalidate = true;
415 brw->vb.last_bo_high_bits[i] = high_bits;
416 }
417 }
418
419 if (brw->draw.draw_params_bo) {
420 uint16_t high_bits = pinned_bo_high_bits(brw->draw.draw_params_bo);
421
422 if (brw->vb.last_bo_high_bits[brw->vb.nr_buffers] != high_bits) {
423 need_invalidate = true;
424 brw->vb.last_bo_high_bits[brw->vb.nr_buffers] = high_bits;
425 }
426 }
427
428 if (brw->draw.derived_draw_params_bo) {
429 uint16_t high_bits = pinned_bo_high_bits(brw->draw.derived_draw_params_bo);
430
431 if (brw->vb.last_bo_high_bits[brw->vb.nr_buffers + 1] != high_bits) {
432 need_invalidate = true;
433 brw->vb.last_bo_high_bits[brw->vb.nr_buffers + 1] = high_bits;
434 }
435 }
436
437 if (need_invalidate) {
438 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL);
439 }
440 #endif
441 }
442
443 static void
vf_invalidate_for_ib_48bit_transition(UNUSED struct brw_context * brw)444 vf_invalidate_for_ib_48bit_transition(UNUSED struct brw_context *brw)
445 {
446 #if GEN_GEN >= 8
447 uint16_t high_bits = pinned_bo_high_bits(brw->ib.bo);
448
449 if (high_bits != brw->ib.last_bo_high_bits) {
450 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE);
451 brw->ib.last_bo_high_bits = high_bits;
452 }
453 #endif
454 }
455
456 static void
genX(emit_vertices)457 genX(emit_vertices)(struct brw_context *brw)
458 {
459 const struct gen_device_info *devinfo = &brw->screen->devinfo;
460 uint32_t *dw;
461
462 brw_prepare_vertices(brw);
463 brw_prepare_shader_draw_parameters(brw);
464
465 #if GEN_GEN < 6
466 brw_emit_query_begin(brw);
467 #endif
468
469 const struct brw_vs_prog_data *vs_prog_data =
470 brw_vs_prog_data(brw->vs.base.prog_data);
471
472 #if GEN_GEN >= 8
473 struct gl_context *ctx = &brw->ctx;
474 const bool uses_edge_flag = (ctx->Polygon.FrontMode != GL_FILL ||
475 ctx->Polygon.BackMode != GL_FILL);
476
477 if (vs_prog_data->uses_vertexid || vs_prog_data->uses_instanceid) {
478 unsigned vue = brw->vb.nr_enabled;
479
480 /* The element for the edge flags must always be last, so we have to
481 * insert the SGVS before it in that case.
482 */
483 if (uses_edge_flag) {
484 assert(vue > 0);
485 vue--;
486 }
487
488 WARN_ONCE(vue >= 33,
489 "Trying to insert VID/IID past 33rd vertex element, "
490 "need to reorder the vertex attrbutes.");
491
492 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs) {
493 if (vs_prog_data->uses_vertexid) {
494 vfs.VertexIDEnable = true;
495 vfs.VertexIDComponentNumber = 2;
496 vfs.VertexIDElementOffset = vue;
497 }
498
499 if (vs_prog_data->uses_instanceid) {
500 vfs.InstanceIDEnable = true;
501 vfs.InstanceIDComponentNumber = 3;
502 vfs.InstanceIDElementOffset = vue;
503 }
504 }
505
506 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) {
507 vfi.InstancingEnable = true;
508 vfi.VertexElementIndex = vue;
509 }
510 } else {
511 brw_batch_emit(brw, GENX(3DSTATE_VF_SGVS), vfs);
512 }
513 #endif
514
515 const bool uses_draw_params =
516 vs_prog_data->uses_firstvertex ||
517 vs_prog_data->uses_baseinstance;
518
519 const bool uses_derived_draw_params =
520 vs_prog_data->uses_drawid ||
521 vs_prog_data->uses_is_indexed_draw;
522
523 const bool needs_sgvs_element = (uses_draw_params ||
524 vs_prog_data->uses_instanceid ||
525 vs_prog_data->uses_vertexid);
526
527 unsigned nr_elements =
528 brw->vb.nr_enabled + needs_sgvs_element + uses_derived_draw_params;
529
530 #if GEN_GEN < 8
531 /* If any of the formats of vb.enabled needs more that one upload, we need
532 * to add it to nr_elements
533 */
534 for (unsigned i = 0; i < brw->vb.nr_enabled; i++) {
535 struct brw_vertex_element *input = brw->vb.enabled[i];
536 uint32_t format = brw_get_vertex_surface_type(brw, input->glformat);
537
538 if (uploads_needed(format, input->is_dual_slot) > 1)
539 nr_elements++;
540 }
541 #endif
542
543 /* If the VS doesn't read any inputs (calculating vertex position from
544 * a state variable for some reason, for example), emit a single pad
545 * VERTEX_ELEMENT struct and bail.
546 *
547 * The stale VB state stays in place, but they don't do anything unless
548 * a VE loads from them.
549 */
550 if (nr_elements == 0) {
551 dw = brw_batch_emitn(brw, GENX(3DSTATE_VERTEX_ELEMENTS),
552 1 + GENX(VERTEX_ELEMENT_STATE_length));
553 struct GENX(VERTEX_ELEMENT_STATE) elem = {
554 .Valid = true,
555 .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
556 .Component0Control = VFCOMP_STORE_0,
557 .Component1Control = VFCOMP_STORE_0,
558 .Component2Control = VFCOMP_STORE_0,
559 .Component3Control = VFCOMP_STORE_1_FP,
560 };
561 GENX(VERTEX_ELEMENT_STATE_pack)(brw, dw, &elem);
562 return;
563 }
564
565 /* Now emit 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS packets. */
566 const unsigned nr_buffers = brw->vb.nr_buffers +
567 uses_draw_params + uses_derived_draw_params;
568
569 vf_invalidate_for_vb_48bit_transitions(brw);
570
571 if (nr_buffers) {
572 assert(nr_buffers <= (GEN_GEN >= 6 ? 33 : 17));
573
574 dw = brw_batch_emitn(brw, GENX(3DSTATE_VERTEX_BUFFERS),
575 1 + GENX(VERTEX_BUFFER_STATE_length) * nr_buffers);
576
577 for (unsigned i = 0; i < brw->vb.nr_buffers; i++) {
578 const struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
579 /* Prior to Haswell and Bay Trail we have to use 4-component formats
580 * to fake 3-component ones. In particular, we do this for
581 * half-float and 8 and 16-bit integer formats. This means that the
582 * vertex element may poke over the end of the buffer by 2 bytes.
583 */
584 const unsigned padding =
585 (GEN_GEN <= 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail) * 2;
586 const unsigned end = buffer->offset + buffer->size + padding;
587 dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo,
588 buffer->offset,
589 end,
590 buffer->stride,
591 buffer->step_rate);
592 }
593
594 if (uses_draw_params) {
595 dw = genX(emit_vertex_buffer_state)(brw, dw, brw->vb.nr_buffers,
596 brw->draw.draw_params_bo,
597 brw->draw.draw_params_offset,
598 brw->draw.draw_params_bo->size,
599 0 /* stride */,
600 0 /* step rate */);
601 }
602
603 if (uses_derived_draw_params) {
604 dw = genX(emit_vertex_buffer_state)(brw, dw, brw->vb.nr_buffers + 1,
605 brw->draw.derived_draw_params_bo,
606 brw->draw.derived_draw_params_offset,
607 brw->draw.derived_draw_params_bo->size,
608 0 /* stride */,
609 0 /* step rate */);
610 }
611 }
612
613 /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS,
614 * presumably for VertexID/InstanceID.
615 */
616 #if GEN_GEN >= 6
617 assert(nr_elements <= 34);
618 const struct brw_vertex_element *gen6_edgeflag_input = NULL;
619 #else
620 assert(nr_elements <= 18);
621 #endif
622
623 dw = brw_batch_emitn(brw, GENX(3DSTATE_VERTEX_ELEMENTS),
624 1 + GENX(VERTEX_ELEMENT_STATE_length) * nr_elements);
625 unsigned i;
626 for (i = 0; i < brw->vb.nr_enabled; i++) {
627 const struct brw_vertex_element *input = brw->vb.enabled[i];
628 const struct gl_vertex_format *glformat = input->glformat;
629 uint32_t format = brw_get_vertex_surface_type(brw, glformat);
630 uint32_t comp0 = VFCOMP_STORE_SRC;
631 uint32_t comp1 = VFCOMP_STORE_SRC;
632 uint32_t comp2 = VFCOMP_STORE_SRC;
633 uint32_t comp3 = VFCOMP_STORE_SRC;
634 const unsigned num_uploads = GEN_GEN < 8 ?
635 uploads_needed(format, input->is_dual_slot) : 1;
636
637 #if GEN_GEN >= 8
638 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE):
639 * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an
640 * element which has edge flag enabled."
641 */
642 assert(!(is_passthru_format(format) && uses_edge_flag));
643 #endif
644
645 /* The gen4 driver expects edgeflag to come in as a float, and passes
646 * that float on to the tests in the clipper. Mesa's current vertex
647 * attribute value for EdgeFlag is stored as a float, which works out.
648 * glEdgeFlagPointer, on the other hand, gives us an unnormalized
649 * integer ubyte. Just rewrite that to convert to a float.
650 *
651 * Gen6+ passes edgeflag as sideband along with the vertex, instead
652 * of in the VUE. We have to upload it sideband as the last vertex
653 * element according to the B-Spec.
654 */
655 #if GEN_GEN >= 6
656 if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) {
657 gen6_edgeflag_input = input;
658 continue;
659 }
660 #endif
661
662 for (unsigned c = 0; c < num_uploads; c++) {
663 const uint32_t upload_format = GEN_GEN >= 8 ? format :
664 downsize_format_if_needed(format, c);
665 /* If we need more that one upload, the offset stride would be 128
666 * bits (16 bytes), as for previous uploads we are using the full
667 * entry. */
668 const unsigned offset = input->offset + c * 16;
669
670 const int size = (GEN_GEN < 8 && is_passthru_format(format)) ?
671 upload_format_size(upload_format) : glformat->Size;
672
673 switch (size) {
674 case 0: comp0 = VFCOMP_STORE_0; /* fallthrough */
675 case 1: comp1 = VFCOMP_STORE_0; /* fallthrough */
676 case 2: comp2 = VFCOMP_STORE_0; /* fallthrough */
677 case 3:
678 if (GEN_GEN >= 8 && glformat->Doubles) {
679 comp3 = VFCOMP_STORE_0;
680 } else if (glformat->Integer) {
681 comp3 = VFCOMP_STORE_1_INT;
682 } else {
683 comp3 = VFCOMP_STORE_1_FP;
684 }
685
686 break;
687 }
688
689 #if GEN_GEN >= 8
690 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE):
691 *
692 * "When SourceElementFormat is set to one of the *64*_PASSTHRU
693 * formats, 64-bit components are stored in the URB without any
694 * conversion. In this case, vertex elements must be written as 128
695 * or 256 bits, with VFCOMP_STORE_0 being used to pad the output as
696 * required. E.g., if R64_PASSTHRU is used to copy a 64-bit Red
697 * component into the URB, Component 1 must be specified as
698 * VFCOMP_STORE_0 (with Components 2,3 set to VFCOMP_NOSTORE) in
699 * order to output a 128-bit vertex element, or Components 1-3 must
700 * be specified as VFCOMP_STORE_0 in order to output a 256-bit vertex
701 * element. Likewise, use of R64G64B64_PASSTHRU requires Component 3
702 * to be specified as VFCOMP_STORE_0 in order to output a 256-bit
703 * vertex element."
704 */
705 if (glformat->Doubles && !input->is_dual_slot) {
706 /* Store vertex elements which correspond to double and dvec2 vertex
707 * shader inputs as 128-bit vertex elements, instead of 256-bits.
708 */
709 comp2 = VFCOMP_NOSTORE;
710 comp3 = VFCOMP_NOSTORE;
711 }
712 #endif
713
714 struct GENX(VERTEX_ELEMENT_STATE) elem_state = {
715 .VertexBufferIndex = input->buffer,
716 .Valid = true,
717 .SourceElementFormat = upload_format,
718 .SourceElementOffset = offset,
719 .Component0Control = comp0,
720 .Component1Control = comp1,
721 .Component2Control = comp2,
722 .Component3Control = comp3,
723 #if GEN_GEN < 5
724 .DestinationElementOffset = i * 4,
725 #endif
726 };
727
728 GENX(VERTEX_ELEMENT_STATE_pack)(brw, dw, &elem_state);
729 dw += GENX(VERTEX_ELEMENT_STATE_length);
730 }
731 }
732
733 if (needs_sgvs_element) {
734 struct GENX(VERTEX_ELEMENT_STATE) elem_state = {
735 .Valid = true,
736 .Component0Control = VFCOMP_STORE_0,
737 .Component1Control = VFCOMP_STORE_0,
738 .Component2Control = VFCOMP_STORE_0,
739 .Component3Control = VFCOMP_STORE_0,
740 #if GEN_GEN < 5
741 .DestinationElementOffset = i * 4,
742 #endif
743 };
744
745 #if GEN_GEN >= 8
746 if (uses_draw_params) {
747 elem_state.VertexBufferIndex = brw->vb.nr_buffers;
748 elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT;
749 elem_state.Component0Control = VFCOMP_STORE_SRC;
750 elem_state.Component1Control = VFCOMP_STORE_SRC;
751 }
752 #else
753 elem_state.VertexBufferIndex = brw->vb.nr_buffers;
754 elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT;
755 if (uses_draw_params) {
756 elem_state.Component0Control = VFCOMP_STORE_SRC;
757 elem_state.Component1Control = VFCOMP_STORE_SRC;
758 }
759
760 if (vs_prog_data->uses_vertexid)
761 elem_state.Component2Control = VFCOMP_STORE_VID;
762
763 if (vs_prog_data->uses_instanceid)
764 elem_state.Component3Control = VFCOMP_STORE_IID;
765 #endif
766
767 GENX(VERTEX_ELEMENT_STATE_pack)(brw, dw, &elem_state);
768 dw += GENX(VERTEX_ELEMENT_STATE_length);
769 }
770
771 if (uses_derived_draw_params) {
772 struct GENX(VERTEX_ELEMENT_STATE) elem_state = {
773 .Valid = true,
774 .VertexBufferIndex = brw->vb.nr_buffers + 1,
775 .SourceElementFormat = ISL_FORMAT_R32G32_UINT,
776 .Component0Control = VFCOMP_STORE_SRC,
777 .Component1Control = VFCOMP_STORE_SRC,
778 .Component2Control = VFCOMP_STORE_0,
779 .Component3Control = VFCOMP_STORE_0,
780 #if GEN_GEN < 5
781 .DestinationElementOffset = i * 4,
782 #endif
783 };
784
785 GENX(VERTEX_ELEMENT_STATE_pack)(brw, dw, &elem_state);
786 dw += GENX(VERTEX_ELEMENT_STATE_length);
787 }
788
789 #if GEN_GEN >= 6
790 if (gen6_edgeflag_input) {
791 const struct gl_vertex_format *glformat = gen6_edgeflag_input->glformat;
792 const uint32_t format = brw_get_vertex_surface_type(brw, glformat);
793
794 struct GENX(VERTEX_ELEMENT_STATE) elem_state = {
795 .Valid = true,
796 .VertexBufferIndex = gen6_edgeflag_input->buffer,
797 .EdgeFlagEnable = true,
798 .SourceElementFormat = format,
799 .SourceElementOffset = gen6_edgeflag_input->offset,
800 .Component0Control = VFCOMP_STORE_SRC,
801 .Component1Control = VFCOMP_STORE_0,
802 .Component2Control = VFCOMP_STORE_0,
803 .Component3Control = VFCOMP_STORE_0,
804 };
805
806 GENX(VERTEX_ELEMENT_STATE_pack)(brw, dw, &elem_state);
807 dw += GENX(VERTEX_ELEMENT_STATE_length);
808 }
809 #endif
810
811 #if GEN_GEN >= 8
812 for (unsigned i = 0, j = 0; i < brw->vb.nr_enabled; i++) {
813 const struct brw_vertex_element *input = brw->vb.enabled[i];
814 const struct brw_vertex_buffer *buffer = &brw->vb.buffers[input->buffer];
815 unsigned element_index;
816
817 /* The edge flag element is reordered to be the last one in the code
818 * above so we need to compensate for that in the element indices used
819 * below.
820 */
821 if (input == gen6_edgeflag_input)
822 element_index = nr_elements - 1;
823 else
824 element_index = j++;
825
826 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) {
827 vfi.VertexElementIndex = element_index;
828 vfi.InstancingEnable = buffer->step_rate != 0;
829 vfi.InstanceDataStepRate = buffer->step_rate;
830 }
831 }
832
833 if (vs_prog_data->uses_drawid) {
834 const unsigned element = brw->vb.nr_enabled + needs_sgvs_element;
835
836 brw_batch_emit(brw, GENX(3DSTATE_VF_INSTANCING), vfi) {
837 vfi.VertexElementIndex = element;
838 }
839 }
840 #endif
841 }
842
843 static const struct brw_tracked_state genX(vertices) = {
844 .dirty = {
845 .mesa = _NEW_POLYGON,
846 .brw = BRW_NEW_BATCH |
847 BRW_NEW_BLORP |
848 BRW_NEW_VERTEX_PROGRAM |
849 BRW_NEW_VERTICES |
850 BRW_NEW_VS_PROG_DATA,
851 },
852 .emit = genX(emit_vertices),
853 };
854
855 static void
genX(emit_index_buffer)856 genX(emit_index_buffer)(struct brw_context *brw)
857 {
858 const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
859
860 if (index_buffer == NULL)
861 return;
862
863 vf_invalidate_for_ib_48bit_transition(brw);
864
865 brw_batch_emit(brw, GENX(3DSTATE_INDEX_BUFFER), ib) {
866 #if GEN_GEN < 8 && !GEN_IS_HASWELL
867 assert(brw->ib.enable_cut_index == brw->prim_restart.enable_cut_index);
868 ib.CutIndexEnable = brw->ib.enable_cut_index;
869 #endif
870 ib.IndexFormat = brw_get_index_type(1 << index_buffer->index_size_shift);
871
872 /* The VF cache designers apparently cut corners, and made the cache
873 * only consider the bottom 32 bits of memory addresses. If you happen
874 * to have two index buffers which get placed exactly 4 GiB apart and
875 * use them in back-to-back draw calls, you can get collisions. To work
876 * around this problem, we restrict index buffers to the low 32 bits of
877 * the address space.
878 */
879 ib.BufferStartingAddress = ro_32_bo(brw->ib.bo, 0);
880 #if GEN_GEN >= 8
881 ib.MOCS = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
882 ib.BufferSize = brw->ib.size;
883 #else
884 ib.BufferEndingAddress = ro_bo(brw->ib.bo, brw->ib.size - 1);
885 #endif
886 }
887 }
888
889 static const struct brw_tracked_state genX(index_buffer) = {
890 .dirty = {
891 .mesa = 0,
892 .brw = BRW_NEW_BATCH |
893 BRW_NEW_BLORP |
894 BRW_NEW_INDEX_BUFFER,
895 },
896 .emit = genX(emit_index_buffer),
897 };
898
899 #if GEN_IS_HASWELL || GEN_GEN >= 8
900 static void
genX(upload_cut_index)901 genX(upload_cut_index)(struct brw_context *brw)
902 {
903 const struct gl_context *ctx = &brw->ctx;
904
905 brw_batch_emit(brw, GENX(3DSTATE_VF), vf) {
906 if (ctx->Array._PrimitiveRestart && brw->ib.ib) {
907 vf.IndexedDrawCutIndexEnable = true;
908 vf.CutIndex = ctx->Array._RestartIndex[brw->ib.index_size - 1];
909 }
910 }
911 }
912
913 const struct brw_tracked_state genX(cut_index) = {
914 .dirty = {
915 .mesa = _NEW_TRANSFORM,
916 .brw = BRW_NEW_INDEX_BUFFER,
917 },
918 .emit = genX(upload_cut_index),
919 };
920 #endif
921
922 static void
genX(upload_vf_statistics)923 genX(upload_vf_statistics)(struct brw_context *brw)
924 {
925 brw_batch_emit(brw, GENX(3DSTATE_VF_STATISTICS), vf) {
926 vf.StatisticsEnable = true;
927 }
928 }
929
930 const struct brw_tracked_state genX(vf_statistics) = {
931 .dirty = {
932 .mesa = 0,
933 .brw = BRW_NEW_BLORP | BRW_NEW_CONTEXT,
934 },
935 .emit = genX(upload_vf_statistics),
936 };
937
938 #if GEN_GEN >= 6
939 /**
940 * Determine the appropriate attribute override value to store into the
941 * 3DSTATE_SF structure for a given fragment shader attribute. The attribute
942 * override value contains two pieces of information: the location of the
943 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
944 * flag indicating whether to "swizzle" the attribute based on the direction
945 * the triangle is facing.
946 *
947 * If an attribute is "swizzled", then the given VUE location is used for
948 * front-facing triangles, and the VUE location that immediately follows is
949 * used for back-facing triangles. We use this to implement the mapping from
950 * gl_FrontColor/gl_BackColor to gl_Color.
951 *
952 * urb_entry_read_offset is the offset into the VUE at which the SF unit is
953 * being instructed to begin reading attribute data. It can be set to a
954 * nonzero value to prevent the SF unit from wasting time reading elements of
955 * the VUE that are not needed by the fragment shader. It is measured in
956 * 256-bit increments.
957 */
958 static void
genX(get_attr_override)959 genX(get_attr_override)(struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) *attr,
960 const struct brw_vue_map *vue_map,
961 int urb_entry_read_offset, int fs_attr,
962 bool two_side_color, uint32_t *max_source_attr)
963 {
964 /* Find the VUE slot for this attribute. */
965 int slot = vue_map->varying_to_slot[fs_attr];
966
967 /* Viewport and Layer are stored in the VUE header. We need to override
968 * them to zero if earlier stages didn't write them, as GL requires that
969 * they read back as zero when not explicitly set.
970 */
971 if (fs_attr == VARYING_SLOT_VIEWPORT || fs_attr == VARYING_SLOT_LAYER) {
972 attr->ComponentOverrideX = true;
973 attr->ComponentOverrideW = true;
974 attr->ConstantSource = CONST_0000;
975
976 if (!(vue_map->slots_valid & VARYING_BIT_LAYER))
977 attr->ComponentOverrideY = true;
978 if (!(vue_map->slots_valid & VARYING_BIT_VIEWPORT))
979 attr->ComponentOverrideZ = true;
980
981 return;
982 }
983
984 /* If there was only a back color written but not front, use back
985 * as the color instead of undefined
986 */
987 if (slot == -1 && fs_attr == VARYING_SLOT_COL0)
988 slot = vue_map->varying_to_slot[VARYING_SLOT_BFC0];
989 if (slot == -1 && fs_attr == VARYING_SLOT_COL1)
990 slot = vue_map->varying_to_slot[VARYING_SLOT_BFC1];
991
992 if (slot == -1) {
993 /* This attribute does not exist in the VUE--that means that the vertex
994 * shader did not write to it. This means that either:
995 *
996 * (a) This attribute is a texture coordinate, and it is going to be
997 * replaced with point coordinates (as a consequence of a call to
998 * glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)), so the
999 * hardware will ignore whatever attribute override we supply.
1000 *
1001 * (b) This attribute is read by the fragment shader but not written by
1002 * the vertex shader, so its value is undefined. Therefore the
1003 * attribute override we supply doesn't matter.
1004 *
1005 * (c) This attribute is gl_PrimitiveID, and it wasn't written by the
1006 * previous shader stage.
1007 *
1008 * Note that we don't have to worry about the cases where the attribute
1009 * is gl_PointCoord or is undergoing point sprite coordinate
1010 * replacement, because in those cases, this function isn't called.
1011 *
1012 * In case (c), we need to program the attribute overrides so that the
1013 * primitive ID will be stored in this slot. In every other case, the
1014 * attribute override we supply doesn't matter. So just go ahead and
1015 * program primitive ID in every case.
1016 */
1017 attr->ComponentOverrideW = true;
1018 attr->ComponentOverrideX = true;
1019 attr->ComponentOverrideY = true;
1020 attr->ComponentOverrideZ = true;
1021 attr->ConstantSource = PRIM_ID;
1022 return;
1023 }
1024
1025 /* Compute the location of the attribute relative to urb_entry_read_offset.
1026 * Each increment of urb_entry_read_offset represents a 256-bit value, so
1027 * it counts for two 128-bit VUE slots.
1028 */
1029 int source_attr = slot - 2 * urb_entry_read_offset;
1030 assert(source_attr >= 0 && source_attr < 32);
1031
1032 /* If we are doing two-sided color, and the VUE slot following this one
1033 * represents a back-facing color, then we need to instruct the SF unit to
1034 * do back-facing swizzling.
1035 */
1036 bool swizzling = two_side_color &&
1037 ((vue_map->slot_to_varying[slot] == VARYING_SLOT_COL0 &&
1038 vue_map->slot_to_varying[slot+1] == VARYING_SLOT_BFC0) ||
1039 (vue_map->slot_to_varying[slot] == VARYING_SLOT_COL1 &&
1040 vue_map->slot_to_varying[slot+1] == VARYING_SLOT_BFC1));
1041
1042 /* Update max_source_attr. If swizzling, the SF will read this slot + 1. */
1043 if (*max_source_attr < source_attr + swizzling)
1044 *max_source_attr = source_attr + swizzling;
1045
1046 attr->SourceAttribute = source_attr;
1047 if (swizzling)
1048 attr->SwizzleSelect = INPUTATTR_FACING;
1049 }
1050
1051
1052 static void
genX(calculate_attr_overrides)1053 genX(calculate_attr_overrides)(const struct brw_context *brw,
1054 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) *attr_overrides,
1055 uint32_t *point_sprite_enables,
1056 uint32_t *urb_entry_read_length,
1057 uint32_t *urb_entry_read_offset)
1058 {
1059 const struct gl_context *ctx = &brw->ctx;
1060
1061 /* _NEW_POINT */
1062 const struct gl_point_attrib *point = &ctx->Point;
1063
1064 /* BRW_NEW_FRAGMENT_PROGRAM */
1065 const struct gl_program *fp = brw->programs[MESA_SHADER_FRAGMENT];
1066
1067 /* BRW_NEW_FS_PROG_DATA */
1068 const struct brw_wm_prog_data *wm_prog_data =
1069 brw_wm_prog_data(brw->wm.base.prog_data);
1070 uint32_t max_source_attr = 0;
1071
1072 *point_sprite_enables = 0;
1073
1074 int first_slot =
1075 brw_compute_first_urb_slot_required(fp->info.inputs_read,
1076 &brw->vue_map_geom_out);
1077
1078 /* Each URB offset packs two varying slots */
1079 assert(first_slot % 2 == 0);
1080 *urb_entry_read_offset = first_slot / 2;
1081
1082 /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
1083 * description of dw10 Point Sprite Texture Coordinate Enable:
1084 *
1085 * "This field must be programmed to zero when non-point primitives
1086 * are rendered."
1087 *
1088 * The SandyBridge PRM doesn't explicitly say that point sprite enables
1089 * must be programmed to zero when rendering non-point primitives, but
1090 * the IvyBridge PRM does, and if we don't, we get garbage.
1091 *
1092 * This is not required on Haswell, as the hardware ignores this state
1093 * when drawing non-points -- although we do still need to be careful to
1094 * correctly set the attr overrides.
1095 *
1096 * _NEW_POLYGON
1097 * BRW_NEW_PRIMITIVE | BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA
1098 */
1099 bool drawing_points = brw_is_drawing_points(brw);
1100
1101 for (uint8_t idx = 0; idx < wm_prog_data->urb_setup_attribs_count; idx++) {
1102 uint8_t attr = wm_prog_data->urb_setup_attribs[idx];
1103 int input_index = wm_prog_data->urb_setup[attr];
1104
1105 assert(0 <= input_index);
1106
1107 /* _NEW_POINT */
1108 bool point_sprite = false;
1109 if (drawing_points) {
1110 if (point->PointSprite &&
1111 (attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7) &&
1112 (point->CoordReplace & (1u << (attr - VARYING_SLOT_TEX0)))) {
1113 point_sprite = true;
1114 }
1115
1116 if (attr == VARYING_SLOT_PNTC)
1117 point_sprite = true;
1118
1119 if (point_sprite)
1120 *point_sprite_enables |= (1 << input_index);
1121 }
1122
1123 /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
1124 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) attribute = { 0 };
1125
1126 if (!point_sprite) {
1127 genX(get_attr_override)(&attribute,
1128 &brw->vue_map_geom_out,
1129 *urb_entry_read_offset, attr,
1130 _mesa_vertex_program_two_side_enabled(ctx),
1131 &max_source_attr);
1132 }
1133
1134 /* The hardware can only do the overrides on 16 overrides at a
1135 * time, and the other up to 16 have to be lined up so that the
1136 * input index = the output index. We'll need to do some
1137 * tweaking to make sure that's the case.
1138 */
1139 if (input_index < 16)
1140 attr_overrides[input_index] = attribute;
1141 else
1142 assert(attribute.SourceAttribute == input_index);
1143 }
1144
1145 /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
1146 * 3DSTATE_SF DWord 1 bits 15:11, "Vertex URB Entry Read Length":
1147 *
1148 * "This field should be set to the minimum length required to read the
1149 * maximum source attribute. The maximum source attribute is indicated
1150 * by the maximum value of the enabled Attribute # Source Attribute if
1151 * Attribute Swizzle Enable is set, Number of Output Attributes-1 if
1152 * enable is not set.
1153 * read_length = ceiling((max_source_attr + 1) / 2)
1154 *
1155 * [errata] Corruption/Hang possible if length programmed larger than
1156 * recommended"
1157 *
1158 * Similar text exists for Ivy Bridge.
1159 */
1160 *urb_entry_read_length = DIV_ROUND_UP(max_source_attr + 1, 2);
1161 }
1162 #endif
1163
1164 /* ---------------------------------------------------------------------- */
1165
1166 #if GEN_GEN >= 8
1167 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL) DEPTH_STENCIL_GENXML;
1168 #elif GEN_GEN >= 6
1169 typedef struct GENX(DEPTH_STENCIL_STATE) DEPTH_STENCIL_GENXML;
1170 #else
1171 typedef struct GENX(COLOR_CALC_STATE) DEPTH_STENCIL_GENXML;
1172 #endif
1173
1174 static inline void
set_depth_stencil_bits(struct brw_context * brw,DEPTH_STENCIL_GENXML * ds)1175 set_depth_stencil_bits(struct brw_context *brw, DEPTH_STENCIL_GENXML *ds)
1176 {
1177 struct gl_context *ctx = &brw->ctx;
1178
1179 /* _NEW_BUFFERS */
1180 struct intel_renderbuffer *depth_irb =
1181 intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
1182
1183 /* _NEW_DEPTH */
1184 struct gl_depthbuffer_attrib *depth = &ctx->Depth;
1185
1186 /* _NEW_STENCIL */
1187 struct gl_stencil_attrib *stencil = &ctx->Stencil;
1188 const int b = stencil->_BackFace;
1189
1190 if (depth->Test && depth_irb) {
1191 ds->DepthTestEnable = true;
1192 ds->DepthBufferWriteEnable = brw_depth_writes_enabled(brw);
1193 ds->DepthTestFunction = intel_translate_compare_func(depth->Func);
1194 }
1195
1196 if (brw->stencil_enabled) {
1197 ds->StencilTestEnable = true;
1198 ds->StencilWriteMask = stencil->WriteMask[0] & 0xff;
1199 ds->StencilTestMask = stencil->ValueMask[0] & 0xff;
1200
1201 ds->StencilTestFunction =
1202 intel_translate_compare_func(stencil->Function[0]);
1203 ds->StencilFailOp =
1204 intel_translate_stencil_op(stencil->FailFunc[0]);
1205 ds->StencilPassDepthPassOp =
1206 intel_translate_stencil_op(stencil->ZPassFunc[0]);
1207 ds->StencilPassDepthFailOp =
1208 intel_translate_stencil_op(stencil->ZFailFunc[0]);
1209
1210 ds->StencilBufferWriteEnable = brw->stencil_write_enabled;
1211
1212 if (brw->stencil_two_sided) {
1213 ds->DoubleSidedStencilEnable = true;
1214 ds->BackfaceStencilWriteMask = stencil->WriteMask[b] & 0xff;
1215 ds->BackfaceStencilTestMask = stencil->ValueMask[b] & 0xff;
1216
1217 ds->BackfaceStencilTestFunction =
1218 intel_translate_compare_func(stencil->Function[b]);
1219 ds->BackfaceStencilFailOp =
1220 intel_translate_stencil_op(stencil->FailFunc[b]);
1221 ds->BackfaceStencilPassDepthPassOp =
1222 intel_translate_stencil_op(stencil->ZPassFunc[b]);
1223 ds->BackfaceStencilPassDepthFailOp =
1224 intel_translate_stencil_op(stencil->ZFailFunc[b]);
1225 }
1226
1227 #if GEN_GEN <= 5 || GEN_GEN >= 9
1228 ds->StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0);
1229 ds->BackfaceStencilReferenceValue = _mesa_get_stencil_ref(ctx, b);
1230 #endif
1231 }
1232 }
1233
1234 #if GEN_GEN >= 6
1235 static void
genX(upload_depth_stencil_state)1236 genX(upload_depth_stencil_state)(struct brw_context *brw)
1237 {
1238 #if GEN_GEN >= 8
1239 brw_batch_emit(brw, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) {
1240 set_depth_stencil_bits(brw, &wmds);
1241 }
1242 #else
1243 uint32_t ds_offset;
1244 brw_state_emit(brw, GENX(DEPTH_STENCIL_STATE), 64, &ds_offset, ds) {
1245 set_depth_stencil_bits(brw, &ds);
1246 }
1247
1248 /* Now upload a pointer to the indirect state */
1249 #if GEN_GEN == 6
1250 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
1251 ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
1252 ptr.DEPTH_STENCIL_STATEChange = true;
1253 }
1254 #else
1255 brw_batch_emit(brw, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), ptr) {
1256 ptr.PointertoDEPTH_STENCIL_STATE = ds_offset;
1257 }
1258 #endif
1259 #endif
1260 }
1261
1262 static const struct brw_tracked_state genX(depth_stencil_state) = {
1263 .dirty = {
1264 .mesa = _NEW_BUFFERS |
1265 _NEW_DEPTH |
1266 _NEW_STENCIL,
1267 .brw = BRW_NEW_BLORP |
1268 (GEN_GEN >= 8 ? BRW_NEW_CONTEXT
1269 : BRW_NEW_BATCH |
1270 BRW_NEW_STATE_BASE_ADDRESS),
1271 },
1272 .emit = genX(upload_depth_stencil_state),
1273 };
1274 #endif
1275
1276 /* ---------------------------------------------------------------------- */
1277
1278 #if GEN_GEN <= 5
1279
1280 static void
genX(upload_clip_state)1281 genX(upload_clip_state)(struct brw_context *brw)
1282 {
1283 struct gl_context *ctx = &brw->ctx;
1284
1285 ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
1286 brw_state_emit(brw, GENX(CLIP_STATE), 32, &brw->clip.state_offset, clip) {
1287 clip.KernelStartPointer = KSP(brw, brw->clip.prog_offset);
1288 clip.GRFRegisterCount =
1289 DIV_ROUND_UP(brw->clip.prog_data->total_grf, 16) - 1;
1290 clip.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
1291 clip.SingleProgramFlow = true;
1292 clip.VertexURBEntryReadLength = brw->clip.prog_data->urb_read_length;
1293 clip.ConstantURBEntryReadLength = brw->clip.prog_data->curb_read_length;
1294
1295 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1296 clip.ConstantURBEntryReadOffset = brw->curbe.clip_start * 2;
1297 clip.DispatchGRFStartRegisterForURBData = 1;
1298 clip.VertexURBEntryReadOffset = 0;
1299
1300 /* BRW_NEW_URB_FENCE */
1301 clip.NumberofURBEntries = brw->urb.nr_clip_entries;
1302 clip.URBEntryAllocationSize = brw->urb.vsize - 1;
1303
1304 if (brw->urb.nr_clip_entries >= 10) {
1305 /* Half of the URB entries go to each thread, and it has to be an
1306 * even number.
1307 */
1308 assert(brw->urb.nr_clip_entries % 2 == 0);
1309
1310 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
1311 * only 2 threads can output VUEs at a time.
1312 */
1313 clip.MaximumNumberofThreads = (GEN_GEN == 5 ? 16 : 2) - 1;
1314 } else {
1315 assert(brw->urb.nr_clip_entries >= 5);
1316 clip.MaximumNumberofThreads = 1 - 1;
1317 }
1318
1319 clip.VertexPositionSpace = VPOS_NDCSPACE;
1320 clip.UserClipFlagsMustClipEnable = true;
1321 clip.GuardbandClipTestEnable = true;
1322
1323 clip.ClipperViewportStatePointer =
1324 ro_bo(brw->batch.state.bo, brw->clip.vp_offset);
1325
1326 clip.ScreenSpaceViewportXMin = -1;
1327 clip.ScreenSpaceViewportXMax = 1;
1328 clip.ScreenSpaceViewportYMin = -1;
1329 clip.ScreenSpaceViewportYMax = 1;
1330
1331 clip.ViewportXYClipTestEnable = true;
1332 clip.ViewportZClipTestEnable = !(ctx->Transform.DepthClampNear &&
1333 ctx->Transform.DepthClampFar);
1334
1335 /* _NEW_TRANSFORM */
1336 if (GEN_GEN == 5 || GEN_IS_G4X) {
1337 clip.UserClipDistanceClipTestEnableBitmask =
1338 ctx->Transform.ClipPlanesEnabled;
1339 } else {
1340 /* Up to 6 actual clip flags, plus the 7th for the negative RHW
1341 * workaround.
1342 */
1343 clip.UserClipDistanceClipTestEnableBitmask =
1344 (ctx->Transform.ClipPlanesEnabled & 0x3f) | 0x40;
1345 }
1346
1347 if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
1348 clip.APIMode = APIMODE_D3D;
1349 else
1350 clip.APIMode = APIMODE_OGL;
1351
1352 clip.GuardbandClipTestEnable = true;
1353
1354 clip.ClipMode = brw->clip.prog_data->clip_mode;
1355
1356 #if GEN_IS_G4X
1357 clip.NegativeWClipTestEnable = true;
1358 #endif
1359 }
1360 }
1361
1362 const struct brw_tracked_state genX(clip_state) = {
1363 .dirty = {
1364 .mesa = _NEW_TRANSFORM |
1365 _NEW_VIEWPORT,
1366 .brw = BRW_NEW_BATCH |
1367 BRW_NEW_BLORP |
1368 BRW_NEW_CLIP_PROG_DATA |
1369 BRW_NEW_PUSH_CONSTANT_ALLOCATION |
1370 BRW_NEW_PROGRAM_CACHE |
1371 BRW_NEW_URB_FENCE,
1372 },
1373 .emit = genX(upload_clip_state),
1374 };
1375
1376 #else
1377
1378 static void
genX(upload_clip_state)1379 genX(upload_clip_state)(struct brw_context *brw)
1380 {
1381 struct gl_context *ctx = &brw->ctx;
1382
1383 /* _NEW_BUFFERS */
1384 struct gl_framebuffer *fb = ctx->DrawBuffer;
1385
1386 /* BRW_NEW_FS_PROG_DATA */
1387 struct brw_wm_prog_data *wm_prog_data =
1388 brw_wm_prog_data(brw->wm.base.prog_data);
1389
1390 brw_batch_emit(brw, GENX(3DSTATE_CLIP), clip) {
1391 clip.StatisticsEnable = !brw->meta_in_progress;
1392
1393 if (wm_prog_data->barycentric_interp_modes &
1394 BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
1395 clip.NonPerspectiveBarycentricEnable = true;
1396
1397 #if GEN_GEN >= 7
1398 clip.EarlyCullEnable = true;
1399 #endif
1400
1401 #if GEN_GEN == 7
1402 clip.FrontWinding = brw->polygon_front_bit != fb->FlipY;
1403
1404 if (ctx->Polygon.CullFlag) {
1405 switch (ctx->Polygon.CullFaceMode) {
1406 case GL_FRONT:
1407 clip.CullMode = CULLMODE_FRONT;
1408 break;
1409 case GL_BACK:
1410 clip.CullMode = CULLMODE_BACK;
1411 break;
1412 case GL_FRONT_AND_BACK:
1413 clip.CullMode = CULLMODE_BOTH;
1414 break;
1415 default:
1416 unreachable("Should not get here: invalid CullFlag");
1417 }
1418 } else {
1419 clip.CullMode = CULLMODE_NONE;
1420 }
1421 #endif
1422
1423 #if GEN_GEN < 8
1424 clip.UserClipDistanceCullTestEnableBitmask =
1425 brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask;
1426
1427 clip.ViewportZClipTestEnable = !(ctx->Transform.DepthClampNear &&
1428 ctx->Transform.DepthClampFar);
1429 #endif
1430
1431 /* _NEW_LIGHT */
1432 if (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
1433 clip.TriangleStripListProvokingVertexSelect = 0;
1434 clip.TriangleFanProvokingVertexSelect = 1;
1435 clip.LineStripListProvokingVertexSelect = 0;
1436 } else {
1437 clip.TriangleStripListProvokingVertexSelect = 2;
1438 clip.TriangleFanProvokingVertexSelect = 2;
1439 clip.LineStripListProvokingVertexSelect = 1;
1440 }
1441
1442 /* _NEW_TRANSFORM */
1443 clip.UserClipDistanceClipTestEnableBitmask =
1444 ctx->Transform.ClipPlanesEnabled;
1445
1446 #if GEN_GEN >= 8
1447 clip.ForceUserClipDistanceClipTestEnableBitmask = true;
1448 #endif
1449
1450 if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
1451 clip.APIMode = APIMODE_D3D;
1452 else
1453 clip.APIMode = APIMODE_OGL;
1454
1455 clip.GuardbandClipTestEnable = true;
1456
1457 /* BRW_NEW_VIEWPORT_COUNT */
1458 const unsigned viewport_count = brw->clip.viewport_count;
1459
1460 if (ctx->RasterDiscard) {
1461 clip.ClipMode = CLIPMODE_REJECT_ALL;
1462 #if GEN_GEN == 6
1463 perf_debug("Rasterizer discard is currently implemented via the "
1464 "clipper; having the GS not write primitives would "
1465 "likely be faster.\n");
1466 #endif
1467 } else {
1468 clip.ClipMode = CLIPMODE_NORMAL;
1469 }
1470
1471 clip.ClipEnable = true;
1472
1473 /* _NEW_POLYGON,
1474 * BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_TES_PROG_DATA | BRW_NEW_PRIMITIVE
1475 */
1476 if (!brw_is_drawing_points(brw) && !brw_is_drawing_lines(brw))
1477 clip.ViewportXYClipTestEnable = true;
1478
1479 clip.MinimumPointWidth = 0.125;
1480 clip.MaximumPointWidth = 255.875;
1481 clip.MaximumVPIndex = viewport_count - 1;
1482 if (_mesa_geometric_layers(fb) == 0)
1483 clip.ForceZeroRTAIndexEnable = true;
1484 }
1485 }
1486
1487 static const struct brw_tracked_state genX(clip_state) = {
1488 .dirty = {
1489 .mesa = _NEW_BUFFERS |
1490 _NEW_LIGHT |
1491 _NEW_POLYGON |
1492 _NEW_TRANSFORM,
1493 .brw = BRW_NEW_BLORP |
1494 BRW_NEW_CONTEXT |
1495 BRW_NEW_FS_PROG_DATA |
1496 BRW_NEW_GS_PROG_DATA |
1497 BRW_NEW_VS_PROG_DATA |
1498 BRW_NEW_META_IN_PROGRESS |
1499 BRW_NEW_PRIMITIVE |
1500 BRW_NEW_RASTERIZER_DISCARD |
1501 BRW_NEW_TES_PROG_DATA |
1502 BRW_NEW_VIEWPORT_COUNT,
1503 },
1504 .emit = genX(upload_clip_state),
1505 };
1506 #endif
1507
1508 /* ---------------------------------------------------------------------- */
1509
1510 static void
genX(upload_sf)1511 genX(upload_sf)(struct brw_context *brw)
1512 {
1513 struct gl_context *ctx = &brw->ctx;
1514 float point_size;
1515
1516 #if GEN_GEN <= 7
1517 /* _NEW_BUFFERS */
1518 bool flip_y = ctx->DrawBuffer->FlipY;
1519 UNUSED const bool multisampled_fbo =
1520 _mesa_geometric_samples(ctx->DrawBuffer) > 1;
1521 #endif
1522
1523 #if GEN_GEN < 6
1524 const struct brw_sf_prog_data *sf_prog_data = brw->sf.prog_data;
1525
1526 ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
1527
1528 brw_state_emit(brw, GENX(SF_STATE), 64, &brw->sf.state_offset, sf) {
1529 sf.KernelStartPointer = KSP(brw, brw->sf.prog_offset);
1530 sf.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
1531 sf.GRFRegisterCount = DIV_ROUND_UP(sf_prog_data->total_grf, 16) - 1;
1532 sf.DispatchGRFStartRegisterForURBData = 3;
1533 sf.VertexURBEntryReadOffset = BRW_SF_URB_ENTRY_READ_OFFSET;
1534 sf.VertexURBEntryReadLength = sf_prog_data->urb_read_length;
1535 sf.NumberofURBEntries = brw->urb.nr_sf_entries;
1536 sf.URBEntryAllocationSize = brw->urb.sfsize - 1;
1537
1538 /* STATE_PREFETCH command description describes this state as being
1539 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION
1540 * domain.
1541 */
1542 sf.SetupViewportStateOffset =
1543 ro_bo(brw->batch.state.bo, brw->sf.vp_offset);
1544
1545 sf.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
1546
1547 /* sf.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; */
1548 /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */
1549
1550 sf.MaximumNumberofThreads =
1551 MIN2(GEN_GEN == 5 ? 48 : 24, brw->urb.nr_sf_entries) - 1;
1552
1553 sf.SpritePointEnable = ctx->Point.PointSprite;
1554
1555 sf.DestinationOriginHorizontalBias = 0.5;
1556 sf.DestinationOriginVerticalBias = 0.5;
1557 #else
1558 brw_batch_emit(brw, GENX(3DSTATE_SF), sf) {
1559 sf.StatisticsEnable = true;
1560 #endif
1561 sf.ViewportTransformEnable = true;
1562
1563 #if GEN_GEN == 7
1564 /* _NEW_BUFFERS */
1565 sf.DepthBufferSurfaceFormat = brw_depthbuffer_format(brw);
1566 #endif
1567
1568 #if GEN_GEN <= 7
1569 /* _NEW_POLYGON */
1570 sf.FrontWinding = brw->polygon_front_bit != flip_y;
1571 #if GEN_GEN >= 6
1572 sf.GlobalDepthOffsetEnableSolid = ctx->Polygon.OffsetFill;
1573 sf.GlobalDepthOffsetEnableWireframe = ctx->Polygon.OffsetLine;
1574 sf.GlobalDepthOffsetEnablePoint = ctx->Polygon.OffsetPoint;
1575
1576 switch (ctx->Polygon.FrontMode) {
1577 case GL_FILL:
1578 sf.FrontFaceFillMode = FILL_MODE_SOLID;
1579 break;
1580 case GL_LINE:
1581 sf.FrontFaceFillMode = FILL_MODE_WIREFRAME;
1582 break;
1583 case GL_POINT:
1584 sf.FrontFaceFillMode = FILL_MODE_POINT;
1585 break;
1586 default:
1587 unreachable("not reached");
1588 }
1589
1590 switch (ctx->Polygon.BackMode) {
1591 case GL_FILL:
1592 sf.BackFaceFillMode = FILL_MODE_SOLID;
1593 break;
1594 case GL_LINE:
1595 sf.BackFaceFillMode = FILL_MODE_WIREFRAME;
1596 break;
1597 case GL_POINT:
1598 sf.BackFaceFillMode = FILL_MODE_POINT;
1599 break;
1600 default:
1601 unreachable("not reached");
1602 }
1603
1604 if (multisampled_fbo && ctx->Multisample.Enabled)
1605 sf.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
1606
1607 sf.GlobalDepthOffsetConstant = ctx->Polygon.OffsetUnits * 2;
1608 sf.GlobalDepthOffsetScale = ctx->Polygon.OffsetFactor;
1609 sf.GlobalDepthOffsetClamp = ctx->Polygon.OffsetClamp;
1610 #endif
1611
1612 sf.ScissorRectangleEnable = true;
1613
1614 if (ctx->Polygon.CullFlag) {
1615 switch (ctx->Polygon.CullFaceMode) {
1616 case GL_FRONT:
1617 sf.CullMode = CULLMODE_FRONT;
1618 break;
1619 case GL_BACK:
1620 sf.CullMode = CULLMODE_BACK;
1621 break;
1622 case GL_FRONT_AND_BACK:
1623 sf.CullMode = CULLMODE_BOTH;
1624 break;
1625 default:
1626 unreachable("not reached");
1627 }
1628 } else {
1629 sf.CullMode = CULLMODE_NONE;
1630 }
1631
1632 #if GEN_IS_HASWELL
1633 sf.LineStippleEnable = ctx->Line.StippleFlag;
1634 #endif
1635
1636 #endif
1637
1638 /* _NEW_LINE */
1639 #if GEN_GEN == 8
1640 const struct gen_device_info *devinfo = &brw->screen->devinfo;
1641
1642 if (devinfo->is_cherryview)
1643 sf.CHVLineWidth = brw_get_line_width(brw);
1644 else
1645 sf.LineWidth = brw_get_line_width(brw);
1646 #else
1647 sf.LineWidth = brw_get_line_width(brw);
1648 #endif
1649
1650 if (ctx->Line.SmoothFlag) {
1651 sf.LineEndCapAntialiasingRegionWidth = _10pixels;
1652 #if GEN_GEN <= 7
1653 sf.AntialiasingEnable = true;
1654 #endif
1655 }
1656
1657 /* _NEW_POINT - Clamp to ARB_point_parameters user limits */
1658 point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
1659 /* Clamp to the hardware limits */
1660 sf.PointWidth = CLAMP(point_size, 0.125f, 255.875f);
1661
1662 /* _NEW_PROGRAM | _NEW_POINT, BRW_NEW_VUE_MAP_GEOM_OUT */
1663 if (use_state_point_size(brw))
1664 sf.PointWidthSource = State;
1665
1666 #if GEN_GEN >= 8
1667 /* _NEW_POINT | _NEW_MULTISAMPLE */
1668 if ((ctx->Point.SmoothFlag || _mesa_is_multisample_enabled(ctx)) &&
1669 !ctx->Point.PointSprite)
1670 sf.SmoothPointEnable = true;
1671 #endif
1672
1673 #if GEN_GEN == 10
1674 /* _NEW_BUFFERS
1675 * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
1676 */
1677 const bool multisampled_fbo =
1678 _mesa_geometric_samples(ctx->DrawBuffer) > 1;
1679 if (multisampled_fbo)
1680 sf.SmoothPointEnable = false;
1681 #endif
1682
1683 #if GEN_IS_G4X || GEN_GEN >= 5
1684 sf.AALineDistanceMode = AALINEDISTANCE_TRUE;
1685 #endif
1686
1687 /* _NEW_LIGHT */
1688 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
1689 sf.TriangleStripListProvokingVertexSelect = 2;
1690 sf.TriangleFanProvokingVertexSelect = 2;
1691 sf.LineStripListProvokingVertexSelect = 1;
1692 } else {
1693 sf.TriangleFanProvokingVertexSelect = 1;
1694 }
1695
1696 #if GEN_GEN == 6
1697 /* BRW_NEW_FS_PROG_DATA */
1698 const struct brw_wm_prog_data *wm_prog_data =
1699 brw_wm_prog_data(brw->wm.base.prog_data);
1700
1701 sf.AttributeSwizzleEnable = true;
1702 sf.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs;
1703
1704 /*
1705 * Window coordinates in an FBO are inverted, which means point
1706 * sprite origin must be inverted, too.
1707 */
1708 if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) == flip_y) {
1709 sf.PointSpriteTextureCoordinateOrigin = LOWERLEFT;
1710 } else {
1711 sf.PointSpriteTextureCoordinateOrigin = UPPERLEFT;
1712 }
1713
1714 /* BRW_NEW_VUE_MAP_GEOM_OUT | BRW_NEW_FRAGMENT_PROGRAM |
1715 * _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM | BRW_NEW_FS_PROG_DATA
1716 */
1717 uint32_t urb_entry_read_length;
1718 uint32_t urb_entry_read_offset;
1719 uint32_t point_sprite_enables;
1720 genX(calculate_attr_overrides)(brw, sf.Attribute, &point_sprite_enables,
1721 &urb_entry_read_length,
1722 &urb_entry_read_offset);
1723 sf.VertexURBEntryReadLength = urb_entry_read_length;
1724 sf.VertexURBEntryReadOffset = urb_entry_read_offset;
1725 sf.PointSpriteTextureCoordinateEnable = point_sprite_enables;
1726 sf.ConstantInterpolationEnable = wm_prog_data->flat_inputs;
1727 #endif
1728 }
1729 }
1730
1731 static const struct brw_tracked_state genX(sf_state) = {
1732 .dirty = {
1733 .mesa = _NEW_LIGHT |
1734 _NEW_LINE |
1735 _NEW_POINT |
1736 _NEW_PROGRAM |
1737 (GEN_GEN >= 6 ? _NEW_MULTISAMPLE : 0) |
1738 (GEN_GEN <= 7 ? _NEW_BUFFERS | _NEW_POLYGON : 0) |
1739 (GEN_GEN == 10 ? _NEW_BUFFERS : 0),
1740 .brw = BRW_NEW_BLORP |
1741 BRW_NEW_VUE_MAP_GEOM_OUT |
1742 (GEN_GEN <= 5 ? BRW_NEW_BATCH |
1743 BRW_NEW_PROGRAM_CACHE |
1744 BRW_NEW_SF_PROG_DATA |
1745 BRW_NEW_SF_VP |
1746 BRW_NEW_URB_FENCE
1747 : 0) |
1748 (GEN_GEN >= 6 ? BRW_NEW_CONTEXT : 0) |
1749 (GEN_GEN >= 6 && GEN_GEN <= 7 ?
1750 BRW_NEW_GS_PROG_DATA |
1751 BRW_NEW_PRIMITIVE |
1752 BRW_NEW_TES_PROG_DATA
1753 : 0) |
1754 (GEN_GEN == 6 ? BRW_NEW_FS_PROG_DATA |
1755 BRW_NEW_FRAGMENT_PROGRAM
1756 : 0),
1757 },
1758 .emit = genX(upload_sf),
1759 };
1760
1761 /* ---------------------------------------------------------------------- */
1762
1763 static bool
1764 brw_color_buffer_write_enabled(struct brw_context *brw)
1765 {
1766 struct gl_context *ctx = &brw->ctx;
1767 /* BRW_NEW_FRAGMENT_PROGRAM */
1768 const struct gl_program *fp = brw->programs[MESA_SHADER_FRAGMENT];
1769 unsigned i;
1770
1771 /* _NEW_BUFFERS */
1772 for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
1773 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
1774 uint64_t outputs_written = fp->info.outputs_written;
1775
1776 /* _NEW_COLOR */
1777 if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
1778 outputs_written & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
1779 GET_COLORMASK(ctx->Color.ColorMask, i)) {
1780 return true;
1781 }
1782 }
1783
1784 return false;
1785 }
1786
1787 static void
1788 genX(upload_wm)(struct brw_context *brw)
1789 {
1790 struct gl_context *ctx = &brw->ctx;
1791
1792 /* BRW_NEW_FS_PROG_DATA */
1793 const struct brw_wm_prog_data *wm_prog_data =
1794 brw_wm_prog_data(brw->wm.base.prog_data);
1795
1796 UNUSED bool writes_depth =
1797 wm_prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF;
1798 UNUSED struct brw_stage_state *stage_state = &brw->wm.base;
1799 UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
1800
1801 #if GEN_GEN == 6
1802 /* We can't fold this into gen6_upload_wm_push_constants(), because
1803 * according to the SNB PRM, vol 2 part 1 section 7.2.2
1804 * (3DSTATE_CONSTANT_PS [DevSNB]):
1805 *
1806 * "[DevSNB]: This packet must be followed by WM_STATE."
1807 */
1808 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_PS), wmcp) {
1809 if (wm_prog_data->base.nr_params != 0) {
1810 wmcp.Buffer0Valid = true;
1811 /* Pointer to the WM constant buffer. Covered by the set of
1812 * state flags from gen6_upload_wm_push_constants.
1813 */
1814 wmcp.ConstantBody.PointertoConstantBuffer0 = stage_state->push_const_offset;
1815 wmcp.ConstantBody.ConstantBuffer0ReadLength = stage_state->push_const_size - 1;
1816 }
1817 }
1818 #endif
1819
1820 #if GEN_GEN >= 6
1821 brw_batch_emit(brw, GENX(3DSTATE_WM), wm) {
1822 #else
1823 ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
1824 brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) {
1825 #endif
1826
1827 #if GEN_GEN <= 6
1828 wm._8PixelDispatchEnable = wm_prog_data->dispatch_8;
1829 wm._16PixelDispatchEnable = wm_prog_data->dispatch_16;
1830 wm._32PixelDispatchEnable = wm_prog_data->dispatch_32;
1831 #endif
1832
1833 #if GEN_GEN == 4
1834 /* On gen4, we only have one shader kernel */
1835 if (brw_wm_state_has_ksp(wm, 0)) {
1836 assert(brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0) == 0);
1837 wm.KernelStartPointer0 = KSP(brw, stage_state->prog_offset);
1838 wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 0);
1839 wm.DispatchGRFStartRegisterForConstantSetupData0 =
1840 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0);
1841 }
1842 #elif GEN_GEN == 5
1843 /* On gen5, we have multiple shader kernels but only one GRF start
1844 * register for all kernels
1845 */
1846 wm.KernelStartPointer0 = stage_state->prog_offset +
1847 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0);
1848 wm.KernelStartPointer1 = stage_state->prog_offset +
1849 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 1);
1850 wm.KernelStartPointer2 = stage_state->prog_offset +
1851 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 2);
1852
1853 wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 0);
1854 wm.GRFRegisterCount1 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 1);
1855 wm.GRFRegisterCount2 = brw_wm_prog_data_reg_blocks(wm_prog_data, wm, 2);
1856
1857 wm.DispatchGRFStartRegisterForConstantSetupData0 =
1858 wm_prog_data->base.dispatch_grf_start_reg;
1859
1860 /* Dispatch GRF Start should be the same for all shaders on gen5 */
1861 if (brw_wm_state_has_ksp(wm, 1)) {
1862 assert(wm_prog_data->base.dispatch_grf_start_reg ==
1863 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 1));
1864 }
1865 if (brw_wm_state_has_ksp(wm, 2)) {
1866 assert(wm_prog_data->base.dispatch_grf_start_reg ==
1867 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2));
1868 }
1869 #elif GEN_GEN == 6
1870 /* On gen6, we have multiple shader kernels and we no longer specify a
1871 * register count for each one.
1872 */
1873 wm.KernelStartPointer0 = stage_state->prog_offset +
1874 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0);
1875 wm.KernelStartPointer1 = stage_state->prog_offset +
1876 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 1);
1877 wm.KernelStartPointer2 = stage_state->prog_offset +
1878 brw_wm_prog_data_prog_offset(wm_prog_data, wm, 2);
1879
1880 wm.DispatchGRFStartRegisterForConstantSetupData0 =
1881 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0);
1882 wm.DispatchGRFStartRegisterForConstantSetupData1 =
1883 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 1);
1884 wm.DispatchGRFStartRegisterForConstantSetupData2 =
1885 brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2);
1886 #endif
1887
1888 #if GEN_GEN <= 5
1889 wm.ConstantURBEntryReadLength = wm_prog_data->base.curb_read_length;
1890 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1891 wm.ConstantURBEntryReadOffset = brw->curbe.wm_start * 2;
1892 wm.SetupURBEntryReadLength = wm_prog_data->num_varying_inputs * 2;
1893 wm.SetupURBEntryReadOffset = 0;
1894 wm.EarlyDepthTestEnable = true;
1895 #endif
1896
1897 #if GEN_GEN >= 6
1898 wm.LineAntialiasingRegionWidth = _10pixels;
1899 wm.LineEndCapAntialiasingRegionWidth = _05pixels;
1900
1901 wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT;
1902 wm.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes;
1903 #else
1904 if (stage_state->sampler_count)
1905 wm.SamplerStatePointer =
1906 ro_bo(brw->batch.state.bo, stage_state->sampler_offset);
1907
1908 wm.LineAntialiasingRegionWidth = _05pixels;
1909 wm.LineEndCapAntialiasingRegionWidth = _10pixels;
1910
1911 /* _NEW_POLYGON */
1912 if (ctx->Polygon.OffsetFill) {
1913 wm.GlobalDepthOffsetEnable = true;
1914 /* Something weird going on with legacy_global_depth_bias,
1915 * offset_constant, scaling and MRD. This value passes glean
1916 * but gives some odd results elsewere (eg. the
1917 * quad-offset-units test).
1918 */
1919 wm.GlobalDepthOffsetConstant = ctx->Polygon.OffsetUnits * 2;
1920
1921 /* This is the only value that passes glean:
1922 */
1923 wm.GlobalDepthOffsetScale = ctx->Polygon.OffsetFactor;
1924 }
1925
1926 wm.DepthCoefficientURBReadOffset = 1;
1927 #endif
1928
1929 /* BRW_NEW_STATS_WM */
1930 wm.StatisticsEnable = GEN_GEN >= 6 || brw->stats_wm;
1931
1932 #if GEN_GEN < 7
1933 if (wm_prog_data->base.use_alt_mode)
1934 wm.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
1935
1936 wm.SamplerCount = GEN_GEN == 5 ?
1937 0 : DIV_ROUND_UP(stage_state->sampler_count, 4);
1938
1939 wm.BindingTableEntryCount =
1940 wm_prog_data->base.binding_table.size_bytes / 4;
1941 wm.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
1942
1943 #if GEN_GEN == 6
1944 wm.DualSourceBlendEnable =
1945 wm_prog_data->dual_src_blend && (ctx->Color.BlendEnabled & 1) &&
1946 ctx->Color.Blend[0]._UsesDualSrc;
1947 wm.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
1948 wm.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs;
1949
1950 /* From the SNB PRM, volume 2 part 1, page 281:
1951 * "If the PS kernel does not need the Position XY Offsets
1952 * to compute a Position XY value, then this field should be
1953 * programmed to POSOFFSET_NONE."
1954 *
1955 * "SW Recommendation: If the PS kernel needs the Position Offsets
1956 * to compute a Position XY value, this field should match Position
1957 * ZW Interpolation Mode to ensure a consistent position.xyzw
1958 * computation."
1959 * We only require XY sample offsets. So, this recommendation doesn't
1960 * look useful at the moment. We might need this in future.
1961 */
1962 if (wm_prog_data->uses_pos_offset)
1963 wm.PositionXYOffsetSelect = POSOFFSET_SAMPLE;
1964 else
1965 wm.PositionXYOffsetSelect = POSOFFSET_NONE;
1966 #endif
1967
1968 if (wm_prog_data->base.total_scratch) {
1969 wm.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0);
1970 wm.PerThreadScratchSpace =
1971 ffs(stage_state->per_thread_scratch) - 11;
1972 }
1973
1974 wm.PixelShaderComputedDepth = writes_depth;
1975 #endif
1976
1977 /* _NEW_LINE */
1978 wm.LineStippleEnable = ctx->Line.StippleFlag;
1979
1980 /* _NEW_POLYGON */
1981 wm.PolygonStippleEnable = ctx->Polygon.StippleFlag;
1982
1983 #if GEN_GEN < 8
1984
1985 #if GEN_GEN >= 6
1986 wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
1987
1988 /* _NEW_BUFFERS */
1989 const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1;
1990
1991 if (multisampled_fbo) {
1992 /* _NEW_MULTISAMPLE */
1993 if (ctx->Multisample.Enabled)
1994 wm.MultisampleRasterizationMode = MSRASTMODE_ON_PATTERN;
1995 else
1996 wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL;
1997
1998 if (wm_prog_data->persample_dispatch)
1999 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
2000 else
2001 wm.MultisampleDispatchMode = MSDISPMODE_PERPIXEL;
2002 } else {
2003 wm.MultisampleRasterizationMode = MSRASTMODE_OFF_PIXEL;
2004 wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
2005 }
2006 #endif
2007 wm.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
2008 if (wm_prog_data->uses_kill ||
2009 _mesa_is_alpha_test_enabled(ctx) ||
2010 _mesa_is_alpha_to_coverage_enabled(ctx) ||
2011 (GEN_GEN >= 6 && wm_prog_data->uses_omask)) {
2012 wm.PixelShaderKillsPixel = true;
2013 }
2014
2015 /* _NEW_BUFFERS | _NEW_COLOR */
2016 if (brw_color_buffer_write_enabled(brw) || writes_depth ||
2017 wm.PixelShaderKillsPixel ||
2018 (GEN_GEN >= 6 && wm_prog_data->has_side_effects)) {
2019 wm.ThreadDispatchEnable = true;
2020 }
2021
2022 #if GEN_GEN >= 7
2023 wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
2024 wm.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask;
2025 #endif
2026
2027 /* The "UAV access enable" bits are unnecessary on HSW because they only
2028 * seem to have an effect on the HW-assisted coherency mechanism which we
2029 * don't need, and the rasterization-related UAV_ONLY flag and the
2030 * DISPATCH_ENABLE bit can be set independently from it.
2031 * C.f. gen8_upload_ps_extra().
2032 *
2033 * BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
2034 * _NEW_COLOR
2035 */
2036 #if GEN_IS_HASWELL
2037 if (!(brw_color_buffer_write_enabled(brw) || writes_depth) &&
2038 wm_prog_data->has_side_effects)
2039 wm.PSUAVonly = ON;
2040 #endif
2041 #endif
2042
2043 #if GEN_GEN >= 7
2044 /* BRW_NEW_FS_PROG_DATA */
2045 if (wm_prog_data->early_fragment_tests)
2046 wm.EarlyDepthStencilControl = EDSC_PREPS;
2047 else if (wm_prog_data->has_side_effects)
2048 wm.EarlyDepthStencilControl = EDSC_PSEXEC;
2049 #endif
2050 }
2051
2052 #if GEN_GEN <= 5
2053 if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) {
2054 brw_batch_emit(brw, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP), clamp) {
2055 clamp.GlobalDepthOffsetClamp = ctx->Polygon.OffsetClamp;
2056 }
2057
2058 brw->wm.offset_clamp = ctx->Polygon.OffsetClamp;
2059 }
2060 #endif
2061 }
2062
2063 static const struct brw_tracked_state genX(wm_state) = {
2064 .dirty = {
2065 .mesa = _NEW_LINE |
2066 _NEW_POLYGON |
2067 (GEN_GEN < 8 ? _NEW_BUFFERS |
2068 _NEW_COLOR :
2069 0) |
2070 (GEN_GEN == 6 ? _NEW_PROGRAM_CONSTANTS : 0) |
2071 (GEN_GEN < 6 ? _NEW_POLYGONSTIPPLE : 0) |
2072 (GEN_GEN < 8 && GEN_GEN >= 6 ? _NEW_MULTISAMPLE : 0),
2073 .brw = BRW_NEW_BLORP |
2074 BRW_NEW_FS_PROG_DATA |
2075 (GEN_GEN < 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION |
2076 BRW_NEW_FRAGMENT_PROGRAM |
2077 BRW_NEW_PROGRAM_CACHE |
2078 BRW_NEW_SAMPLER_STATE_TABLE |
2079 BRW_NEW_STATS_WM
2080 : 0) |
2081 (GEN_GEN < 7 ? BRW_NEW_BATCH : BRW_NEW_CONTEXT),
2082 },
2083 .emit = genX(upload_wm),
2084 };
2085
2086 /* ---------------------------------------------------------------------- */
2087
2088 /* We restrict scratch buffers to the bottom 32 bits of the address space
2089 * by using rw_32_bo().
2090 *
2091 * General State Base Address is a bit broken. If the address + size as
2092 * seen by STATE_BASE_ADDRESS overflows 48 bits, the GPU appears to treat
2093 * all accesses to the buffer as being out of bounds and returns zero.
2094 */
2095
2096 #define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix) \
2097 pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \
2098 /* WA_1606682166 */ \
2099 pkt.SamplerCount = \
2100 GEN_GEN == 11 ? \
2101 0 : \
2102 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \
2103 pkt.BindingTableEntryCount = \
2104 stage_prog_data->binding_table.size_bytes / 4; \
2105 pkt.FloatingPointMode = stage_prog_data->use_alt_mode; \
2106 \
2107 if (stage_prog_data->total_scratch) { \
2108 pkt.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0); \
2109 pkt.PerThreadScratchSpace = \
2110 ffs(stage_state->per_thread_scratch) - 11; \
2111 } \
2112 \
2113 pkt.DispatchGRFStartRegisterForURBData = \
2114 stage_prog_data->dispatch_grf_start_reg; \
2115 pkt.prefix##URBEntryReadLength = vue_prog_data->urb_read_length; \
2116 pkt.prefix##URBEntryReadOffset = 0; \
2117 \
2118 pkt.StatisticsEnable = true; \
2119 pkt.Enable = true;
2120
2121 static void
2122 genX(upload_vs_state)(struct brw_context *brw)
2123 {
2124 UNUSED struct gl_context *ctx = &brw->ctx;
2125 const struct gen_device_info *devinfo = &brw->screen->devinfo;
2126 struct brw_stage_state *stage_state = &brw->vs.base;
2127
2128 /* BRW_NEW_VS_PROG_DATA */
2129 const struct brw_vue_prog_data *vue_prog_data =
2130 brw_vue_prog_data(brw->vs.base.prog_data);
2131 const struct brw_stage_prog_data *stage_prog_data = &vue_prog_data->base;
2132
2133 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
2134 vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
2135 assert(GEN_GEN < 11 ||
2136 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
2137
2138 #if GEN_GEN == 6
2139 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
2140 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
2141 *
2142 * [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
2143 * command that causes the VS Function Enable to toggle. Pipeline
2144 * flush can be executed by sending a PIPE_CONTROL command with CS
2145 * stall bit set and a post sync operation.
2146 *
2147 * We've already done such a flush at the start of state upload, so we
2148 * don't need to do another one here.
2149 */
2150 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), cvs) {
2151 if (stage_state->push_const_size != 0) {
2152 cvs.Buffer0Valid = true;
2153 cvs.ConstantBody.PointertoConstantBuffer0 = stage_state->push_const_offset;
2154 cvs.ConstantBody.ConstantBuffer0ReadLength = stage_state->push_const_size - 1;
2155 }
2156 }
2157 #endif
2158
2159 if (GEN_GEN == 7 && devinfo->is_ivybridge)
2160 gen7_emit_vs_workaround_flush(brw);
2161
2162 #if GEN_GEN >= 6
2163 brw_batch_emit(brw, GENX(3DSTATE_VS), vs) {
2164 #else
2165 ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
2166 brw_state_emit(brw, GENX(VS_STATE), 32, &stage_state->state_offset, vs) {
2167 #endif
2168 INIT_THREAD_DISPATCH_FIELDS(vs, Vertex);
2169
2170 vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
2171
2172 #if GEN_GEN < 6
2173 vs.GRFRegisterCount = DIV_ROUND_UP(vue_prog_data->total_grf, 16) - 1;
2174 vs.ConstantURBEntryReadLength = stage_prog_data->curb_read_length;
2175 vs.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2;
2176
2177 vs.NumberofURBEntries = brw->urb.nr_vs_entries >> (GEN_GEN == 5 ? 2 : 0);
2178 vs.URBEntryAllocationSize = brw->urb.vsize - 1;
2179
2180 vs.MaximumNumberofThreads =
2181 CLAMP(brw->urb.nr_vs_entries / 2, 1, devinfo->max_vs_threads) - 1;
2182
2183 vs.StatisticsEnable = false;
2184 vs.SamplerStatePointer =
2185 ro_bo(brw->batch.state.bo, stage_state->sampler_offset);
2186 #endif
2187
2188 #if GEN_GEN == 5
2189 /* Force single program flow on Ironlake. We cannot reliably get
2190 * all applications working without it. See:
2191 * https://bugs.freedesktop.org/show_bug.cgi?id=29172
2192 *
2193 * The most notable and reliably failing application is the Humus
2194 * demo "CelShading"
2195 */
2196 vs.SingleProgramFlow = true;
2197 vs.SamplerCount = 0; /* hardware requirement */
2198 #endif
2199
2200 #if GEN_GEN >= 8
2201 vs.SIMD8DispatchEnable =
2202 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
2203
2204 vs.UserClipDistanceCullTestEnableBitmask =
2205 vue_prog_data->cull_distance_mask;
2206 #endif
2207 }
2208
2209 #if GEN_GEN == 6
2210 /* Based on my reading of the simulator, the VS constants don't get
2211 * pulled into the VS FF unit until an appropriate pipeline flush
2212 * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds
2213 * references to them into a little FIFO. The flushes are common,
2214 * but don't reliably happen between this and a 3DPRIMITIVE, causing
2215 * the primitive to use the wrong constants. Then the FIFO
2216 * containing the constant setup gets added to again on the next
2217 * constants change, and eventually when a flush does happen the
2218 * unit is overwhelmed by constant changes and dies.
2219 *
2220 * To avoid this, send a PIPE_CONTROL down the line that will
2221 * update the unit immediately loading the constants. The flush
2222 * type bits here were those set by the STATE_BASE_ADDRESS whose
2223 * move in a82a43e8d99e1715dd11c9c091b5ab734079b6a6 triggered the
2224 * bug reports that led to this workaround, and may be more than
2225 * what is strictly required to avoid the issue.
2226 */
2227 brw_emit_pipe_control_flush(brw,
2228 PIPE_CONTROL_DEPTH_STALL |
2229 PIPE_CONTROL_INSTRUCTION_INVALIDATE |
2230 PIPE_CONTROL_STATE_CACHE_INVALIDATE);
2231 #endif
2232 }
2233
2234 static const struct brw_tracked_state genX(vs_state) = {
2235 .dirty = {
2236 .mesa = (GEN_GEN == 6 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0),
2237 .brw = BRW_NEW_BATCH |
2238 BRW_NEW_BLORP |
2239 BRW_NEW_CONTEXT |
2240 BRW_NEW_VS_PROG_DATA |
2241 (GEN_GEN == 6 ? BRW_NEW_VERTEX_PROGRAM : 0) |
2242 (GEN_GEN <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION |
2243 BRW_NEW_PROGRAM_CACHE |
2244 BRW_NEW_SAMPLER_STATE_TABLE |
2245 BRW_NEW_URB_FENCE
2246 : 0),
2247 },
2248 .emit = genX(upload_vs_state),
2249 };
2250
2251 /* ---------------------------------------------------------------------- */
2252
2253 static void
2254 genX(upload_cc_viewport)(struct brw_context *brw)
2255 {
2256 struct gl_context *ctx = &brw->ctx;
2257
2258 /* BRW_NEW_VIEWPORT_COUNT */
2259 const unsigned viewport_count = brw->clip.viewport_count;
2260
2261 struct GENX(CC_VIEWPORT) ccv;
2262 uint32_t cc_vp_offset;
2263 uint32_t *cc_map =
2264 brw_state_batch(brw, 4 * GENX(CC_VIEWPORT_length) * viewport_count,
2265 32, &cc_vp_offset);
2266
2267 for (unsigned i = 0; i < viewport_count; i++) {
2268 /* _NEW_VIEWPORT | _NEW_TRANSFORM */
2269 const struct gl_viewport_attrib *vp = &ctx->ViewportArray[i];
2270 if (ctx->Transform.DepthClampNear && ctx->Transform.DepthClampFar) {
2271 ccv.MinimumDepth = MIN2(vp->Near, vp->Far);
2272 ccv.MaximumDepth = MAX2(vp->Near, vp->Far);
2273 } else if (ctx->Transform.DepthClampNear) {
2274 ccv.MinimumDepth = MIN2(vp->Near, vp->Far);
2275 ccv.MaximumDepth = 0.0;
2276 } else if (ctx->Transform.DepthClampFar) {
2277 ccv.MinimumDepth = 0.0;
2278 ccv.MaximumDepth = MAX2(vp->Near, vp->Far);
2279 } else {
2280 ccv.MinimumDepth = 0.0;
2281 ccv.MaximumDepth = 1.0;
2282 }
2283 GENX(CC_VIEWPORT_pack)(NULL, cc_map, &ccv);
2284 cc_map += GENX(CC_VIEWPORT_length);
2285 }
2286
2287 #if GEN_GEN >= 7
2288 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
2289 ptr.CCViewportPointer = cc_vp_offset;
2290 }
2291 #elif GEN_GEN == 6
2292 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) {
2293 vp.CCViewportStateChange = 1;
2294 vp.PointertoCC_VIEWPORT = cc_vp_offset;
2295 }
2296 #else
2297 brw->cc.vp_offset = cc_vp_offset;
2298 ctx->NewDriverState |= BRW_NEW_CC_VP;
2299 #endif
2300 }
2301
2302 const struct brw_tracked_state genX(cc_vp) = {
2303 .dirty = {
2304 .mesa = _NEW_TRANSFORM |
2305 _NEW_VIEWPORT,
2306 .brw = BRW_NEW_BATCH |
2307 BRW_NEW_BLORP |
2308 BRW_NEW_VIEWPORT_COUNT,
2309 },
2310 .emit = genX(upload_cc_viewport)
2311 };
2312
2313 /* ---------------------------------------------------------------------- */
2314
2315 static void
2316 set_scissor_bits(const struct gl_context *ctx, int i,
2317 bool flip_y, unsigned fb_width, unsigned fb_height,
2318 struct GENX(SCISSOR_RECT) *sc)
2319 {
2320 int bbox[4];
2321
2322 bbox[0] = MAX2(ctx->ViewportArray[i].X, 0);
2323 bbox[1] = MIN2(bbox[0] + ctx->ViewportArray[i].Width, fb_width);
2324 bbox[2] = CLAMP(ctx->ViewportArray[i].Y, 0, fb_height);
2325 bbox[3] = MIN2(bbox[2] + ctx->ViewportArray[i].Height, fb_height);
2326 _mesa_intersect_scissor_bounding_box(ctx, i, bbox);
2327
2328 if (bbox[0] == bbox[1] || bbox[2] == bbox[3]) {
2329 /* If the scissor was out of bounds and got clamped to 0 width/height
2330 * at the bounds, the subtraction of 1 from maximums could produce a
2331 * negative number and thus not clip anything. Instead, just provide
2332 * a min > max scissor inside the bounds, which produces the expected
2333 * no rendering.
2334 */
2335 sc->ScissorRectangleXMin = 1;
2336 sc->ScissorRectangleXMax = 0;
2337 sc->ScissorRectangleYMin = 1;
2338 sc->ScissorRectangleYMax = 0;
2339 } else if (!flip_y) {
2340 /* texmemory: Y=0=bottom */
2341 sc->ScissorRectangleXMin = bbox[0];
2342 sc->ScissorRectangleXMax = bbox[1] - 1;
2343 sc->ScissorRectangleYMin = bbox[2];
2344 sc->ScissorRectangleYMax = bbox[3] - 1;
2345 } else {
2346 /* memory: Y=0=top */
2347 sc->ScissorRectangleXMin = bbox[0];
2348 sc->ScissorRectangleXMax = bbox[1] - 1;
2349 sc->ScissorRectangleYMin = fb_height - bbox[3];
2350 sc->ScissorRectangleYMax = fb_height - bbox[2] - 1;
2351 }
2352 }
2353
2354 #if GEN_GEN >= 6
2355 static void
2356 genX(upload_scissor_state)(struct brw_context *brw)
2357 {
2358 struct gl_context *ctx = &brw->ctx;
2359 const bool flip_y = ctx->DrawBuffer->FlipY;
2360 struct GENX(SCISSOR_RECT) scissor;
2361 uint32_t scissor_state_offset;
2362 const unsigned int fb_width = _mesa_geometric_width(ctx->DrawBuffer);
2363 const unsigned int fb_height = _mesa_geometric_height(ctx->DrawBuffer);
2364 uint32_t *scissor_map;
2365
2366 /* BRW_NEW_VIEWPORT_COUNT */
2367 const unsigned viewport_count = brw->clip.viewport_count;
2368 /* GEN:BUG:1409725701:
2369 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
2370 * stored as an array of up to 16 elements. The location of first
2371 * element of the array, as specified by Pointer to SCISSOR_RECT, should
2372 * be aligned to a 64-byte boundary.
2373 */
2374 const unsigned alignment = 64;
2375 scissor_map = brw_state_batch(
2376 brw, GENX(SCISSOR_RECT_length) * sizeof(uint32_t) * viewport_count,
2377 alignment, &scissor_state_offset);
2378
2379 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */
2380
2381 /* The scissor only needs to handle the intersection of drawable and
2382 * scissor rect. Clipping to the boundaries of static shared buffers
2383 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
2384 *
2385 * Note that the hardware's coordinates are inclusive, while Mesa's min is
2386 * inclusive but max is exclusive.
2387 */
2388 for (unsigned i = 0; i < viewport_count; i++) {
2389 set_scissor_bits(ctx, i, flip_y, fb_width, fb_height, &scissor);
2390 GENX(SCISSOR_RECT_pack)(
2391 NULL, scissor_map + i * GENX(SCISSOR_RECT_length), &scissor);
2392 }
2393
2394 brw_batch_emit(brw, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
2395 ptr.ScissorRectPointer = scissor_state_offset;
2396 }
2397 }
2398
2399 static const struct brw_tracked_state genX(scissor_state) = {
2400 .dirty = {
2401 .mesa = _NEW_BUFFERS |
2402 _NEW_SCISSOR |
2403 _NEW_VIEWPORT,
2404 .brw = BRW_NEW_BATCH |
2405 BRW_NEW_BLORP |
2406 BRW_NEW_VIEWPORT_COUNT,
2407 },
2408 .emit = genX(upload_scissor_state),
2409 };
2410 #endif
2411
2412 /* ---------------------------------------------------------------------- */
2413
2414 static void
2415 genX(upload_sf_clip_viewport)(struct brw_context *brw)
2416 {
2417 struct gl_context *ctx = &brw->ctx;
2418 float y_scale, y_bias;
2419
2420 /* BRW_NEW_VIEWPORT_COUNT */
2421 const unsigned viewport_count = brw->clip.viewport_count;
2422
2423 /* _NEW_BUFFERS */
2424 const bool flip_y = ctx->DrawBuffer->FlipY;
2425 const uint32_t fb_width = (float)_mesa_geometric_width(ctx->DrawBuffer);
2426 const uint32_t fb_height = (float)_mesa_geometric_height(ctx->DrawBuffer);
2427
2428 #if GEN_GEN >= 7
2429 #define clv sfv
2430 struct GENX(SF_CLIP_VIEWPORT) sfv;
2431 uint32_t sf_clip_vp_offset;
2432 uint32_t *sf_clip_map =
2433 brw_state_batch(brw, GENX(SF_CLIP_VIEWPORT_length) * 4 * viewport_count,
2434 64, &sf_clip_vp_offset);
2435 #else
2436 struct GENX(SF_VIEWPORT) sfv;
2437 struct GENX(CLIP_VIEWPORT) clv;
2438 uint32_t sf_vp_offset, clip_vp_offset;
2439 uint32_t *sf_map =
2440 brw_state_batch(brw, GENX(SF_VIEWPORT_length) * 4 * viewport_count,
2441 32, &sf_vp_offset);
2442 uint32_t *clip_map =
2443 brw_state_batch(brw, GENX(CLIP_VIEWPORT_length) * 4 * viewport_count,
2444 32, &clip_vp_offset);
2445 #endif
2446
2447 /* _NEW_BUFFERS */
2448 if (flip_y) {
2449 y_scale = -1.0;
2450 y_bias = (float)fb_height;
2451 } else {
2452 y_scale = 1.0;
2453 y_bias = 0;
2454 }
2455
2456 for (unsigned i = 0; i < brw->clip.viewport_count; i++) {
2457 /* _NEW_VIEWPORT: Guardband Clipping */
2458 float scale[3], translate[3], gb_xmin, gb_xmax, gb_ymin, gb_ymax;
2459 _mesa_get_viewport_xform(ctx, i, scale, translate);
2460
2461 sfv.ViewportMatrixElementm00 = scale[0];
2462 sfv.ViewportMatrixElementm11 = scale[1] * y_scale,
2463 sfv.ViewportMatrixElementm22 = scale[2],
2464 sfv.ViewportMatrixElementm30 = translate[0],
2465 sfv.ViewportMatrixElementm31 = translate[1] * y_scale + y_bias,
2466 sfv.ViewportMatrixElementm32 = translate[2],
2467 gen_calculate_guardband_size(fb_width, fb_height,
2468 sfv.ViewportMatrixElementm00,
2469 sfv.ViewportMatrixElementm11,
2470 sfv.ViewportMatrixElementm30,
2471 sfv.ViewportMatrixElementm31,
2472 &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax);
2473
2474
2475 clv.XMinClipGuardband = gb_xmin;
2476 clv.XMaxClipGuardband = gb_xmax;
2477 clv.YMinClipGuardband = gb_ymin;
2478 clv.YMaxClipGuardband = gb_ymax;
2479
2480 #if GEN_GEN < 6
2481 set_scissor_bits(ctx, i, flip_y, fb_width, fb_height,
2482 &sfv.ScissorRectangle);
2483 #elif GEN_GEN >= 8
2484 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport
2485 * The hardware will take the intersection of the drawing rectangle,
2486 * scissor rectangle, and the viewport extents. However, emitting
2487 * 3DSTATE_DRAWING_RECTANGLE is expensive since it requires a full
2488 * pipeline stall so we're better off just being a little more clever
2489 * with our viewport so we can emit it once at context creation time.
2490 */
2491 const float viewport_Xmin = MAX2(ctx->ViewportArray[i].X, 0);
2492 const float viewport_Ymin = MAX2(ctx->ViewportArray[i].Y, 0);
2493 const float viewport_Xmax =
2494 MIN2(ctx->ViewportArray[i].X + ctx->ViewportArray[i].Width, fb_width);
2495 const float viewport_Ymax =
2496 MIN2(ctx->ViewportArray[i].Y + ctx->ViewportArray[i].Height, fb_height);
2497
2498 if (flip_y) {
2499 sfv.XMinViewPort = viewport_Xmin;
2500 sfv.XMaxViewPort = viewport_Xmax - 1;
2501 sfv.YMinViewPort = fb_height - viewport_Ymax;
2502 sfv.YMaxViewPort = fb_height - viewport_Ymin - 1;
2503 } else {
2504 sfv.XMinViewPort = viewport_Xmin;
2505 sfv.XMaxViewPort = viewport_Xmax - 1;
2506 sfv.YMinViewPort = viewport_Ymin;
2507 sfv.YMaxViewPort = viewport_Ymax - 1;
2508 }
2509 #endif
2510
2511 #if GEN_GEN >= 7
2512 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_map, &sfv);
2513 sf_clip_map += GENX(SF_CLIP_VIEWPORT_length);
2514 #else
2515 GENX(SF_VIEWPORT_pack)(NULL, sf_map, &sfv);
2516 GENX(CLIP_VIEWPORT_pack)(NULL, clip_map, &clv);
2517 sf_map += GENX(SF_VIEWPORT_length);
2518 clip_map += GENX(CLIP_VIEWPORT_length);
2519 #endif
2520 }
2521
2522 #if GEN_GEN >= 7
2523 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
2524 ptr.SFClipViewportPointer = sf_clip_vp_offset;
2525 }
2526 #elif GEN_GEN == 6
2527 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) {
2528 vp.SFViewportStateChange = 1;
2529 vp.CLIPViewportStateChange = 1;
2530 vp.PointertoCLIP_VIEWPORT = clip_vp_offset;
2531 vp.PointertoSF_VIEWPORT = sf_vp_offset;
2532 }
2533 #else
2534 brw->sf.vp_offset = sf_vp_offset;
2535 brw->clip.vp_offset = clip_vp_offset;
2536 brw->ctx.NewDriverState |= BRW_NEW_SF_VP | BRW_NEW_CLIP_VP;
2537 #endif
2538 }
2539
2540 static const struct brw_tracked_state genX(sf_clip_viewport) = {
2541 .dirty = {
2542 .mesa = _NEW_BUFFERS |
2543 _NEW_VIEWPORT |
2544 (GEN_GEN <= 5 ? _NEW_SCISSOR : 0),
2545 .brw = BRW_NEW_BATCH |
2546 BRW_NEW_BLORP |
2547 BRW_NEW_VIEWPORT_COUNT,
2548 },
2549 .emit = genX(upload_sf_clip_viewport),
2550 };
2551
2552 /* ---------------------------------------------------------------------- */
2553
2554 static void
2555 genX(upload_gs_state)(struct brw_context *brw)
2556 {
2557 UNUSED struct gl_context *ctx = &brw->ctx;
2558 UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
2559 const struct brw_stage_state *stage_state = &brw->gs.base;
2560 const struct gl_program *gs_prog = brw->programs[MESA_SHADER_GEOMETRY];
2561 /* BRW_NEW_GEOMETRY_PROGRAM */
2562 bool active = GEN_GEN >= 6 && gs_prog;
2563
2564 /* BRW_NEW_GS_PROG_DATA */
2565 struct brw_stage_prog_data *stage_prog_data = stage_state->prog_data;
2566 UNUSED const struct brw_vue_prog_data *vue_prog_data =
2567 brw_vue_prog_data(stage_prog_data);
2568 #if GEN_GEN >= 7
2569 const struct brw_gs_prog_data *gs_prog_data =
2570 brw_gs_prog_data(stage_prog_data);
2571 #endif
2572
2573 #if GEN_GEN == 6
2574 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_GS), cgs) {
2575 if (active && stage_state->push_const_size != 0) {
2576 cgs.Buffer0Valid = true;
2577 cgs.ConstantBody.PointertoConstantBuffer0 = stage_state->push_const_offset;
2578 cgs.ConstantBody.ConstantBuffer0ReadLength = stage_state->push_const_size - 1;
2579 }
2580 }
2581 #endif
2582
2583 #if GEN_GEN == 7 && !GEN_IS_HASWELL
2584 /**
2585 * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
2586 * Geometry > Geometry Shader > State:
2587 *
2588 * "Note: Because of corruption in IVB:GT2, software needs to flush the
2589 * whole fixed function pipeline when the GS enable changes value in
2590 * the 3DSTATE_GS."
2591 *
2592 * The hardware architects have clarified that in this context "flush the
2593 * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
2594 * Stall" bit set.
2595 */
2596 if (devinfo->gt == 2 && brw->gs.enabled != active)
2597 gen7_emit_cs_stall_flush(brw);
2598 #endif
2599
2600 #if GEN_GEN >= 6
2601 brw_batch_emit(brw, GENX(3DSTATE_GS), gs) {
2602 #else
2603 ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
2604 brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) {
2605 #endif
2606
2607 #if GEN_GEN >= 6
2608 if (active) {
2609 INIT_THREAD_DISPATCH_FIELDS(gs, Vertex);
2610
2611 #if GEN_GEN >= 7
2612 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1;
2613 gs.OutputTopology = gs_prog_data->output_topology;
2614 gs.ControlDataHeaderSize =
2615 gs_prog_data->control_data_header_size_hwords;
2616
2617 gs.InstanceControl = gs_prog_data->invocations - 1;
2618 gs.DispatchMode = vue_prog_data->dispatch_mode;
2619
2620 gs.IncludePrimitiveID = gs_prog_data->include_primitive_id;
2621
2622 gs.ControlDataFormat = gs_prog_data->control_data_format;
2623 #endif
2624
2625 /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between
2626 * Ivy Bridge and Haswell.
2627 *
2628 * On Ivy Bridge, setting this bit causes the vertices of a triangle
2629 * strip to be delivered to the geometry shader in an order that does
2630 * not strictly follow the OpenGL spec, but preserves triangle
2631 * orientation. For example, if the vertices are (1, 2, 3, 4, 5), then
2632 * the geometry shader sees triangles:
2633 *
2634 * (1, 2, 3), (2, 4, 3), (3, 4, 5)
2635 *
2636 * (Clearing the bit is even worse, because it fails to preserve
2637 * orientation).
2638 *
2639 * Triangle strips with adjacency always ordered in a way that preserves
2640 * triangle orientation but does not strictly follow the OpenGL spec,
2641 * regardless of the setting of this bit.
2642 *
2643 * On Haswell, both triangle strips and triangle strips with adjacency
2644 * are always ordered in a way that preserves triangle orientation.
2645 * Setting this bit causes the ordering to strictly follow the OpenGL
2646 * spec.
2647 *
2648 * So in either case we want to set the bit. Unfortunately on Ivy
2649 * Bridge this will get the order close to correct but not perfect.
2650 */
2651 gs.ReorderMode = TRAILING;
2652 gs.MaximumNumberofThreads =
2653 GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1)
2654 : (devinfo->max_gs_threads - 1);
2655
2656 #if GEN_GEN < 7
2657 gs.SOStatisticsEnable = true;
2658 if (gs_prog->info.has_transform_feedback_varyings)
2659 gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx);
2660
2661 /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it
2662 * was previously done for gen6.
2663 *
2664 * TODO: test with both disabled to see if the HW is behaving
2665 * as expected, like in gen7.
2666 */
2667 gs.SingleProgramFlow = true;
2668 gs.VectorMaskEnable = true;
2669 #endif
2670
2671 #if GEN_GEN >= 8
2672 gs.ExpectedVertexCount = gs_prog_data->vertices_in;
2673
2674 if (gs_prog_data->static_vertex_count != -1) {
2675 gs.StaticOutput = true;
2676 gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count;
2677 }
2678 gs.IncludeVertexHandles = vue_prog_data->include_vue_handles;
2679
2680 gs.UserClipDistanceCullTestEnableBitmask =
2681 vue_prog_data->cull_distance_mask;
2682
2683 const int urb_entry_write_offset = 1;
2684 const uint32_t urb_entry_output_length =
2685 DIV_ROUND_UP(vue_prog_data->vue_map.num_slots, 2) -
2686 urb_entry_write_offset;
2687
2688 gs.VertexURBEntryOutputReadOffset = urb_entry_write_offset;
2689 gs.VertexURBEntryOutputLength = MAX2(urb_entry_output_length, 1);
2690 #endif
2691 }
2692 #endif
2693
2694 #if GEN_GEN <= 6
2695 if (!active && brw->ff_gs.prog_active) {
2696 /* In gen6, transform feedback for the VS stage is done with an
2697 * ad-hoc GS program. This function provides the needed 3DSTATE_GS
2698 * for this.
2699 */
2700 gs.KernelStartPointer = KSP(brw, brw->ff_gs.prog_offset);
2701 gs.SingleProgramFlow = true;
2702 gs.DispatchGRFStartRegisterForURBData = GEN_GEN == 6 ? 2 : 1;
2703 gs.VertexURBEntryReadLength = brw->ff_gs.prog_data->urb_read_length;
2704
2705 #if GEN_GEN <= 5
2706 gs.GRFRegisterCount =
2707 DIV_ROUND_UP(brw->ff_gs.prog_data->total_grf, 16) - 1;
2708 /* BRW_NEW_URB_FENCE */
2709 gs.NumberofURBEntries = brw->urb.nr_gs_entries;
2710 gs.URBEntryAllocationSize = brw->urb.vsize - 1;
2711 gs.MaximumNumberofThreads = brw->urb.nr_gs_entries >= 8 ? 1 : 0;
2712 gs.FloatingPointMode = FLOATING_POINT_MODE_Alternate;
2713 #else
2714 gs.Enable = true;
2715 gs.VectorMaskEnable = true;
2716 gs.SVBIPayloadEnable = true;
2717 gs.SVBIPostIncrementEnable = true;
2718 gs.SVBIPostIncrementValue =
2719 brw->ff_gs.prog_data->svbi_postincrement_value;
2720 gs.SOStatisticsEnable = true;
2721 gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1;
2722 #endif
2723 }
2724 #endif
2725 if (!active && !brw->ff_gs.prog_active) {
2726 #if GEN_GEN < 8
2727 gs.DispatchGRFStartRegisterForURBData = 1;
2728 #if GEN_GEN >= 7
2729 gs.IncludeVertexHandles = true;
2730 #endif
2731 #endif
2732 }
2733
2734 #if GEN_GEN >= 6
2735 gs.StatisticsEnable = true;
2736 #endif
2737 #if GEN_GEN == 5 || GEN_GEN == 6
2738 gs.RenderingEnabled = true;
2739 #endif
2740 #if GEN_GEN <= 5
2741 gs.MaximumVPIndex = brw->clip.viewport_count - 1;
2742 #endif
2743 }
2744
2745 #if GEN_GEN == 6
2746 brw->gs.enabled = active;
2747 #endif
2748 }
2749
2750 static const struct brw_tracked_state genX(gs_state) = {
2751 .dirty = {
2752 .mesa = (GEN_GEN == 6 ? _NEW_PROGRAM_CONSTANTS : 0),
2753 .brw = BRW_NEW_BATCH |
2754 BRW_NEW_BLORP |
2755 (GEN_GEN <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION |
2756 BRW_NEW_PROGRAM_CACHE |
2757 BRW_NEW_URB_FENCE |
2758 BRW_NEW_VIEWPORT_COUNT
2759 : 0) |
2760 (GEN_GEN >= 6 ? BRW_NEW_CONTEXT |
2761 BRW_NEW_GEOMETRY_PROGRAM |
2762 BRW_NEW_GS_PROG_DATA
2763 : 0) |
2764 (GEN_GEN < 7 ? BRW_NEW_FF_GS_PROG_DATA : 0),
2765 },
2766 .emit = genX(upload_gs_state),
2767 };
2768
2769 /* ---------------------------------------------------------------------- */
2770
2771 UNUSED static GLenum
2772 fix_dual_blend_alpha_to_one(GLenum function)
2773 {
2774 switch (function) {
2775 case GL_SRC1_ALPHA:
2776 return GL_ONE;
2777
2778 case GL_ONE_MINUS_SRC1_ALPHA:
2779 return GL_ZERO;
2780 }
2781
2782 return function;
2783 }
2784
2785 #define blend_factor(x) brw_translate_blend_factor(x)
2786 #define blend_eqn(x) brw_translate_blend_equation(x)
2787
2788 /**
2789 * Modify blend function to force destination alpha to 1.0
2790 *
2791 * If \c function specifies a blend function that uses destination alpha,
2792 * replace it with a function that hard-wires destination alpha to 1.0. This
2793 * is used when rendering to xRGB targets.
2794 */
2795 static GLenum
2796 brw_fix_xRGB_alpha(GLenum function)
2797 {
2798 switch (function) {
2799 case GL_DST_ALPHA:
2800 return GL_ONE;
2801
2802 case GL_ONE_MINUS_DST_ALPHA:
2803 case GL_SRC_ALPHA_SATURATE:
2804 return GL_ZERO;
2805 }
2806
2807 return function;
2808 }
2809
2810 #if GEN_GEN >= 6
2811 typedef struct GENX(BLEND_STATE_ENTRY) BLEND_ENTRY_GENXML;
2812 #else
2813 typedef struct GENX(COLOR_CALC_STATE) BLEND_ENTRY_GENXML;
2814 #endif
2815
2816 UNUSED static bool
2817 set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i,
2818 bool alpha_to_one)
2819 {
2820 struct gl_context *ctx = &brw->ctx;
2821
2822 /* _NEW_BUFFERS */
2823 const struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
2824
2825 bool independent_alpha_blend = false;
2826
2827 /* Used for implementing the following bit of GL_EXT_texture_integer:
2828 * "Per-fragment operations that require floating-point color
2829 * components, including multisample alpha operations, alpha test,
2830 * blending, and dithering, have no effect when the corresponding
2831 * colors are written to an integer color buffer."
2832 */
2833 const bool integer = ctx->DrawBuffer->_IntegerBuffers & (0x1 << i);
2834
2835 const unsigned blend_enabled = GEN_GEN >= 6 ?
2836 ctx->Color.BlendEnabled & (1 << i) : ctx->Color.BlendEnabled;
2837
2838 /* _NEW_COLOR */
2839 if (ctx->Color.ColorLogicOpEnabled) {
2840 GLenum rb_type = rb ? _mesa_get_format_datatype(rb->Format)
2841 : GL_UNSIGNED_NORMALIZED;
2842 WARN_ONCE(ctx->Color.LogicOp != GL_COPY &&
2843 rb_type != GL_UNSIGNED_NORMALIZED &&
2844 rb_type != GL_FLOAT, "Ignoring %s logic op on %s "
2845 "renderbuffer\n",
2846 _mesa_enum_to_string(ctx->Color.LogicOp),
2847 _mesa_enum_to_string(rb_type));
2848 if (GEN_GEN >= 8 || rb_type == GL_UNSIGNED_NORMALIZED) {
2849 entry->LogicOpEnable = true;
2850 entry->LogicOpFunction = ctx->Color._LogicOp;
2851 }
2852 } else if (blend_enabled &&
2853 ctx->Color._AdvancedBlendMode == BLEND_NONE
2854 && (GEN_GEN <= 5 || !integer)) {
2855 GLenum eqRGB = ctx->Color.Blend[i].EquationRGB;
2856 GLenum eqA = ctx->Color.Blend[i].EquationA;
2857 GLenum srcRGB = ctx->Color.Blend[i].SrcRGB;
2858 GLenum dstRGB = ctx->Color.Blend[i].DstRGB;
2859 GLenum srcA = ctx->Color.Blend[i].SrcA;
2860 GLenum dstA = ctx->Color.Blend[i].DstA;
2861
2862 if (eqRGB == GL_MIN || eqRGB == GL_MAX)
2863 srcRGB = dstRGB = GL_ONE;
2864
2865 if (eqA == GL_MIN || eqA == GL_MAX)
2866 srcA = dstA = GL_ONE;
2867
2868 /* Due to hardware limitations, the destination may have information
2869 * in an alpha channel even when the format specifies no alpha
2870 * channel. In order to avoid getting any incorrect blending due to
2871 * that alpha channel, coerce the blend factors to values that will
2872 * not read the alpha channel, but will instead use the correct
2873 * implicit value for alpha.
2874 */
2875 if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat,
2876 GL_TEXTURE_ALPHA_TYPE)) {
2877 srcRGB = brw_fix_xRGB_alpha(srcRGB);
2878 srcA = brw_fix_xRGB_alpha(srcA);
2879 dstRGB = brw_fix_xRGB_alpha(dstRGB);
2880 dstA = brw_fix_xRGB_alpha(dstA);
2881 }
2882
2883 /* From the BLEND_STATE docs, DWord 0, Bit 29 (AlphaToOne Enable):
2884 * "If Dual Source Blending is enabled, this bit must be disabled."
2885 *
2886 * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO,
2887 * and leave it enabled anyway.
2888 */
2889 if (GEN_GEN >= 6 && ctx->Color.Blend[i]._UsesDualSrc && alpha_to_one) {
2890 srcRGB = fix_dual_blend_alpha_to_one(srcRGB);
2891 srcA = fix_dual_blend_alpha_to_one(srcA);
2892 dstRGB = fix_dual_blend_alpha_to_one(dstRGB);
2893 dstA = fix_dual_blend_alpha_to_one(dstA);
2894 }
2895
2896 /* BRW_NEW_FS_PROG_DATA */
2897 const struct brw_wm_prog_data *wm_prog_data =
2898 brw_wm_prog_data(brw->wm.base.prog_data);
2899
2900 /* The Dual Source Blending documentation says:
2901 *
2902 * "If SRC1 is included in a src/dst blend factor and
2903 * a DualSource RT Write message is not used, results
2904 * are UNDEFINED. (This reflects the same restriction in DX APIs,
2905 * where undefined results are produced if “o1” is not written
2906 * by a PS – there are no default values defined).
2907 * If SRC1 is not included in a src/dst blend factor,
2908 * dual source blending must be disabled."
2909 *
2910 * There is no way to gracefully fix this undefined situation
2911 * so we just disable the blending to prevent possible issues.
2912 */
2913 entry->ColorBufferBlendEnable =
2914 !ctx->Color.Blend[0]._UsesDualSrc || wm_prog_data->dual_src_blend;
2915
2916 entry->DestinationBlendFactor = blend_factor(dstRGB);
2917 entry->SourceBlendFactor = blend_factor(srcRGB);
2918 entry->DestinationAlphaBlendFactor = blend_factor(dstA);
2919 entry->SourceAlphaBlendFactor = blend_factor(srcA);
2920 entry->ColorBlendFunction = blend_eqn(eqRGB);
2921 entry->AlphaBlendFunction = blend_eqn(eqA);
2922
2923 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB)
2924 independent_alpha_blend = true;
2925 }
2926
2927 return independent_alpha_blend;
2928 }
2929
2930 #if GEN_GEN >= 6
2931 static void
2932 genX(upload_blend_state)(struct brw_context *brw)
2933 {
2934 struct gl_context *ctx = &brw->ctx;
2935 int size;
2936
2937 /* We need at least one BLEND_STATE written, because we might do
2938 * thread dispatch even if _NumColorDrawBuffers is 0 (for example
2939 * for computed depth or alpha test), which will do an FB write
2940 * with render target 0, which will reference BLEND_STATE[0] for
2941 * alpha test enable.
2942 */
2943 int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers;
2944 if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled)
2945 nr_draw_buffers = 1;
2946
2947 size = GENX(BLEND_STATE_ENTRY_length) * 4 * nr_draw_buffers;
2948 #if GEN_GEN >= 8
2949 size += GENX(BLEND_STATE_length) * 4;
2950 #endif
2951
2952 uint32_t *blend_map;
2953 blend_map = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset);
2954
2955 #if GEN_GEN >= 8
2956 struct GENX(BLEND_STATE) blend = { 0 };
2957 {
2958 #else
2959 for (int i = 0; i < nr_draw_buffers; i++) {
2960 struct GENX(BLEND_STATE_ENTRY) entry = { 0 };
2961 #define blend entry
2962 #endif
2963 /* OpenGL specification 3.3 (page 196), section 4.1.3 says:
2964 * "If drawbuffer zero is not NONE and the buffer it references has an
2965 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
2966 * operations are skipped."
2967 */
2968 if (!(ctx->DrawBuffer->_IntegerBuffers & 0x1)) {
2969 /* _NEW_MULTISAMPLE */
2970 if (_mesa_is_multisample_enabled(ctx)) {
2971 if (ctx->Multisample.SampleAlphaToCoverage) {
2972 blend.AlphaToCoverageEnable = true;
2973 blend.AlphaToCoverageDitherEnable = GEN_GEN >= 7;
2974 }
2975 if (ctx->Multisample.SampleAlphaToOne)
2976 blend.AlphaToOneEnable = true;
2977 }
2978
2979 /* _NEW_COLOR */
2980 if (ctx->Color.AlphaEnabled) {
2981 blend.AlphaTestEnable = true;
2982 blend.AlphaTestFunction =
2983 intel_translate_compare_func(ctx->Color.AlphaFunc);
2984 }
2985
2986 if (ctx->Color.DitherFlag) {
2987 blend.ColorDitherEnable = true;
2988 }
2989 }
2990
2991 #if GEN_GEN >= 8
2992 for (int i = 0; i < nr_draw_buffers; i++) {
2993 struct GENX(BLEND_STATE_ENTRY) entry = { 0 };
2994 #else
2995 {
2996 #endif
2997 blend.IndependentAlphaBlendEnable =
2998 set_blend_entry_bits(brw, &entry, i, blend.AlphaToOneEnable) ||
2999 blend.IndependentAlphaBlendEnable;
3000
3001 /* See section 8.1.6 "Pre-Blend Color Clamping" of the
3002 * SandyBridge PRM Volume 2 Part 1 for HW requirements.
3003 *
3004 * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR
3005 * clamping in the fragment shader. For its clamping of
3006 * blending, the spec says:
3007 *
3008 * "RESOLVED: For fixed-point color buffers, the inputs and
3009 * the result of the blending equation are clamped. For
3010 * floating-point color buffers, no clamping occurs."
3011 *
3012 * So, generally, we want clamping to the render target's range.
3013 * And, good news, the hardware tables for both pre- and
3014 * post-blend color clamping are either ignored, or any are
3015 * allowed, or clamping is required but RT range clamping is a
3016 * valid option.
3017 */
3018 entry.PreBlendColorClampEnable = true;
3019 entry.PostBlendColorClampEnable = true;
3020 entry.ColorClampRange = COLORCLAMP_RTFORMAT;
3021
3022 entry.WriteDisableRed = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 0);
3023 entry.WriteDisableGreen = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 1);
3024 entry.WriteDisableBlue = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 2);
3025 entry.WriteDisableAlpha = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 3);
3026
3027 #if GEN_GEN >= 8
3028 GENX(BLEND_STATE_ENTRY_pack)(NULL, &blend_map[1 + i * 2], &entry);
3029 #else
3030 GENX(BLEND_STATE_ENTRY_pack)(NULL, &blend_map[i * 2], &entry);
3031 #endif
3032 }
3033 }
3034
3035 #if GEN_GEN >= 8
3036 GENX(BLEND_STATE_pack)(NULL, blend_map, &blend);
3037 #endif
3038
3039 #if GEN_GEN < 7
3040 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
3041 ptr.PointertoBLEND_STATE = brw->cc.blend_state_offset;
3042 ptr.BLEND_STATEChange = true;
3043 }
3044 #else
3045 brw_batch_emit(brw, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) {
3046 ptr.BlendStatePointer = brw->cc.blend_state_offset;
3047 #if GEN_GEN >= 8
3048 ptr.BlendStatePointerValid = true;
3049 #endif
3050 }
3051 #endif
3052 }
3053
3054 UNUSED static const struct brw_tracked_state genX(blend_state) = {
3055 .dirty = {
3056 .mesa = _NEW_BUFFERS |
3057 _NEW_COLOR |
3058 _NEW_MULTISAMPLE,
3059 .brw = BRW_NEW_BATCH |
3060 BRW_NEW_BLORP |
3061 BRW_NEW_FS_PROG_DATA |
3062 BRW_NEW_STATE_BASE_ADDRESS,
3063 },
3064 .emit = genX(upload_blend_state),
3065 };
3066 #endif
3067
3068 /* ---------------------------------------------------------------------- */
3069
3070 #if GEN_GEN >= 7
3071 UNUSED static const uint32_t push_constant_opcodes[] = {
3072 [MESA_SHADER_VERTEX] = 21,
3073 [MESA_SHADER_TESS_CTRL] = 25, /* HS */
3074 [MESA_SHADER_TESS_EVAL] = 26, /* DS */
3075 [MESA_SHADER_GEOMETRY] = 22,
3076 [MESA_SHADER_FRAGMENT] = 23,
3077 [MESA_SHADER_COMPUTE] = 0,
3078 };
3079
3080 static void
3081 genX(upload_push_constant_packets)(struct brw_context *brw)
3082 {
3083 const struct gen_device_info *devinfo = &brw->screen->devinfo;
3084 struct gl_context *ctx = &brw->ctx;
3085
3086 UNUSED uint32_t mocs = GEN_GEN < 8 ? GEN7_MOCS_L3 : 0;
3087
3088 struct brw_stage_state *stage_states[] = {
3089 &brw->vs.base,
3090 &brw->tcs.base,
3091 &brw->tes.base,
3092 &brw->gs.base,
3093 &brw->wm.base,
3094 };
3095
3096 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail &&
3097 stage_states[MESA_SHADER_VERTEX]->push_constants_dirty)
3098 gen7_emit_vs_workaround_flush(brw);
3099
3100 for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
3101 struct brw_stage_state *stage_state = stage_states[stage];
3102 UNUSED struct gl_program *prog = ctx->_Shader->CurrentProgram[stage];
3103
3104 if (!stage_state->push_constants_dirty)
3105 continue;
3106
3107 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) {
3108 pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
3109 if (stage_state->prog_data) {
3110 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3111 /* The Skylake PRM contains the following restriction:
3112 *
3113 * "The driver must ensure The following case does not occur
3114 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3115 * buffer 3 read length equal to zero committed followed by a
3116 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3117 * zero committed."
3118 *
3119 * To avoid this, we program the buffers in the highest slots.
3120 * This way, slot 0 is only used if slot 3 is also used.
3121 */
3122 int n = 3;
3123
3124 for (int i = 3; i >= 0; i--) {
3125 const struct brw_ubo_range *range =
3126 &stage_state->prog_data->ubo_ranges[i];
3127
3128 if (range->length == 0)
3129 continue;
3130
3131 const struct gl_uniform_block *block =
3132 prog->sh.UniformBlocks[range->block];
3133 const struct gl_buffer_binding *binding =
3134 &ctx->UniformBufferBindings[block->Binding];
3135
3136 if (!binding->BufferObject) {
3137 static unsigned msg_id = 0;
3138 _mesa_gl_debugf(ctx, &msg_id, MESA_DEBUG_SOURCE_API,
3139 MESA_DEBUG_TYPE_UNDEFINED,
3140 MESA_DEBUG_SEVERITY_HIGH,
3141 "UBO %d unbound, %s shader uniform data "
3142 "will be undefined.",
3143 range->block,
3144 _mesa_shader_stage_to_string(stage));
3145 continue;
3146 }
3147
3148 assert(binding->Offset % 32 == 0);
3149
3150 struct brw_bo *bo = intel_bufferobj_buffer(brw,
3151 intel_buffer_object(binding->BufferObject),
3152 binding->Offset, range->length * 32, false);
3153
3154 pkt.ConstantBody.ReadLength[n] = range->length;
3155 pkt.ConstantBody.Buffer[n] =
3156 ro_bo(bo, range->start * 32 + binding->Offset);
3157 n--;
3158 }
3159
3160 if (stage_state->push_const_size > 0) {
3161 assert(n >= 0);
3162 pkt.ConstantBody.ReadLength[n] = stage_state->push_const_size;
3163 pkt.ConstantBody.Buffer[n] =
3164 ro_bo(stage_state->push_const_bo,
3165 stage_state->push_const_offset);
3166 }
3167 #else
3168 pkt.ConstantBody.ReadLength[0] = stage_state->push_const_size;
3169 pkt.ConstantBody.Buffer[0].offset =
3170 stage_state->push_const_offset | mocs;
3171 #endif
3172 }
3173 }
3174
3175 stage_state->push_constants_dirty = false;
3176 brw->ctx.NewDriverState |= GEN_GEN >= 9 ? BRW_NEW_SURFACES : 0;
3177 }
3178 }
3179
3180 const struct brw_tracked_state genX(push_constant_packets) = {
3181 .dirty = {
3182 .mesa = 0,
3183 .brw = BRW_NEW_DRAW_CALL,
3184 },
3185 .emit = genX(upload_push_constant_packets),
3186 };
3187 #endif
3188
3189 #if GEN_GEN >= 6
3190 static void
3191 genX(upload_vs_push_constants)(struct brw_context *brw)
3192 {
3193 struct brw_stage_state *stage_state = &brw->vs.base;
3194
3195 /* BRW_NEW_VERTEX_PROGRAM */
3196 const struct gl_program *vp = brw->programs[MESA_SHADER_VERTEX];
3197 /* BRW_NEW_VS_PROG_DATA */
3198 const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
3199
3200 gen6_upload_push_constants(brw, vp, prog_data, stage_state);
3201 }
3202
3203 static const struct brw_tracked_state genX(vs_push_constants) = {
3204 .dirty = {
3205 .mesa = _NEW_PROGRAM_CONSTANTS |
3206 _NEW_TRANSFORM,
3207 .brw = BRW_NEW_BATCH |
3208 BRW_NEW_BLORP |
3209 BRW_NEW_VERTEX_PROGRAM |
3210 BRW_NEW_VS_PROG_DATA,
3211 },
3212 .emit = genX(upload_vs_push_constants),
3213 };
3214
3215 static void
3216 genX(upload_gs_push_constants)(struct brw_context *brw)
3217 {
3218 struct brw_stage_state *stage_state = &brw->gs.base;
3219
3220 /* BRW_NEW_GEOMETRY_PROGRAM */
3221 const struct gl_program *gp = brw->programs[MESA_SHADER_GEOMETRY];
3222
3223 /* BRW_NEW_GS_PROG_DATA */
3224 struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
3225
3226 gen6_upload_push_constants(brw, gp, prog_data, stage_state);
3227 }
3228
3229 static const struct brw_tracked_state genX(gs_push_constants) = {
3230 .dirty = {
3231 .mesa = _NEW_PROGRAM_CONSTANTS |
3232 _NEW_TRANSFORM,
3233 .brw = BRW_NEW_BATCH |
3234 BRW_NEW_BLORP |
3235 BRW_NEW_GEOMETRY_PROGRAM |
3236 BRW_NEW_GS_PROG_DATA,
3237 },
3238 .emit = genX(upload_gs_push_constants),
3239 };
3240
3241 static void
3242 genX(upload_wm_push_constants)(struct brw_context *brw)
3243 {
3244 struct brw_stage_state *stage_state = &brw->wm.base;
3245 /* BRW_NEW_FRAGMENT_PROGRAM */
3246 const struct gl_program *fp = brw->programs[MESA_SHADER_FRAGMENT];
3247 /* BRW_NEW_FS_PROG_DATA */
3248 const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
3249
3250 gen6_upload_push_constants(brw, fp, prog_data, stage_state);
3251 }
3252
3253 static const struct brw_tracked_state genX(wm_push_constants) = {
3254 .dirty = {
3255 .mesa = _NEW_PROGRAM_CONSTANTS,
3256 .brw = BRW_NEW_BATCH |
3257 BRW_NEW_BLORP |
3258 BRW_NEW_FRAGMENT_PROGRAM |
3259 BRW_NEW_FS_PROG_DATA,
3260 },
3261 .emit = genX(upload_wm_push_constants),
3262 };
3263 #endif
3264
3265 /* ---------------------------------------------------------------------- */
3266
3267 #if GEN_GEN >= 6
3268 static unsigned
3269 genX(determine_sample_mask)(struct brw_context *brw)
3270 {
3271 struct gl_context *ctx = &brw->ctx;
3272 float coverage = 1.0f;
3273 float coverage_invert = false;
3274 unsigned sample_mask = ~0u;
3275
3276 /* BRW_NEW_NUM_SAMPLES */
3277 unsigned num_samples = brw->num_samples;
3278
3279 if (_mesa_is_multisample_enabled(ctx)) {
3280 if (ctx->Multisample.SampleCoverage) {
3281 coverage = ctx->Multisample.SampleCoverageValue;
3282 coverage_invert = ctx->Multisample.SampleCoverageInvert;
3283 }
3284 if (ctx->Multisample.SampleMask) {
3285 sample_mask = ctx->Multisample.SampleMaskValue;
3286 }
3287 }
3288
3289 if (num_samples > 1) {
3290 int coverage_int = (int) (num_samples * coverage + 0.5f);
3291 uint32_t coverage_bits = (1 << coverage_int) - 1;
3292 if (coverage_invert)
3293 coverage_bits ^= (1 << num_samples) - 1;
3294 return coverage_bits & sample_mask;
3295 } else {
3296 return 1;
3297 }
3298 }
3299
3300 static void
3301 genX(emit_3dstate_multisample2)(struct brw_context *brw,
3302 unsigned num_samples)
3303 {
3304 unsigned log2_samples = ffs(num_samples) - 1;
3305
3306 brw_batch_emit(brw, GENX(3DSTATE_MULTISAMPLE), multi) {
3307 multi.PixelLocation = CENTER;
3308 multi.NumberofMultisamples = log2_samples;
3309 #if GEN_GEN == 6
3310 GEN_SAMPLE_POS_4X(multi.Sample);
3311 #elif GEN_GEN == 7
3312 switch (num_samples) {
3313 case 1:
3314 GEN_SAMPLE_POS_1X(multi.Sample);
3315 break;
3316 case 2:
3317 GEN_SAMPLE_POS_2X(multi.Sample);
3318 break;
3319 case 4:
3320 GEN_SAMPLE_POS_4X(multi.Sample);
3321 break;
3322 case 8:
3323 GEN_SAMPLE_POS_8X(multi.Sample);
3324 break;
3325 default:
3326 break;
3327 }
3328 #endif
3329 }
3330 }
3331
3332 static void
3333 genX(upload_multisample_state)(struct brw_context *brw)
3334 {
3335 assert(brw->num_samples > 0 && brw->num_samples <= 16);
3336
3337 genX(emit_3dstate_multisample2)(brw, brw->num_samples);
3338
3339 brw_batch_emit(brw, GENX(3DSTATE_SAMPLE_MASK), sm) {
3340 sm.SampleMask = genX(determine_sample_mask)(brw);
3341 }
3342 }
3343
3344 static const struct brw_tracked_state genX(multisample_state) = {
3345 .dirty = {
3346 .mesa = _NEW_MULTISAMPLE |
3347 (GEN_GEN == 10 ? _NEW_BUFFERS : 0),
3348 .brw = BRW_NEW_BLORP |
3349 BRW_NEW_CONTEXT |
3350 BRW_NEW_NUM_SAMPLES,
3351 },
3352 .emit = genX(upload_multisample_state)
3353 };
3354 #endif
3355
3356 /* ---------------------------------------------------------------------- */
3357
3358 static void
3359 genX(upload_color_calc_state)(struct brw_context *brw)
3360 {
3361 struct gl_context *ctx = &brw->ctx;
3362
3363 brw_state_emit(brw, GENX(COLOR_CALC_STATE), 64, &brw->cc.state_offset, cc) {
3364 #if GEN_GEN <= 5
3365 cc.IndependentAlphaBlendEnable =
3366 set_blend_entry_bits(brw, &cc, 0, false);
3367 set_depth_stencil_bits(brw, &cc);
3368
3369 if (ctx->Color.AlphaEnabled &&
3370 ctx->DrawBuffer->_NumColorDrawBuffers <= 1) {
3371 cc.AlphaTestEnable = true;
3372 cc.AlphaTestFunction =
3373 intel_translate_compare_func(ctx->Color.AlphaFunc);
3374 }
3375
3376 cc.ColorDitherEnable = ctx->Color.DitherFlag;
3377
3378 cc.StatisticsEnable = brw->stats_wm;
3379
3380 cc.CCViewportStatePointer =
3381 ro_bo(brw->batch.state.bo, brw->cc.vp_offset);
3382 #else
3383 /* _NEW_COLOR */
3384 cc.BlendConstantColorRed = ctx->Color.BlendColorUnclamped[0];
3385 cc.BlendConstantColorGreen = ctx->Color.BlendColorUnclamped[1];
3386 cc.BlendConstantColorBlue = ctx->Color.BlendColorUnclamped[2];
3387 cc.BlendConstantColorAlpha = ctx->Color.BlendColorUnclamped[3];
3388
3389 #if GEN_GEN < 9
3390 /* _NEW_STENCIL */
3391 cc.StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0);
3392 cc.BackfaceStencilReferenceValue =
3393 _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace);
3394 #endif
3395
3396 #endif
3397
3398 /* _NEW_COLOR */
3399 UNCLAMPED_FLOAT_TO_UBYTE(cc.AlphaReferenceValueAsUNORM8,
3400 ctx->Color.AlphaRef);
3401 }
3402
3403 #if GEN_GEN >= 6
3404 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
3405 ptr.ColorCalcStatePointer = brw->cc.state_offset;
3406 #if GEN_GEN != 7
3407 ptr.ColorCalcStatePointerValid = true;
3408 #endif
3409 }
3410 #else
3411 brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
3412 #endif
3413 }
3414
3415 UNUSED static const struct brw_tracked_state genX(color_calc_state) = {
3416 .dirty = {
3417 .mesa = _NEW_COLOR |
3418 _NEW_STENCIL |
3419 (GEN_GEN <= 5 ? _NEW_BUFFERS |
3420 _NEW_DEPTH
3421 : 0),
3422 .brw = BRW_NEW_BATCH |
3423 BRW_NEW_BLORP |
3424 (GEN_GEN <= 5 ? BRW_NEW_CC_VP |
3425 BRW_NEW_STATS_WM
3426 : BRW_NEW_CC_STATE |
3427 BRW_NEW_STATE_BASE_ADDRESS),
3428 },
3429 .emit = genX(upload_color_calc_state),
3430 };
3431
3432
3433 /* ---------------------------------------------------------------------- */
3434
3435 #if GEN_IS_HASWELL
3436 static void
3437 genX(upload_color_calc_and_blend_state)(struct brw_context *brw)
3438 {
3439 genX(upload_blend_state)(brw);
3440 genX(upload_color_calc_state)(brw);
3441 }
3442
3443 /* On Haswell when BLEND_STATE is emitted CC_STATE should also be re-emitted,
3444 * this workarounds the flickering shadows in several games.
3445 */
3446 static const struct brw_tracked_state genX(cc_and_blend_state) = {
3447 .dirty = {
3448 .mesa = _NEW_BUFFERS |
3449 _NEW_COLOR |
3450 _NEW_STENCIL |
3451 _NEW_MULTISAMPLE,
3452 .brw = BRW_NEW_BATCH |
3453 BRW_NEW_BLORP |
3454 BRW_NEW_CC_STATE |
3455 BRW_NEW_FS_PROG_DATA |
3456 BRW_NEW_STATE_BASE_ADDRESS,
3457 },
3458 .emit = genX(upload_color_calc_and_blend_state),
3459 };
3460 #endif
3461
3462 /* ---------------------------------------------------------------------- */
3463
3464 #if GEN_GEN >= 7
3465 static void
3466 genX(upload_sbe)(struct brw_context *brw)
3467 {
3468 struct gl_context *ctx = &brw->ctx;
3469 /* BRW_NEW_FRAGMENT_PROGRAM */
3470 UNUSED const struct gl_program *fp = brw->programs[MESA_SHADER_FRAGMENT];
3471 /* BRW_NEW_FS_PROG_DATA */
3472 const struct brw_wm_prog_data *wm_prog_data =
3473 brw_wm_prog_data(brw->wm.base.prog_data);
3474 #if GEN_GEN >= 8
3475 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) attr_overrides[16] = { { 0 } };
3476 #else
3477 #define attr_overrides sbe.Attribute
3478 #endif
3479 uint32_t urb_entry_read_length;
3480 uint32_t urb_entry_read_offset;
3481 uint32_t point_sprite_enables;
3482
3483 brw_batch_emit(brw, GENX(3DSTATE_SBE), sbe) {
3484 sbe.AttributeSwizzleEnable = true;
3485 sbe.NumberofSFOutputAttributes = wm_prog_data->num_varying_inputs;
3486
3487 /* _NEW_BUFFERS */
3488 bool flip_y = ctx->DrawBuffer->FlipY;
3489
3490 /* _NEW_POINT
3491 *
3492 * Window coordinates in an FBO are inverted, which means point
3493 * sprite origin must be inverted.
3494 */
3495 if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) == flip_y)
3496 sbe.PointSpriteTextureCoordinateOrigin = LOWERLEFT;
3497 else
3498 sbe.PointSpriteTextureCoordinateOrigin = UPPERLEFT;
3499
3500 /* _NEW_POINT | _NEW_LIGHT | _NEW_PROGRAM,
3501 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM |
3502 * BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA |
3503 * BRW_NEW_VUE_MAP_GEOM_OUT
3504 */
3505 genX(calculate_attr_overrides)(brw,
3506 attr_overrides,
3507 &point_sprite_enables,
3508 &urb_entry_read_length,
3509 &urb_entry_read_offset);
3510
3511 /* Typically, the URB entry read length and offset should be programmed
3512 * in 3DSTATE_VS and 3DSTATE_GS; SBE inherits it from the last active
3513 * stage which produces geometry. However, we don't know the proper
3514 * value until we call calculate_attr_overrides().
3515 *
3516 * To fit with our existing code, we override the inherited values and
3517 * specify it here directly, as we did on previous generations.
3518 */
3519 sbe.VertexURBEntryReadLength = urb_entry_read_length;
3520 sbe.VertexURBEntryReadOffset = urb_entry_read_offset;
3521 sbe.PointSpriteTextureCoordinateEnable = point_sprite_enables;
3522 sbe.ConstantInterpolationEnable = wm_prog_data->flat_inputs;
3523
3524 #if GEN_GEN >= 8
3525 sbe.ForceVertexURBEntryReadLength = true;
3526 sbe.ForceVertexURBEntryReadOffset = true;
3527 #endif
3528
3529 #if GEN_GEN >= 9
3530 /* prepare the active component dwords */
3531 for (int i = 0; i < 32; i++)
3532 sbe.AttributeActiveComponentFormat[i] = ACTIVE_COMPONENT_XYZW;
3533 #endif
3534 }
3535
3536 #if GEN_GEN >= 8
3537 brw_batch_emit(brw, GENX(3DSTATE_SBE_SWIZ), sbes) {
3538 for (int i = 0; i < 16; i++)
3539 sbes.Attribute[i] = attr_overrides[i];
3540 }
3541 #endif
3542
3543 #undef attr_overrides
3544 }
3545
3546 static const struct brw_tracked_state genX(sbe_state) = {
3547 .dirty = {
3548 .mesa = _NEW_BUFFERS |
3549 _NEW_LIGHT |
3550 _NEW_POINT |
3551 _NEW_POLYGON |
3552 _NEW_PROGRAM,
3553 .brw = BRW_NEW_BLORP |
3554 BRW_NEW_CONTEXT |
3555 BRW_NEW_FRAGMENT_PROGRAM |
3556 BRW_NEW_FS_PROG_DATA |
3557 BRW_NEW_GS_PROG_DATA |
3558 BRW_NEW_TES_PROG_DATA |
3559 BRW_NEW_VUE_MAP_GEOM_OUT |
3560 (GEN_GEN == 7 ? BRW_NEW_PRIMITIVE
3561 : 0),
3562 },
3563 .emit = genX(upload_sbe),
3564 };
3565 #endif
3566
3567 /* ---------------------------------------------------------------------- */
3568
3569 #if GEN_GEN >= 7
3570 /**
3571 * Outputs the 3DSTATE_SO_DECL_LIST command.
3572 *
3573 * The data output is a series of 64-bit entries containing a SO_DECL per
3574 * stream. We only have one stream of rendering coming out of the GS unit, so
3575 * we only emit stream 0 (low 16 bits) SO_DECLs.
3576 */
3577 static void
3578 genX(upload_3dstate_so_decl_list)(struct brw_context *brw,
3579 const struct brw_vue_map *vue_map)
3580 {
3581 struct gl_context *ctx = &brw->ctx;
3582 /* BRW_NEW_TRANSFORM_FEEDBACK */
3583 struct gl_transform_feedback_object *xfb_obj =
3584 ctx->TransformFeedback.CurrentObject;
3585 const struct gl_transform_feedback_info *linked_xfb_info =
3586 xfb_obj->program->sh.LinkedTransformFeedback;
3587 struct GENX(SO_DECL) so_decl[MAX_VERTEX_STREAMS][128];
3588 int buffer_mask[MAX_VERTEX_STREAMS] = {0, 0, 0, 0};
3589 int next_offset[MAX_VERTEX_STREAMS] = {0, 0, 0, 0};
3590 int decls[MAX_VERTEX_STREAMS] = {0, 0, 0, 0};
3591 int max_decls = 0;
3592 STATIC_ASSERT(ARRAY_SIZE(so_decl[0]) >= MAX_PROGRAM_OUTPUTS);
3593
3594 memset(so_decl, 0, sizeof(so_decl));
3595
3596 /* Construct the list of SO_DECLs to be emitted. The formatting of the
3597 * command feels strange -- each dword pair contains a SO_DECL per stream.
3598 */
3599 for (unsigned i = 0; i < linked_xfb_info->NumOutputs; i++) {
3600 const struct gl_transform_feedback_output *output =
3601 &linked_xfb_info->Outputs[i];
3602 const int buffer = output->OutputBuffer;
3603 const int varying = output->OutputRegister;
3604 const unsigned stream_id = output->StreamId;
3605 assert(stream_id < MAX_VERTEX_STREAMS);
3606
3607 buffer_mask[stream_id] |= 1 << buffer;
3608
3609 assert(vue_map->varying_to_slot[varying] >= 0);
3610
3611 /* Mesa doesn't store entries for gl_SkipComponents in the Outputs[]
3612 * array. Instead, it simply increments DstOffset for the following
3613 * input by the number of components that should be skipped.
3614 *
3615 * Our hardware is unusual in that it requires us to program SO_DECLs
3616 * for fake "hole" components, rather than simply taking the offset
3617 * for each real varying. Each hole can have size 1, 2, 3, or 4; we
3618 * program as many size = 4 holes as we can, then a final hole to
3619 * accommodate the final 1, 2, or 3 remaining.
3620 */
3621 int skip_components = output->DstOffset - next_offset[buffer];
3622
3623 while (skip_components > 0) {
3624 so_decl[stream_id][decls[stream_id]++] = (struct GENX(SO_DECL)) {
3625 .HoleFlag = 1,
3626 .OutputBufferSlot = output->OutputBuffer,
3627 .ComponentMask = (1 << MIN2(skip_components, 4)) - 1,
3628 };
3629 skip_components -= 4;
3630 }
3631
3632 next_offset[buffer] = output->DstOffset + output->NumComponents;
3633
3634 so_decl[stream_id][decls[stream_id]++] = (struct GENX(SO_DECL)) {
3635 .OutputBufferSlot = output->OutputBuffer,
3636 .RegisterIndex = vue_map->varying_to_slot[varying],
3637 .ComponentMask =
3638 ((1 << output->NumComponents) - 1) << output->ComponentOffset,
3639 };
3640
3641 if (decls[stream_id] > max_decls)
3642 max_decls = decls[stream_id];
3643 }
3644
3645 uint32_t *dw;
3646 dw = brw_batch_emitn(brw, GENX(3DSTATE_SO_DECL_LIST), 3 + 2 * max_decls,
3647 .StreamtoBufferSelects0 = buffer_mask[0],
3648 .StreamtoBufferSelects1 = buffer_mask[1],
3649 .StreamtoBufferSelects2 = buffer_mask[2],
3650 .StreamtoBufferSelects3 = buffer_mask[3],
3651 .NumEntries0 = decls[0],
3652 .NumEntries1 = decls[1],
3653 .NumEntries2 = decls[2],
3654 .NumEntries3 = decls[3]);
3655
3656 for (int i = 0; i < max_decls; i++) {
3657 GENX(SO_DECL_ENTRY_pack)(
3658 brw, dw + 2 + i * 2,
3659 &(struct GENX(SO_DECL_ENTRY)) {
3660 .Stream0Decl = so_decl[0][i],
3661 .Stream1Decl = so_decl[1][i],
3662 .Stream2Decl = so_decl[2][i],
3663 .Stream3Decl = so_decl[3][i],
3664 });
3665 }
3666 }
3667
3668 static void
3669 genX(upload_3dstate_so_buffers)(struct brw_context *brw)
3670 {
3671 struct gl_context *ctx = &brw->ctx;
3672 /* BRW_NEW_TRANSFORM_FEEDBACK */
3673 struct gl_transform_feedback_object *xfb_obj =
3674 ctx->TransformFeedback.CurrentObject;
3675 #if GEN_GEN < 8
3676 const struct gl_transform_feedback_info *linked_xfb_info =
3677 xfb_obj->program->sh.LinkedTransformFeedback;
3678 #else
3679 struct brw_transform_feedback_object *brw_obj =
3680 (struct brw_transform_feedback_object *) xfb_obj;
3681 uint32_t mocs_wb = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
3682 #endif
3683
3684 /* Set up the up to 4 output buffers. These are the ranges defined in the
3685 * gl_transform_feedback_object.
3686 */
3687 for (int i = 0; i < 4; i++) {
3688 struct intel_buffer_object *bufferobj =
3689 intel_buffer_object(xfb_obj->Buffers[i]);
3690 uint32_t start = xfb_obj->Offset[i];
3691 uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
3692 uint32_t const size = end - start;
3693
3694 if (!bufferobj || !size) {
3695 brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
3696 sob.SOBufferIndex = i;
3697 }
3698 continue;
3699 }
3700
3701 assert(start % 4 == 0);
3702 struct brw_bo *bo =
3703 intel_bufferobj_buffer(brw, bufferobj, start, size, true);
3704 assert(end <= bo->size);
3705
3706 brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
3707 sob.SOBufferIndex = i;
3708
3709 sob.SurfaceBaseAddress = rw_bo(bo, start);
3710 #if GEN_GEN < 8
3711 sob.SurfacePitch = linked_xfb_info->Buffers[i].Stride * 4;
3712 sob.SurfaceEndAddress = rw_bo(bo, end);
3713 #else
3714 sob.SOBufferEnable = true;
3715 sob.StreamOffsetWriteEnable = true;
3716 sob.StreamOutputBufferOffsetAddressEnable = true;
3717 sob.MOCS = mocs_wb;
3718
3719 sob.SurfaceSize = MAX2(xfb_obj->Size[i] / 4, 1) - 1;
3720 sob.StreamOutputBufferOffsetAddress =
3721 rw_bo(brw_obj->offset_bo, i * sizeof(uint32_t));
3722
3723 if (brw_obj->zero_offsets) {
3724 /* Zero out the offset and write that to offset_bo */
3725 sob.StreamOffset = 0;
3726 } else {
3727 /* Use offset_bo as the "Stream Offset." */
3728 sob.StreamOffset = 0xFFFFFFFF;
3729 }
3730 #endif
3731 }
3732 }
3733
3734 #if GEN_GEN >= 8
3735 brw_obj->zero_offsets = false;
3736 #endif
3737 }
3738
3739 static bool
3740 query_active(struct gl_query_object *q)
3741 {
3742 return q && q->Active;
3743 }
3744
3745 static void
3746 genX(upload_3dstate_streamout)(struct brw_context *brw, bool active,
3747 const struct brw_vue_map *vue_map)
3748 {
3749 struct gl_context *ctx = &brw->ctx;
3750 /* BRW_NEW_TRANSFORM_FEEDBACK */
3751 struct gl_transform_feedback_object *xfb_obj =
3752 ctx->TransformFeedback.CurrentObject;
3753
3754 brw_batch_emit(brw, GENX(3DSTATE_STREAMOUT), sos) {
3755 if (active) {
3756 int urb_entry_read_offset = 0;
3757 int urb_entry_read_length = (vue_map->num_slots + 1) / 2 -
3758 urb_entry_read_offset;
3759
3760 sos.SOFunctionEnable = true;
3761 sos.SOStatisticsEnable = true;
3762
3763 /* BRW_NEW_RASTERIZER_DISCARD */
3764 if (ctx->RasterDiscard) {
3765 if (!query_active(ctx->Query.PrimitivesGenerated[0])) {
3766 sos.RenderingDisable = true;
3767 } else {
3768 perf_debug("Rasterizer discard with a GL_PRIMITIVES_GENERATED "
3769 "query active relies on the clipper.\n");
3770 }
3771 }
3772
3773 /* _NEW_LIGHT */
3774 if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION)
3775 sos.ReorderMode = TRAILING;
3776
3777 #if GEN_GEN < 8
3778 sos.SOBufferEnable0 = xfb_obj->Buffers[0] != NULL;
3779 sos.SOBufferEnable1 = xfb_obj->Buffers[1] != NULL;
3780 sos.SOBufferEnable2 = xfb_obj->Buffers[2] != NULL;
3781 sos.SOBufferEnable3 = xfb_obj->Buffers[3] != NULL;
3782 #else
3783 const struct gl_transform_feedback_info *linked_xfb_info =
3784 xfb_obj->program->sh.LinkedTransformFeedback;
3785 /* Set buffer pitches; 0 means unbound. */
3786 if (xfb_obj->Buffers[0])
3787 sos.Buffer0SurfacePitch = linked_xfb_info->Buffers[0].Stride * 4;
3788 if (xfb_obj->Buffers[1])
3789 sos.Buffer1SurfacePitch = linked_xfb_info->Buffers[1].Stride * 4;
3790 if (xfb_obj->Buffers[2])
3791 sos.Buffer2SurfacePitch = linked_xfb_info->Buffers[2].Stride * 4;
3792 if (xfb_obj->Buffers[3])
3793 sos.Buffer3SurfacePitch = linked_xfb_info->Buffers[3].Stride * 4;
3794 #endif
3795
3796 /* We always read the whole vertex. This could be reduced at some
3797 * point by reading less and offsetting the register index in the
3798 * SO_DECLs.
3799 */
3800 sos.Stream0VertexReadOffset = urb_entry_read_offset;
3801 sos.Stream0VertexReadLength = urb_entry_read_length - 1;
3802 sos.Stream1VertexReadOffset = urb_entry_read_offset;
3803 sos.Stream1VertexReadLength = urb_entry_read_length - 1;
3804 sos.Stream2VertexReadOffset = urb_entry_read_offset;
3805 sos.Stream2VertexReadLength = urb_entry_read_length - 1;
3806 sos.Stream3VertexReadOffset = urb_entry_read_offset;
3807 sos.Stream3VertexReadLength = urb_entry_read_length - 1;
3808 }
3809 }
3810 }
3811
3812 static void
3813 genX(upload_sol)(struct brw_context *brw)
3814 {
3815 struct gl_context *ctx = &brw->ctx;
3816 /* BRW_NEW_TRANSFORM_FEEDBACK */
3817 bool active = _mesa_is_xfb_active_and_unpaused(ctx);
3818
3819 if (active) {
3820 genX(upload_3dstate_so_buffers)(brw);
3821
3822 /* BRW_NEW_VUE_MAP_GEOM_OUT */
3823 genX(upload_3dstate_so_decl_list)(brw, &brw->vue_map_geom_out);
3824 }
3825
3826 /* Finally, set up the SOL stage. This command must always follow updates to
3827 * the nonpipelined SOL state (3DSTATE_SO_BUFFER, 3DSTATE_SO_DECL_LIST) or
3828 * MMIO register updates (current performed by the kernel at each batch
3829 * emit).
3830 */
3831 genX(upload_3dstate_streamout)(brw, active, &brw->vue_map_geom_out);
3832 }
3833
3834 static const struct brw_tracked_state genX(sol_state) = {
3835 .dirty = {
3836 .mesa = _NEW_LIGHT,
3837 .brw = BRW_NEW_BATCH |
3838 BRW_NEW_BLORP |
3839 BRW_NEW_RASTERIZER_DISCARD |
3840 BRW_NEW_VUE_MAP_GEOM_OUT |
3841 BRW_NEW_TRANSFORM_FEEDBACK,
3842 },
3843 .emit = genX(upload_sol),
3844 };
3845 #endif
3846
3847 /* ---------------------------------------------------------------------- */
3848
3849 #if GEN_GEN >= 7
3850 static void
3851 genX(upload_ps)(struct brw_context *brw)
3852 {
3853 UNUSED const struct gl_context *ctx = &brw->ctx;
3854 UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo;
3855
3856 /* BRW_NEW_FS_PROG_DATA */
3857 const struct brw_wm_prog_data *prog_data =
3858 brw_wm_prog_data(brw->wm.base.prog_data);
3859 const struct brw_stage_state *stage_state = &brw->wm.base;
3860
3861 #if GEN_GEN < 8
3862 #endif
3863
3864 brw_batch_emit(brw, GENX(3DSTATE_PS), ps) {
3865 /* Initialize the execution mask with VMask. Otherwise, derivatives are
3866 * incorrect for subspans where some of the pixels are unlit. We believe
3867 * the bit just didn't take effect in previous generations.
3868 */
3869 ps.VectorMaskEnable = GEN_GEN >= 8;
3870
3871 /* WA_1606682166:
3872 * "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
3873 * Disable the Sampler state prefetch functionality in the SARB by
3874 * programming 0xB000[30] to '1'."
3875 */
3876 ps.SamplerCount = GEN_GEN == 11 ?
3877 0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
3878
3879 /* BRW_NEW_FS_PROG_DATA */
3880 ps.BindingTableEntryCount = prog_data->base.binding_table.size_bytes / 4;
3881
3882 if (prog_data->base.use_alt_mode)
3883 ps.FloatingPointMode = Alternate;
3884
3885 /* Haswell requires the sample mask to be set in this packet as well as
3886 * in 3DSTATE_SAMPLE_MASK; the values should match.
3887 */
3888
3889 /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
3890 #if GEN_IS_HASWELL
3891 ps.SampleMask = genX(determine_sample_mask(brw));
3892 #endif
3893
3894 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
3895 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
3896 * k, it implies 2(k+1) threads. It implicitly scales for different GT
3897 * levels (which have some # of PSDs).
3898 *
3899 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
3900 */
3901 #if GEN_GEN >= 9
3902 ps.MaximumNumberofThreadsPerPSD = 64 - 1;
3903 #elif GEN_GEN >= 8
3904 ps.MaximumNumberofThreadsPerPSD = 64 - 2;
3905 #else
3906 ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
3907 #endif
3908
3909 if (prog_data->base.nr_params > 0 ||
3910 prog_data->base.ubo_ranges[0].length > 0)
3911 ps.PushConstantEnable = true;
3912
3913 #if GEN_GEN < 8
3914 /* From the IVB PRM, volume 2 part 1, page 287:
3915 * "This bit is inserted in the PS payload header and made available to
3916 * the DataPort (either via the message header or via header bypass) to
3917 * indicate that oMask data (one or two phases) is included in Render
3918 * Target Write messages. If present, the oMask data is used to mask off
3919 * samples."
3920 */
3921 ps.oMaskPresenttoRenderTarget = prog_data->uses_omask;
3922
3923 /* The hardware wedges if you have this bit set but don't turn on any
3924 * dual source blend factors.
3925 *
3926 * BRW_NEW_FS_PROG_DATA | _NEW_COLOR
3927 */
3928 ps.DualSourceBlendEnable = prog_data->dual_src_blend &&
3929 (ctx->Color.BlendEnabled & 1) &&
3930 ctx->Color.Blend[0]._UsesDualSrc;
3931
3932 /* BRW_NEW_FS_PROG_DATA */
3933 ps.AttributeEnable = (prog_data->num_varying_inputs != 0);
3934 #endif
3935
3936 /* From the documentation for this packet:
3937 * "If the PS kernel does not need the Position XY Offsets to
3938 * compute a Position Value, then this field should be programmed
3939 * to POSOFFSET_NONE."
3940 *
3941 * "SW Recommendation: If the PS kernel needs the Position Offsets
3942 * to compute a Position XY value, this field should match Position
3943 * ZW Interpolation Mode to ensure a consistent position.xyzw
3944 * computation."
3945 *
3946 * We only require XY sample offsets. So, this recommendation doesn't
3947 * look useful at the moment. We might need this in future.
3948 */
3949 if (prog_data->uses_pos_offset)
3950 ps.PositionXYOffsetSelect = POSOFFSET_SAMPLE;
3951 else
3952 ps.PositionXYOffsetSelect = POSOFFSET_NONE;
3953
3954 ps._8PixelDispatchEnable = prog_data->dispatch_8;
3955 ps._16PixelDispatchEnable = prog_data->dispatch_16;
3956 ps._32PixelDispatchEnable = prog_data->dispatch_32;
3957
3958 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
3959 *
3960 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
3961 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
3962 *
3963 * Since 16x MSAA is first introduced on SKL, we don't need to apply
3964 * the workaround on any older hardware.
3965 *
3966 * BRW_NEW_NUM_SAMPLES
3967 */
3968 if (GEN_GEN >= 9 && !prog_data->persample_dispatch &&
3969 brw->num_samples == 16) {
3970 assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable);
3971 ps._32PixelDispatchEnable = false;
3972 }
3973
3974 ps.DispatchGRFStartRegisterForConstantSetupData0 =
3975 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
3976 ps.DispatchGRFStartRegisterForConstantSetupData1 =
3977 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
3978 ps.DispatchGRFStartRegisterForConstantSetupData2 =
3979 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
3980
3981 ps.KernelStartPointer0 = stage_state->prog_offset +
3982 brw_wm_prog_data_prog_offset(prog_data, ps, 0);
3983 ps.KernelStartPointer1 = stage_state->prog_offset +
3984 brw_wm_prog_data_prog_offset(prog_data, ps, 1);
3985 ps.KernelStartPointer2 = stage_state->prog_offset +
3986 brw_wm_prog_data_prog_offset(prog_data, ps, 2);
3987
3988 if (prog_data->base.total_scratch) {
3989 ps.ScratchSpaceBasePointer =
3990 rw_32_bo(stage_state->scratch_bo,
3991 ffs(stage_state->per_thread_scratch) - 11);
3992 }
3993 }
3994 }
3995
3996 static const struct brw_tracked_state genX(ps_state) = {
3997 .dirty = {
3998 .mesa = _NEW_MULTISAMPLE |
3999 (GEN_GEN < 8 ? _NEW_BUFFERS |
4000 _NEW_COLOR
4001 : 0),
4002 .brw = BRW_NEW_BATCH |
4003 BRW_NEW_BLORP |
4004 BRW_NEW_FS_PROG_DATA |
4005 (GEN_GEN >= 9 ? BRW_NEW_NUM_SAMPLES : 0),
4006 },
4007 .emit = genX(upload_ps),
4008 };
4009 #endif
4010
4011 /* ---------------------------------------------------------------------- */
4012
4013 #if GEN_GEN >= 7
4014 static void
4015 genX(upload_hs_state)(struct brw_context *brw)
4016 {
4017 const struct gen_device_info *devinfo = &brw->screen->devinfo;
4018 struct brw_stage_state *stage_state = &brw->tcs.base;
4019 struct brw_stage_prog_data *stage_prog_data = stage_state->prog_data;
4020 const struct brw_vue_prog_data *vue_prog_data =
4021 brw_vue_prog_data(stage_prog_data);
4022
4023 /* BRW_NEW_TES_PROG_DATA */
4024 struct brw_tcs_prog_data *tcs_prog_data =
4025 brw_tcs_prog_data(stage_prog_data);
4026
4027 if (!tcs_prog_data) {
4028 brw_batch_emit(brw, GENX(3DSTATE_HS), hs);
4029 } else {
4030 brw_batch_emit(brw, GENX(3DSTATE_HS), hs) {
4031 INIT_THREAD_DISPATCH_FIELDS(hs, Vertex);
4032
4033 hs.InstanceCount = tcs_prog_data->instances - 1;
4034 hs.IncludeVertexHandles = true;
4035
4036 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
4037
4038 #if GEN_GEN >= 9
4039 hs.DispatchMode = vue_prog_data->dispatch_mode;
4040 hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id;
4041 #endif
4042 }
4043 }
4044 }
4045
4046 static const struct brw_tracked_state genX(hs_state) = {
4047 .dirty = {
4048 .mesa = 0,
4049 .brw = BRW_NEW_BATCH |
4050 BRW_NEW_BLORP |
4051 BRW_NEW_TCS_PROG_DATA |
4052 BRW_NEW_TESS_PROGRAMS,
4053 },
4054 .emit = genX(upload_hs_state),
4055 };
4056
4057 static void
4058 genX(upload_ds_state)(struct brw_context *brw)
4059 {
4060 const struct gen_device_info *devinfo = &brw->screen->devinfo;
4061 const struct brw_stage_state *stage_state = &brw->tes.base;
4062 struct brw_stage_prog_data *stage_prog_data = stage_state->prog_data;
4063
4064 /* BRW_NEW_TES_PROG_DATA */
4065 const struct brw_tes_prog_data *tes_prog_data =
4066 brw_tes_prog_data(stage_prog_data);
4067 const struct brw_vue_prog_data *vue_prog_data =
4068 brw_vue_prog_data(stage_prog_data);
4069
4070 if (!tes_prog_data) {
4071 brw_batch_emit(brw, GENX(3DSTATE_DS), ds);
4072 } else {
4073 assert(GEN_GEN < 11 ||
4074 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
4075
4076 brw_batch_emit(brw, GENX(3DSTATE_DS), ds) {
4077 INIT_THREAD_DISPATCH_FIELDS(ds, Patch);
4078
4079 ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
4080 ds.ComputeWCoordinateEnable =
4081 tes_prog_data->domain == BRW_TESS_DOMAIN_TRI;
4082
4083 #if GEN_GEN >= 8
4084 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
4085 ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
4086 ds.UserClipDistanceCullTestEnableBitmask =
4087 vue_prog_data->cull_distance_mask;
4088 #endif
4089 }
4090 }
4091 }
4092
4093 static const struct brw_tracked_state genX(ds_state) = {
4094 .dirty = {
4095 .mesa = 0,
4096 .brw = BRW_NEW_BATCH |
4097 BRW_NEW_BLORP |
4098 BRW_NEW_TESS_PROGRAMS |
4099 BRW_NEW_TES_PROG_DATA,
4100 },
4101 .emit = genX(upload_ds_state),
4102 };
4103
4104 /* ---------------------------------------------------------------------- */
4105
4106 static void
4107 upload_te_state(struct brw_context *brw)
4108 {
4109 /* BRW_NEW_TESS_PROGRAMS */
4110 bool active = brw->programs[MESA_SHADER_TESS_EVAL];
4111
4112 /* BRW_NEW_TES_PROG_DATA */
4113 const struct brw_tes_prog_data *tes_prog_data =
4114 brw_tes_prog_data(brw->tes.base.prog_data);
4115
4116 if (active) {
4117 brw_batch_emit(brw, GENX(3DSTATE_TE), te) {
4118 te.Partitioning = tes_prog_data->partitioning;
4119 te.OutputTopology = tes_prog_data->output_topology;
4120 te.TEDomain = tes_prog_data->domain;
4121 te.TEEnable = true;
4122 te.MaximumTessellationFactorOdd = 63.0;
4123 te.MaximumTessellationFactorNotOdd = 64.0;
4124 }
4125 } else {
4126 brw_batch_emit(brw, GENX(3DSTATE_TE), te);
4127 }
4128 }
4129
4130 static const struct brw_tracked_state genX(te_state) = {
4131 .dirty = {
4132 .mesa = 0,
4133 .brw = BRW_NEW_BLORP |
4134 BRW_NEW_CONTEXT |
4135 BRW_NEW_TES_PROG_DATA |
4136 BRW_NEW_TESS_PROGRAMS,
4137 },
4138 .emit = upload_te_state,
4139 };
4140
4141 /* ---------------------------------------------------------------------- */
4142
4143 static void
4144 genX(upload_tes_push_constants)(struct brw_context *brw)
4145 {
4146 struct brw_stage_state *stage_state = &brw->tes.base;
4147 /* BRW_NEW_TESS_PROGRAMS */
4148 const struct gl_program *tep = brw->programs[MESA_SHADER_TESS_EVAL];
4149
4150 /* BRW_NEW_TES_PROG_DATA */
4151 const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data;
4152 gen6_upload_push_constants(brw, tep, prog_data, stage_state);
4153 }
4154
4155 static const struct brw_tracked_state genX(tes_push_constants) = {
4156 .dirty = {
4157 .mesa = _NEW_PROGRAM_CONSTANTS,
4158 .brw = BRW_NEW_BATCH |
4159 BRW_NEW_BLORP |
4160 BRW_NEW_TESS_PROGRAMS |
4161 BRW_NEW_TES_PROG_DATA,
4162 },
4163 .emit = genX(upload_tes_push_constants),
4164 };
4165
4166 static void
4167 genX(upload_tcs_push_constants)(struct brw_context *brw)
4168 {
4169 struct brw_stage_state *stage_state = &brw->tcs.base;
4170 /* BRW_NEW_TESS_PROGRAMS */
4171 const struct gl_program *tcp = brw->programs[MESA_SHADER_TESS_CTRL];
4172
4173 /* BRW_NEW_TCS_PROG_DATA */
4174 const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data;
4175
4176 gen6_upload_push_constants(brw, tcp, prog_data, stage_state);
4177 }
4178
4179 static const struct brw_tracked_state genX(tcs_push_constants) = {
4180 .dirty = {
4181 .mesa = _NEW_PROGRAM_CONSTANTS,
4182 .brw = BRW_NEW_BATCH |
4183 BRW_NEW_BLORP |
4184 BRW_NEW_DEFAULT_TESS_LEVELS |
4185 BRW_NEW_TESS_PROGRAMS |
4186 BRW_NEW_TCS_PROG_DATA,
4187 },
4188 .emit = genX(upload_tcs_push_constants),
4189 };
4190
4191 #endif
4192
4193 /* ---------------------------------------------------------------------- */
4194
4195 #if GEN_GEN >= 7
4196 static void
4197 genX(upload_cs_push_constants)(struct brw_context *brw)
4198 {
4199 struct brw_stage_state *stage_state = &brw->cs.base;
4200
4201 /* BRW_NEW_COMPUTE_PROGRAM */
4202 const struct gl_program *cp = brw->programs[MESA_SHADER_COMPUTE];
4203
4204 if (cp) {
4205 /* BRW_NEW_CS_PROG_DATA */
4206 struct brw_cs_prog_data *cs_prog_data =
4207 brw_cs_prog_data(brw->cs.base.prog_data);
4208
4209 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
4210 brw_upload_cs_push_constants(brw, cp, cs_prog_data, stage_state);
4211 }
4212 }
4213
4214 const struct brw_tracked_state genX(cs_push_constants) = {
4215 .dirty = {
4216 .mesa = _NEW_PROGRAM_CONSTANTS,
4217 .brw = BRW_NEW_BATCH |
4218 BRW_NEW_BLORP |
4219 BRW_NEW_COMPUTE_PROGRAM |
4220 BRW_NEW_CS_PROG_DATA,
4221 },
4222 .emit = genX(upload_cs_push_constants),
4223 };
4224
4225 /**
4226 * Creates a new CS constant buffer reflecting the current CS program's
4227 * constants, if needed by the CS program.
4228 */
4229 static void
4230 genX(upload_cs_pull_constants)(struct brw_context *brw)
4231 {
4232 struct brw_stage_state *stage_state = &brw->cs.base;
4233
4234 /* BRW_NEW_COMPUTE_PROGRAM */
4235 struct brw_program *cp =
4236 (struct brw_program *) brw->programs[MESA_SHADER_COMPUTE];
4237
4238 /* BRW_NEW_CS_PROG_DATA */
4239 const struct brw_stage_prog_data *prog_data = brw->cs.base.prog_data;
4240
4241 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_COMPUTE);
4242 /* _NEW_PROGRAM_CONSTANTS */
4243 brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &cp->program,
4244 stage_state, prog_data);
4245 }
4246
4247 const struct brw_tracked_state genX(cs_pull_constants) = {
4248 .dirty = {
4249 .mesa = _NEW_PROGRAM_CONSTANTS,
4250 .brw = BRW_NEW_BATCH |
4251 BRW_NEW_BLORP |
4252 BRW_NEW_COMPUTE_PROGRAM |
4253 BRW_NEW_CS_PROG_DATA,
4254 },
4255 .emit = genX(upload_cs_pull_constants),
4256 };
4257
4258 static void
4259 genX(upload_cs_state)(struct brw_context *brw)
4260 {
4261 if (!brw->cs.base.prog_data)
4262 return;
4263
4264 uint32_t offset;
4265 uint32_t *desc = (uint32_t*) brw_state_batch(
4266 brw, GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t), 64,
4267 &offset);
4268
4269 struct brw_stage_state *stage_state = &brw->cs.base;
4270 struct brw_stage_prog_data *prog_data = stage_state->prog_data;
4271 struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(prog_data);
4272 const struct gen_device_info *devinfo = &brw->screen->devinfo;
4273
4274 const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw);
4275
4276 if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
4277 brw_emit_buffer_surface_state(
4278 brw, &stage_state->surf_offset[
4279 prog_data->binding_table.shader_time_start],
4280 brw->shader_time.bo, 0, ISL_FORMAT_RAW,
4281 brw->shader_time.bo->size, 1,
4282 RELOC_WRITE);
4283 }
4284
4285 uint32_t *bind = brw_state_batch(brw, prog_data->binding_table.size_bytes,
4286 32, &stage_state->bind_bo_offset);
4287
4288 /* The MEDIA_VFE_STATE documentation for Gen8+ says:
4289 *
4290 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4291 * the only bits that are changed are scoreboard related: Scoreboard
4292 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4293 * these scoreboard related states, a MEDIA_STATE_FLUSH is sufficient."
4294 *
4295 * Earlier generations say "MI_FLUSH" instead of "stalling PIPE_CONTROL",
4296 * but MI_FLUSH isn't really a thing, so we assume they meant PIPE_CONTROL.
4297 */
4298 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
4299
4300 brw_batch_emit(brw, GENX(MEDIA_VFE_STATE), vfe) {
4301 if (prog_data->total_scratch) {
4302 uint32_t per_thread_scratch_value;
4303
4304 if (GEN_GEN >= 8) {
4305 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
4306 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
4307 */
4308 per_thread_scratch_value = ffs(stage_state->per_thread_scratch) - 11;
4309 } else if (GEN_IS_HASWELL) {
4310 /* Haswell's Per Thread Scratch Space is in the range [0, 10]
4311 * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
4312 */
4313 per_thread_scratch_value = ffs(stage_state->per_thread_scratch) - 12;
4314 } else {
4315 /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
4316 * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
4317 */
4318 per_thread_scratch_value = stage_state->per_thread_scratch / 1024 - 1;
4319 }
4320 vfe.ScratchSpaceBasePointer = rw_32_bo(stage_state->scratch_bo, 0);
4321 vfe.PerThreadScratchSpace = per_thread_scratch_value;
4322 }
4323
4324 /* If brw->screen->subslice_total is greater than one, then
4325 * devinfo->max_cs_threads stores number of threads per sub-slice;
4326 * thus we need to multiply by that number by subslices to get
4327 * the actual maximum number of threads; the -1 is because the HW
4328 * has a bias of 1 (would not make sense to say the maximum number
4329 * of threads is 0).
4330 */
4331 const uint32_t subslices = MAX2(brw->screen->subslice_total, 1);
4332 vfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1;
4333 vfe.NumberofURBEntries = GEN_GEN >= 8 ? 2 : 0;
4334 #if GEN_GEN < 11
4335 vfe.ResetGatewayTimer =
4336 Resettingrelativetimerandlatchingtheglobaltimestamp;
4337 #endif
4338 #if GEN_GEN < 9
4339 vfe.BypassGatewayControl = BypassingOpenGatewayCloseGatewayprotocol;
4340 #endif
4341 #if GEN_GEN == 7
4342 vfe.GPGPUMode = 1;
4343 #endif
4344
4345 /* We are uploading duplicated copies of push constant uniforms for each
4346 * thread. Although the local id data needs to vary per thread, it won't
4347 * change for other uniform data. Unfortunately this duplication is
4348 * required for gen7. As of Haswell, this duplication can be avoided,
4349 * but this older mechanism with duplicated data continues to work.
4350 *
4351 * FINISHME: As of Haswell, we could make use of the
4352 * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length"
4353 * field to only store one copy of uniform data.
4354 *
4355 * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
4356 * which is described in the GPGPU_WALKER command and in the Broadwell
4357 * PRM Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
4358 * Operations => GPGPU Mode => Indirect Payload Storage.
4359 *
4360 * Note: The constant data is built in brw_upload_cs_push_constants
4361 * below.
4362 */
4363 vfe.URBEntryAllocationSize = GEN_GEN >= 8 ? 2 : 0;
4364
4365 const uint32_t vfe_curbe_allocation =
4366 ALIGN(cs_prog_data->push.per_thread.regs * cs_params.threads +
4367 cs_prog_data->push.cross_thread.regs, 2);
4368 vfe.CURBEAllocationSize = vfe_curbe_allocation;
4369 }
4370
4371 const unsigned push_const_size =
4372 brw_cs_push_const_total_size(cs_prog_data, cs_params.threads);
4373 if (push_const_size > 0) {
4374 brw_batch_emit(brw, GENX(MEDIA_CURBE_LOAD), curbe) {
4375 curbe.CURBETotalDataLength = ALIGN(push_const_size, 64);
4376 curbe.CURBEDataStartAddress = stage_state->push_const_offset;
4377 }
4378 }
4379
4380 /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
4381 memcpy(bind, stage_state->surf_offset,
4382 prog_data->binding_table.size_bytes);
4383 const uint64_t ksp = brw->cs.base.prog_offset +
4384 brw_cs_prog_data_prog_offset(cs_prog_data,
4385 cs_params.simd_size);
4386 const struct GENX(INTERFACE_DESCRIPTOR_DATA) idd = {
4387 .KernelStartPointer = ksp,
4388 .SamplerStatePointer = stage_state->sampler_offset,
4389 /* WA_1606682166 */
4390 .SamplerCount = GEN_GEN == 11 ? 0 :
4391 DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4),
4392 .BindingTablePointer = stage_state->bind_bo_offset,
4393 .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
4394 .NumberofThreadsinGPGPUThreadGroup = cs_params.threads,
4395 .SharedLocalMemorySize = encode_slm_size(GEN_GEN,
4396 prog_data->total_shared),
4397 .BarrierEnable = cs_prog_data->uses_barrier,
4398 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4399 .CrossThreadConstantDataReadLength =
4400 cs_prog_data->push.cross_thread.regs,
4401 #endif
4402 };
4403
4404 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(brw, desc, &idd);
4405
4406 brw_batch_emit(brw, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), load) {
4407 load.InterfaceDescriptorTotalLength =
4408 GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
4409 load.InterfaceDescriptorDataStartAddress = offset;
4410 }
4411 }
4412
4413 static const struct brw_tracked_state genX(cs_state) = {
4414 .dirty = {
4415 .mesa = _NEW_PROGRAM_CONSTANTS,
4416 .brw = BRW_NEW_BATCH |
4417 BRW_NEW_BLORP |
4418 BRW_NEW_CS_PROG_DATA |
4419 BRW_NEW_SAMPLER_STATE_TABLE |
4420 BRW_NEW_SURFACES,
4421 },
4422 .emit = genX(upload_cs_state)
4423 };
4424
4425 #define GPGPU_DISPATCHDIMX 0x2500
4426 #define GPGPU_DISPATCHDIMY 0x2504
4427 #define GPGPU_DISPATCHDIMZ 0x2508
4428
4429 #define MI_PREDICATE_SRC0 0x2400
4430 #define MI_PREDICATE_SRC1 0x2408
4431
4432 static void
4433 prepare_indirect_gpgpu_walker(struct brw_context *brw)
4434 {
4435 GLintptr indirect_offset = brw->compute.num_work_groups_offset;
4436 struct brw_bo *bo = brw->compute.num_work_groups_bo;
4437
4438 emit_lrm(brw, GPGPU_DISPATCHDIMX, ro_bo(bo, indirect_offset + 0));
4439 emit_lrm(brw, GPGPU_DISPATCHDIMY, ro_bo(bo, indirect_offset + 4));
4440 emit_lrm(brw, GPGPU_DISPATCHDIMZ, ro_bo(bo, indirect_offset + 8));
4441
4442 #if GEN_GEN <= 7
4443 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
4444 emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0);
4445 emit_lri(brw, MI_PREDICATE_SRC1 , 0);
4446 emit_lri(brw, MI_PREDICATE_SRC1 + 4, 0);
4447
4448 /* Load compute_dispatch_indirect_x_size into SRC0 */
4449 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 0));
4450
4451 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4452 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4453 mip.LoadOperation = LOAD_LOAD;
4454 mip.CombineOperation = COMBINE_SET;
4455 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4456 }
4457
4458 /* Load compute_dispatch_indirect_y_size into SRC0 */
4459 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 4));
4460
4461 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4462 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4463 mip.LoadOperation = LOAD_LOAD;
4464 mip.CombineOperation = COMBINE_OR;
4465 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4466 }
4467
4468 /* Load compute_dispatch_indirect_z_size into SRC0 */
4469 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 8));
4470
4471 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4472 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4473 mip.LoadOperation = LOAD_LOAD;
4474 mip.CombineOperation = COMBINE_OR;
4475 mip.CompareOperation = COMPARE_SRCS_EQUAL;
4476 }
4477
4478 /* predicate = !predicate; */
4479 #define COMPARE_FALSE 1
4480 brw_batch_emit(brw, GENX(MI_PREDICATE), mip) {
4481 mip.LoadOperation = LOAD_LOADINV;
4482 mip.CombineOperation = COMBINE_OR;
4483 mip.CompareOperation = COMPARE_FALSE;
4484 }
4485 #endif
4486 }
4487
4488 static void
4489 genX(emit_gpgpu_walker)(struct brw_context *brw)
4490 {
4491 const GLuint *num_groups = brw->compute.num_work_groups;
4492
4493 bool indirect = brw->compute.num_work_groups_bo != NULL;
4494 if (indirect)
4495 prepare_indirect_gpgpu_walker(brw);
4496
4497 const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw);
4498
4499 const uint32_t right_mask =
4500 brw_cs_right_mask(cs_params.group_size, cs_params.simd_size);
4501
4502 brw_batch_emit(brw, GENX(GPGPU_WALKER), ggw) {
4503 ggw.IndirectParameterEnable = indirect;
4504 ggw.PredicateEnable = GEN_GEN <= 7 && indirect;
4505 ggw.SIMDSize = cs_params.simd_size / 16;
4506 ggw.ThreadDepthCounterMaximum = 0;
4507 ggw.ThreadHeightCounterMaximum = 0;
4508 ggw.ThreadWidthCounterMaximum = cs_params.threads - 1;
4509 ggw.ThreadGroupIDXDimension = num_groups[0];
4510 ggw.ThreadGroupIDYDimension = num_groups[1];
4511 ggw.ThreadGroupIDZDimension = num_groups[2];
4512 ggw.RightExecutionMask = right_mask;
4513 ggw.BottomExecutionMask = 0xffffffff;
4514 }
4515
4516 brw_batch_emit(brw, GENX(MEDIA_STATE_FLUSH), msf);
4517 }
4518
4519 #endif
4520
4521 /* ---------------------------------------------------------------------- */
4522
4523 #if GEN_GEN >= 8
4524 static void
4525 genX(upload_raster)(struct brw_context *brw)
4526 {
4527 const struct gl_context *ctx = &brw->ctx;
4528
4529 /* _NEW_BUFFERS */
4530 const bool flip_y = ctx->DrawBuffer->FlipY;
4531
4532 /* _NEW_POLYGON */
4533 const struct gl_polygon_attrib *polygon = &ctx->Polygon;
4534
4535 /* _NEW_POINT */
4536 const struct gl_point_attrib *point = &ctx->Point;
4537
4538 brw_batch_emit(brw, GENX(3DSTATE_RASTER), raster) {
4539 if (brw->polygon_front_bit != flip_y)
4540 raster.FrontWinding = CounterClockwise;
4541
4542 if (polygon->CullFlag) {
4543 switch (polygon->CullFaceMode) {
4544 case GL_FRONT:
4545 raster.CullMode = CULLMODE_FRONT;
4546 break;
4547 case GL_BACK:
4548 raster.CullMode = CULLMODE_BACK;
4549 break;
4550 case GL_FRONT_AND_BACK:
4551 raster.CullMode = CULLMODE_BOTH;
4552 break;
4553 default:
4554 unreachable("not reached");
4555 }
4556 } else {
4557 raster.CullMode = CULLMODE_NONE;
4558 }
4559
4560 raster.SmoothPointEnable = point->SmoothFlag;
4561
4562 raster.DXMultisampleRasterizationEnable =
4563 _mesa_is_multisample_enabled(ctx);
4564
4565 raster.GlobalDepthOffsetEnableSolid = polygon->OffsetFill;
4566 raster.GlobalDepthOffsetEnableWireframe = polygon->OffsetLine;
4567 raster.GlobalDepthOffsetEnablePoint = polygon->OffsetPoint;
4568
4569 switch (polygon->FrontMode) {
4570 case GL_FILL:
4571 raster.FrontFaceFillMode = FILL_MODE_SOLID;
4572 break;
4573 case GL_LINE:
4574 raster.FrontFaceFillMode = FILL_MODE_WIREFRAME;
4575 break;
4576 case GL_POINT:
4577 raster.FrontFaceFillMode = FILL_MODE_POINT;
4578 break;
4579 default:
4580 unreachable("not reached");
4581 }
4582
4583 switch (polygon->BackMode) {
4584 case GL_FILL:
4585 raster.BackFaceFillMode = FILL_MODE_SOLID;
4586 break;
4587 case GL_LINE:
4588 raster.BackFaceFillMode = FILL_MODE_WIREFRAME;
4589 break;
4590 case GL_POINT:
4591 raster.BackFaceFillMode = FILL_MODE_POINT;
4592 break;
4593 default:
4594 unreachable("not reached");
4595 }
4596
4597 /* _NEW_LINE */
4598 raster.AntialiasingEnable = ctx->Line.SmoothFlag;
4599
4600 #if GEN_GEN == 10
4601 /* _NEW_BUFFERS
4602 * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1.
4603 */
4604 const bool multisampled_fbo =
4605 _mesa_geometric_samples(ctx->DrawBuffer) > 1;
4606 if (multisampled_fbo)
4607 raster.AntialiasingEnable = false;
4608 #endif
4609
4610 /* _NEW_SCISSOR */
4611 raster.ScissorRectangleEnable = ctx->Scissor.EnableFlags;
4612
4613 /* _NEW_TRANSFORM */
4614 #if GEN_GEN < 9
4615 if (!(ctx->Transform.DepthClampNear &&
4616 ctx->Transform.DepthClampFar))
4617 raster.ViewportZClipTestEnable = true;
4618 #endif
4619
4620 #if GEN_GEN >= 9
4621 if (!ctx->Transform.DepthClampNear)
4622 raster.ViewportZNearClipTestEnable = true;
4623
4624 if (!ctx->Transform.DepthClampFar)
4625 raster.ViewportZFarClipTestEnable = true;
4626 #endif
4627
4628 /* BRW_NEW_CONSERVATIVE_RASTERIZATION */
4629 #if GEN_GEN >= 9
4630 raster.ConservativeRasterizationEnable =
4631 ctx->IntelConservativeRasterization;
4632 #endif
4633
4634 raster.GlobalDepthOffsetClamp = polygon->OffsetClamp;
4635 raster.GlobalDepthOffsetScale = polygon->OffsetFactor;
4636
4637 raster.GlobalDepthOffsetConstant = polygon->OffsetUnits * 2;
4638 }
4639 }
4640
4641 static const struct brw_tracked_state genX(raster_state) = {
4642 .dirty = {
4643 .mesa = _NEW_BUFFERS |
4644 _NEW_LINE |
4645 _NEW_MULTISAMPLE |
4646 _NEW_POINT |
4647 _NEW_POLYGON |
4648 _NEW_SCISSOR |
4649 _NEW_TRANSFORM,
4650 .brw = BRW_NEW_BLORP |
4651 BRW_NEW_CONTEXT |
4652 BRW_NEW_CONSERVATIVE_RASTERIZATION,
4653 },
4654 .emit = genX(upload_raster),
4655 };
4656 #endif
4657
4658 /* ---------------------------------------------------------------------- */
4659
4660 #if GEN_GEN >= 8
4661 static void
4662 genX(upload_ps_extra)(struct brw_context *brw)
4663 {
4664 UNUSED struct gl_context *ctx = &brw->ctx;
4665
4666 const struct brw_wm_prog_data *prog_data =
4667 brw_wm_prog_data(brw->wm.base.prog_data);
4668
4669 brw_batch_emit(brw, GENX(3DSTATE_PS_EXTRA), psx) {
4670 psx.PixelShaderValid = true;
4671 psx.PixelShaderComputedDepthMode = prog_data->computed_depth_mode;
4672 psx.PixelShaderKillsPixel = prog_data->uses_kill;
4673 psx.AttributeEnable = prog_data->num_varying_inputs != 0;
4674 psx.PixelShaderUsesSourceDepth = prog_data->uses_src_depth;
4675 psx.PixelShaderUsesSourceW = prog_data->uses_src_w;
4676 psx.PixelShaderIsPerSample = prog_data->persample_dispatch;
4677
4678 /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */
4679 if (prog_data->uses_sample_mask) {
4680 #if GEN_GEN >= 9
4681 if (prog_data->post_depth_coverage)
4682 psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE;
4683 else if (prog_data->inner_coverage && ctx->IntelConservativeRasterization)
4684 psx.InputCoverageMaskState = ICMS_INNER_CONSERVATIVE;
4685 else
4686 psx.InputCoverageMaskState = ICMS_NORMAL;
4687 #else
4688 psx.PixelShaderUsesInputCoverageMask = true;
4689 #endif
4690 }
4691
4692 psx.oMaskPresenttoRenderTarget = prog_data->uses_omask;
4693 #if GEN_GEN >= 9
4694 psx.PixelShaderPullsBary = prog_data->pulls_bary;
4695 psx.PixelShaderComputesStencil = prog_data->computed_stencil;
4696 #endif
4697
4698 /* The stricter cross-primitive coherency guarantees that the hardware
4699 * gives us with the "Accesses UAV" bit set for at least one shader stage
4700 * and the "UAV coherency required" bit set on the 3DPRIMITIVE command
4701 * are redundant within the current image, atomic counter and SSBO GL
4702 * APIs, which all have very loose ordering and coherency requirements
4703 * and generally rely on the application to insert explicit barriers when
4704 * a shader invocation is expected to see the memory writes performed by
4705 * the invocations of some previous primitive. Regardless of the value
4706 * of "UAV coherency required", the "Accesses UAV" bits will implicitly
4707 * cause an in most cases useless DC flush when the lowermost stage with
4708 * the bit set finishes execution.
4709 *
4710 * It would be nice to disable it, but in some cases we can't because on
4711 * Gen8+ it also has an influence on rasterization via the PS UAV-only
4712 * signal (which could be set independently from the coherency mechanism
4713 * in the 3DSTATE_WM command on Gen7), and because in some cases it will
4714 * determine whether the hardware skips execution of the fragment shader
4715 * or not via the ThreadDispatchEnable signal. However if we know that
4716 * GEN8_PS_BLEND_HAS_WRITEABLE_RT is going to be set and
4717 * GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE is not set it shouldn't make any
4718 * difference so we may just disable it here.
4719 *
4720 * Gen8 hardware tries to compute ThreadDispatchEnable for us but doesn't
4721 * take into account KillPixels when no depth or stencil writes are
4722 * enabled. In order for occlusion queries to work correctly with no
4723 * attachments, we need to force-enable here.
4724 *
4725 * BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS |
4726 * _NEW_COLOR
4727 */
4728 if ((prog_data->has_side_effects || prog_data->uses_kill) &&
4729 !brw_color_buffer_write_enabled(brw))
4730 psx.PixelShaderHasUAV = true;
4731 }
4732 }
4733
4734 const struct brw_tracked_state genX(ps_extra) = {
4735 .dirty = {
4736 .mesa = _NEW_BUFFERS | _NEW_COLOR,
4737 .brw = BRW_NEW_BLORP |
4738 BRW_NEW_CONTEXT |
4739 BRW_NEW_FRAGMENT_PROGRAM |
4740 BRW_NEW_FS_PROG_DATA |
4741 BRW_NEW_CONSERVATIVE_RASTERIZATION,
4742 },
4743 .emit = genX(upload_ps_extra),
4744 };
4745 #endif
4746
4747 /* ---------------------------------------------------------------------- */
4748
4749 #if GEN_GEN >= 8
4750 static void
4751 genX(upload_ps_blend)(struct brw_context *brw)
4752 {
4753 struct gl_context *ctx = &brw->ctx;
4754
4755 /* _NEW_BUFFERS */
4756 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
4757 const bool buffer0_is_integer = ctx->DrawBuffer->_IntegerBuffers & 0x1;
4758
4759 /* _NEW_COLOR */
4760 struct gl_colorbuffer_attrib *color = &ctx->Color;
4761
4762 brw_batch_emit(brw, GENX(3DSTATE_PS_BLEND), pb) {
4763 /* BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR */
4764 pb.HasWriteableRT = brw_color_buffer_write_enabled(brw);
4765
4766 bool alpha_to_one = false;
4767
4768 if (!buffer0_is_integer) {
4769 /* _NEW_MULTISAMPLE */
4770
4771 if (_mesa_is_multisample_enabled(ctx)) {
4772 pb.AlphaToCoverageEnable = ctx->Multisample.SampleAlphaToCoverage;
4773 alpha_to_one = ctx->Multisample.SampleAlphaToOne;
4774 }
4775
4776 pb.AlphaTestEnable = color->AlphaEnabled;
4777 }
4778
4779 /* Used for implementing the following bit of GL_EXT_texture_integer:
4780 * "Per-fragment operations that require floating-point color
4781 * components, including multisample alpha operations, alpha test,
4782 * blending, and dithering, have no effect when the corresponding
4783 * colors are written to an integer color buffer."
4784 *
4785 * The OpenGL specification 3.3 (page 196), section 4.1.3 says:
4786 * "If drawbuffer zero is not NONE and the buffer it references has an
4787 * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE
4788 * operations are skipped."
4789 */
4790 if (rb && !buffer0_is_integer && (color->BlendEnabled & 1)) {
4791 GLenum eqRGB = color->Blend[0].EquationRGB;
4792 GLenum eqA = color->Blend[0].EquationA;
4793 GLenum srcRGB = color->Blend[0].SrcRGB;
4794 GLenum dstRGB = color->Blend[0].DstRGB;
4795 GLenum srcA = color->Blend[0].SrcA;
4796 GLenum dstA = color->Blend[0].DstA;
4797
4798 if (eqRGB == GL_MIN || eqRGB == GL_MAX)
4799 srcRGB = dstRGB = GL_ONE;
4800
4801 if (eqA == GL_MIN || eqA == GL_MAX)
4802 srcA = dstA = GL_ONE;
4803
4804 /* Due to hardware limitations, the destination may have information
4805 * in an alpha channel even when the format specifies no alpha
4806 * channel. In order to avoid getting any incorrect blending due to
4807 * that alpha channel, coerce the blend factors to values that will
4808 * not read the alpha channel, but will instead use the correct
4809 * implicit value for alpha.
4810 */
4811 if (!_mesa_base_format_has_channel(rb->_BaseFormat,
4812 GL_TEXTURE_ALPHA_TYPE)) {
4813 srcRGB = brw_fix_xRGB_alpha(srcRGB);
4814 srcA = brw_fix_xRGB_alpha(srcA);
4815 dstRGB = brw_fix_xRGB_alpha(dstRGB);
4816 dstA = brw_fix_xRGB_alpha(dstA);
4817 }
4818
4819 /* Alpha to One doesn't work with Dual Color Blending. Override
4820 * SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO.
4821 */
4822 if (alpha_to_one && color->Blend[0]._UsesDualSrc) {
4823 srcRGB = fix_dual_blend_alpha_to_one(srcRGB);
4824 srcA = fix_dual_blend_alpha_to_one(srcA);
4825 dstRGB = fix_dual_blend_alpha_to_one(dstRGB);
4826 dstA = fix_dual_blend_alpha_to_one(dstA);
4827 }
4828
4829 /* BRW_NEW_FS_PROG_DATA */
4830 const struct brw_wm_prog_data *wm_prog_data =
4831 brw_wm_prog_data(brw->wm.base.prog_data);
4832
4833 /* The Dual Source Blending documentation says:
4834 *
4835 * "If SRC1 is included in a src/dst blend factor and
4836 * a DualSource RT Write message is not used, results
4837 * are UNDEFINED. (This reflects the same restriction in DX APIs,
4838 * where undefined results are produced if “o1” is not written
4839 * by a PS – there are no default values defined).
4840 * If SRC1 is not included in a src/dst blend factor,
4841 * dual source blending must be disabled."
4842 *
4843 * There is no way to gracefully fix this undefined situation
4844 * so we just disable the blending to prevent possible issues.
4845 */
4846 pb.ColorBufferBlendEnable =
4847 !color->Blend[0]._UsesDualSrc || wm_prog_data->dual_src_blend;
4848 pb.SourceAlphaBlendFactor = brw_translate_blend_factor(srcA);
4849 pb.DestinationAlphaBlendFactor = brw_translate_blend_factor(dstA);
4850 pb.SourceBlendFactor = brw_translate_blend_factor(srcRGB);
4851 pb.DestinationBlendFactor = brw_translate_blend_factor(dstRGB);
4852
4853 pb.IndependentAlphaBlendEnable =
4854 srcA != srcRGB || dstA != dstRGB || eqA != eqRGB;
4855 }
4856 }
4857 }
4858
4859 static const struct brw_tracked_state genX(ps_blend) = {
4860 .dirty = {
4861 .mesa = _NEW_BUFFERS |
4862 _NEW_COLOR |
4863 _NEW_MULTISAMPLE,
4864 .brw = BRW_NEW_BLORP |
4865 BRW_NEW_CONTEXT |
4866 BRW_NEW_FRAGMENT_PROGRAM |
4867 BRW_NEW_FS_PROG_DATA,
4868 },
4869 .emit = genX(upload_ps_blend)
4870 };
4871 #endif
4872
4873 /* ---------------------------------------------------------------------- */
4874
4875 #if GEN_GEN >= 8
4876 static void
4877 genX(emit_vf_topology)(struct brw_context *brw)
4878 {
4879 brw_batch_emit(brw, GENX(3DSTATE_VF_TOPOLOGY), vftopo) {
4880 vftopo.PrimitiveTopologyType = brw->primitive;
4881 }
4882 }
4883
4884 static const struct brw_tracked_state genX(vf_topology) = {
4885 .dirty = {
4886 .mesa = 0,
4887 .brw = BRW_NEW_BLORP |
4888 BRW_NEW_PRIMITIVE,
4889 },
4890 .emit = genX(emit_vf_topology),
4891 };
4892 #endif
4893
4894 /* ---------------------------------------------------------------------- */
4895
4896 #if GEN_GEN >= 7
4897 static void
4898 genX(emit_mi_report_perf_count)(struct brw_context *brw,
4899 struct brw_bo *bo,
4900 uint32_t offset_in_bytes,
4901 uint32_t report_id)
4902 {
4903 brw_batch_emit(brw, GENX(MI_REPORT_PERF_COUNT), mi_rpc) {
4904 mi_rpc.MemoryAddress = ggtt_bo(bo, offset_in_bytes);
4905 mi_rpc.ReportID = report_id;
4906 }
4907 }
4908 #endif
4909
4910 /* ---------------------------------------------------------------------- */
4911
4912 /**
4913 * Emit a 3DSTATE_SAMPLER_STATE_POINTERS_{VS,HS,GS,DS,PS} packet.
4914 */
4915 static void
4916 genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw,
4917 UNUSED struct brw_stage_state *stage_state)
4918 {
4919 #if GEN_GEN >= 7
4920 static const uint16_t packet_headers[] = {
4921 [MESA_SHADER_VERTEX] = 43,
4922 [MESA_SHADER_TESS_CTRL] = 44,
4923 [MESA_SHADER_TESS_EVAL] = 45,
4924 [MESA_SHADER_GEOMETRY] = 46,
4925 [MESA_SHADER_FRAGMENT] = 47,
4926 };
4927
4928 /* Ivybridge requires a workaround flush before VS packets. */
4929 if (GEN_GEN == 7 && !GEN_IS_HASWELL &&
4930 stage_state->stage == MESA_SHADER_VERTEX) {
4931 gen7_emit_vs_workaround_flush(brw);
4932 }
4933
4934 brw_batch_emit(brw, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
4935 ptr._3DCommandSubOpcode = packet_headers[stage_state->stage];
4936 ptr.PointertoVSSamplerState = stage_state->sampler_offset;
4937 }
4938 #endif
4939 }
4940
4941 UNUSED static bool
4942 has_component(mesa_format format, int i)
4943 {
4944 if (_mesa_is_format_color_format(format))
4945 return _mesa_format_has_color_component(format, i);
4946
4947 /* depth and stencil have only one component */
4948 return i == 0;
4949 }
4950
4951 /**
4952 * Upload SAMPLER_BORDER_COLOR_STATE.
4953 */
4954 static void
4955 genX(upload_default_color)(struct brw_context *brw,
4956 const struct gl_sampler_object *sampler,
4957 UNUSED mesa_format format,
4958 GLenum base_format,
4959 bool is_integer_format, bool is_stencil_sampling,
4960 uint32_t *sdc_offset)
4961 {
4962 union gl_color_union color;
4963
4964 switch (base_format) {
4965 case GL_DEPTH_COMPONENT:
4966 /* GL specs that border color for depth textures is taken from the
4967 * R channel, while the hardware uses A. Spam R into all the
4968 * channels for safety.
4969 */
4970 color.ui[0] = sampler->BorderColor.ui[0];
4971 color.ui[1] = sampler->BorderColor.ui[0];
4972 color.ui[2] = sampler->BorderColor.ui[0];
4973 color.ui[3] = sampler->BorderColor.ui[0];
4974 break;
4975 case GL_ALPHA:
4976 color.ui[0] = 0u;
4977 color.ui[1] = 0u;
4978 color.ui[2] = 0u;
4979 color.ui[3] = sampler->BorderColor.ui[3];
4980 break;
4981 case GL_INTENSITY:
4982 color.ui[0] = sampler->BorderColor.ui[0];
4983 color.ui[1] = sampler->BorderColor.ui[0];
4984 color.ui[2] = sampler->BorderColor.ui[0];
4985 color.ui[3] = sampler->BorderColor.ui[0];
4986 break;
4987 case GL_LUMINANCE:
4988 color.ui[0] = sampler->BorderColor.ui[0];
4989 color.ui[1] = sampler->BorderColor.ui[0];
4990 color.ui[2] = sampler->BorderColor.ui[0];
4991 color.ui[3] = float_as_int(1.0);
4992 break;
4993 case GL_LUMINANCE_ALPHA:
4994 color.ui[0] = sampler->BorderColor.ui[0];
4995 color.ui[1] = sampler->BorderColor.ui[0];
4996 color.ui[2] = sampler->BorderColor.ui[0];
4997 color.ui[3] = sampler->BorderColor.ui[3];
4998 break;
4999 default:
5000 color.ui[0] = sampler->BorderColor.ui[0];
5001 color.ui[1] = sampler->BorderColor.ui[1];
5002 color.ui[2] = sampler->BorderColor.ui[2];
5003 color.ui[3] = sampler->BorderColor.ui[3];
5004 break;
5005 }
5006
5007 /* In some cases we use an RGBA surface format for GL RGB textures,
5008 * where we've initialized the A channel to 1.0. We also have to set
5009 * the border color alpha to 1.0 in that case.
5010 */
5011 if (base_format == GL_RGB)
5012 color.ui[3] = float_as_int(1.0);
5013
5014 int alignment = 32;
5015 if (GEN_GEN >= 8) {
5016 alignment = 64;
5017 } else if (GEN_IS_HASWELL && (is_integer_format || is_stencil_sampling)) {
5018 alignment = 512;
5019 }
5020
5021 uint32_t *sdc = brw_state_batch(
5022 brw, GENX(SAMPLER_BORDER_COLOR_STATE_length) * sizeof(uint32_t),
5023 alignment, sdc_offset);
5024
5025 struct GENX(SAMPLER_BORDER_COLOR_STATE) state = { 0 };
5026
5027 #define ASSIGN(dst, src) \
5028 do { \
5029 dst = src; \
5030 } while (0)
5031
5032 #define ASSIGNu16(dst, src) \
5033 do { \
5034 dst = (uint16_t)src; \
5035 } while (0)
5036
5037 #define ASSIGNu8(dst, src) \
5038 do { \
5039 dst = (uint8_t)src; \
5040 } while (0)
5041
5042 #define BORDER_COLOR_ATTR(macro, _color_type, src) \
5043 macro(state.BorderColor ## _color_type ## Red, src[0]); \
5044 macro(state.BorderColor ## _color_type ## Green, src[1]); \
5045 macro(state.BorderColor ## _color_type ## Blue, src[2]); \
5046 macro(state.BorderColor ## _color_type ## Alpha, src[3]);
5047
5048 #if GEN_GEN >= 8
5049 /* On Broadwell, the border color is represented as four 32-bit floats,
5050 * integers, or unsigned values, interpreted according to the surface
5051 * format. This matches the sampler->BorderColor union exactly; just
5052 * memcpy the values.
5053 */
5054 BORDER_COLOR_ATTR(ASSIGN, 32bit, color.ui);
5055 #elif GEN_IS_HASWELL
5056 if (is_integer_format || is_stencil_sampling) {
5057 bool stencil = format == MESA_FORMAT_S_UINT8 || is_stencil_sampling;
5058 const int bits_per_channel =
5059 _mesa_get_format_bits(format, stencil ? GL_STENCIL_BITS : GL_RED_BITS);
5060
5061 /* From the Haswell PRM, "Command Reference: Structures", Page 36:
5062 * "If any color channel is missing from the surface format,
5063 * corresponding border color should be programmed as zero and if
5064 * alpha channel is missing, corresponding Alpha border color should
5065 * be programmed as 1."
5066 */
5067 unsigned c[4] = { 0, 0, 0, 1 };
5068 for (int i = 0; i < 4; i++) {
5069 if (has_component(format, i))
5070 c[i] = color.ui[i];
5071 }
5072
5073 switch (bits_per_channel) {
5074 case 8:
5075 /* Copy RGBA in order. */
5076 BORDER_COLOR_ATTR(ASSIGNu8, 8bit, c);
5077 break;
5078 case 10:
5079 /* R10G10B10A2_UINT is treated like a 16-bit format. */
5080 case 16:
5081 BORDER_COLOR_ATTR(ASSIGNu16, 16bit, c);
5082 break;
5083 case 32:
5084 if (base_format == GL_RG) {
5085 /* Careful inspection of the tables reveals that for RG32 formats,
5086 * the green channel needs to go where blue normally belongs.
5087 */
5088 state.BorderColor32bitRed = c[0];
5089 state.BorderColor32bitBlue = c[1];
5090 state.BorderColor32bitAlpha = 1;
5091 } else {
5092 /* Copy RGBA in order. */
5093 BORDER_COLOR_ATTR(ASSIGN, 32bit, c);
5094 }
5095 break;
5096 default:
5097 assert(!"Invalid number of bits per channel in integer format.");
5098 break;
5099 }
5100 } else {
5101 BORDER_COLOR_ATTR(ASSIGN, Float, color.f);
5102 }
5103 #elif GEN_GEN == 5 || GEN_GEN == 6
5104 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE, Unorm, color.f);
5105 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT, Unorm16, color.f);
5106 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT, Snorm16, color.f);
5107
5108 #define MESA_FLOAT_TO_HALF(dst, src) \
5109 dst = _mesa_float_to_half(src);
5110
5111 BORDER_COLOR_ATTR(MESA_FLOAT_TO_HALF, Float16, color.f);
5112
5113 #undef MESA_FLOAT_TO_HALF
5114
5115 state.BorderColorSnorm8Red = state.BorderColorSnorm16Red >> 8;
5116 state.BorderColorSnorm8Green = state.BorderColorSnorm16Green >> 8;
5117 state.BorderColorSnorm8Blue = state.BorderColorSnorm16Blue >> 8;
5118 state.BorderColorSnorm8Alpha = state.BorderColorSnorm16Alpha >> 8;
5119
5120 BORDER_COLOR_ATTR(ASSIGN, Float, color.f);
5121 #elif GEN_GEN == 4
5122 BORDER_COLOR_ATTR(ASSIGN, , color.f);
5123 #else
5124 BORDER_COLOR_ATTR(ASSIGN, Float, color.f);
5125 #endif
5126
5127 #undef ASSIGN
5128 #undef BORDER_COLOR_ATTR
5129
5130 GENX(SAMPLER_BORDER_COLOR_STATE_pack)(brw, sdc, &state);
5131 }
5132
5133 static uint32_t
5134 translate_wrap_mode(GLenum wrap, UNUSED bool using_nearest)
5135 {
5136 switch (wrap) {
5137 case GL_REPEAT:
5138 return TCM_WRAP;
5139 case GL_CLAMP:
5140 #if GEN_GEN >= 8
5141 /* GL_CLAMP is the weird mode where coordinates are clamped to
5142 * [0.0, 1.0], so linear filtering of coordinates outside of
5143 * [0.0, 1.0] give you half edge texel value and half border
5144 * color.
5145 *
5146 * Gen8+ supports this natively.
5147 */
5148 return TCM_HALF_BORDER;
5149 #else
5150 /* On Gen4-7.5, we clamp the coordinates in the fragment shader
5151 * and set clamp_border here, which gets the result desired.
5152 * We just use clamp(_to_edge) for nearest, because for nearest
5153 * clamping to 1.0 gives border color instead of the desired
5154 * edge texels.
5155 */
5156 if (using_nearest)
5157 return TCM_CLAMP;
5158 else
5159 return TCM_CLAMP_BORDER;
5160 #endif
5161 case GL_CLAMP_TO_EDGE:
5162 return TCM_CLAMP;
5163 case GL_CLAMP_TO_BORDER:
5164 return TCM_CLAMP_BORDER;
5165 case GL_MIRRORED_REPEAT:
5166 return TCM_MIRROR;
5167 case GL_MIRROR_CLAMP_TO_EDGE:
5168 return TCM_MIRROR_ONCE;
5169 default:
5170 return TCM_WRAP;
5171 }
5172 }
5173
5174 /**
5175 * Return true if the given wrap mode requires the border color to exist.
5176 */
5177 static bool
5178 wrap_mode_needs_border_color(unsigned wrap_mode)
5179 {
5180 #if GEN_GEN >= 8
5181 return wrap_mode == TCM_CLAMP_BORDER ||
5182 wrap_mode == TCM_HALF_BORDER;
5183 #else
5184 return wrap_mode == TCM_CLAMP_BORDER;
5185 #endif
5186 }
5187
5188 /**
5189 * Sets the sampler state for a single unit based off of the sampler key
5190 * entry.
5191 */
5192 static void
5193 genX(update_sampler_state)(struct brw_context *brw,
5194 GLenum target, bool tex_cube_map_seamless,
5195 GLfloat tex_unit_lod_bias,
5196 mesa_format format, GLenum base_format,
5197 const struct gl_texture_object *texObj,
5198 const struct gl_sampler_object *sampler,
5199 uint32_t *sampler_state)
5200 {
5201 struct GENX(SAMPLER_STATE) samp_st = { 0 };
5202
5203 /* Select min and mip filters. */
5204 switch (sampler->MinFilter) {
5205 case GL_NEAREST:
5206 samp_st.MinModeFilter = MAPFILTER_NEAREST;
5207 samp_st.MipModeFilter = MIPFILTER_NONE;
5208 break;
5209 case GL_LINEAR:
5210 samp_st.MinModeFilter = MAPFILTER_LINEAR;
5211 samp_st.MipModeFilter = MIPFILTER_NONE;
5212 break;
5213 case GL_NEAREST_MIPMAP_NEAREST:
5214 samp_st.MinModeFilter = MAPFILTER_NEAREST;
5215 samp_st.MipModeFilter = MIPFILTER_NEAREST;
5216 break;
5217 case GL_LINEAR_MIPMAP_NEAREST:
5218 samp_st.MinModeFilter = MAPFILTER_LINEAR;
5219 samp_st.MipModeFilter = MIPFILTER_NEAREST;
5220 break;
5221 case GL_NEAREST_MIPMAP_LINEAR:
5222 samp_st.MinModeFilter = MAPFILTER_NEAREST;
5223 samp_st.MipModeFilter = MIPFILTER_LINEAR;
5224 break;
5225 case GL_LINEAR_MIPMAP_LINEAR:
5226 samp_st.MinModeFilter = MAPFILTER_LINEAR;
5227 samp_st.MipModeFilter = MIPFILTER_LINEAR;
5228 break;
5229 default:
5230 unreachable("not reached");
5231 }
5232
5233 /* Select mag filter. */
5234 samp_st.MagModeFilter = sampler->MagFilter == GL_LINEAR ?
5235 MAPFILTER_LINEAR : MAPFILTER_NEAREST;
5236
5237 /* Enable anisotropic filtering if desired. */
5238 samp_st.MaximumAnisotropy = RATIO21;
5239
5240 if (sampler->MaxAnisotropy > 1.0f) {
5241 if (samp_st.MinModeFilter == MAPFILTER_LINEAR)
5242 samp_st.MinModeFilter = MAPFILTER_ANISOTROPIC;
5243 if (samp_st.MagModeFilter == MAPFILTER_LINEAR)
5244 samp_st.MagModeFilter = MAPFILTER_ANISOTROPIC;
5245
5246 if (sampler->MaxAnisotropy > 2.0f) {
5247 samp_st.MaximumAnisotropy =
5248 MIN2((sampler->MaxAnisotropy - 2) / 2, RATIO161);
5249 }
5250 }
5251
5252 /* Set address rounding bits if not using nearest filtering. */
5253 if (samp_st.MinModeFilter != MAPFILTER_NEAREST) {
5254 samp_st.UAddressMinFilterRoundingEnable = true;
5255 samp_st.VAddressMinFilterRoundingEnable = true;
5256 samp_st.RAddressMinFilterRoundingEnable = true;
5257 }
5258
5259 if (samp_st.MagModeFilter != MAPFILTER_NEAREST) {
5260 samp_st.UAddressMagFilterRoundingEnable = true;
5261 samp_st.VAddressMagFilterRoundingEnable = true;
5262 samp_st.RAddressMagFilterRoundingEnable = true;
5263 }
5264
5265 bool either_nearest =
5266 sampler->MinFilter == GL_NEAREST || sampler->MagFilter == GL_NEAREST;
5267 unsigned wrap_s = translate_wrap_mode(sampler->WrapS, either_nearest);
5268 unsigned wrap_t = translate_wrap_mode(sampler->WrapT, either_nearest);
5269 unsigned wrap_r = translate_wrap_mode(sampler->WrapR, either_nearest);
5270
5271 if (target == GL_TEXTURE_CUBE_MAP ||
5272 target == GL_TEXTURE_CUBE_MAP_ARRAY) {
5273 /* Cube maps must use the same wrap mode for all three coordinate
5274 * dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
5275 *
5276 * Ivybridge and Baytrail seem to have problems with CUBE mode and
5277 * integer formats. Fall back to CLAMP for now.
5278 */
5279 if ((tex_cube_map_seamless || sampler->CubeMapSeamless) &&
5280 !(GEN_GEN == 7 && !GEN_IS_HASWELL && texObj->_IsIntegerFormat)) {
5281 wrap_s = TCM_CUBE;
5282 wrap_t = TCM_CUBE;
5283 wrap_r = TCM_CUBE;
5284 } else {
5285 wrap_s = TCM_CLAMP;
5286 wrap_t = TCM_CLAMP;
5287 wrap_r = TCM_CLAMP;
5288 }
5289 } else if (target == GL_TEXTURE_1D) {
5290 /* There's a bug in 1D texture sampling - it actually pays
5291 * attention to the wrap_t value, though it should not.
5292 * Override the wrap_t value here to GL_REPEAT to keep
5293 * any nonexistent border pixels from floating in.
5294 */
5295 wrap_t = TCM_WRAP;
5296 }
5297
5298 samp_st.TCXAddressControlMode = wrap_s;
5299 samp_st.TCYAddressControlMode = wrap_t;
5300 samp_st.TCZAddressControlMode = wrap_r;
5301
5302 samp_st.ShadowFunction =
5303 sampler->CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB ?
5304 intel_translate_shadow_compare_func(sampler->CompareFunc) : 0;
5305
5306 #if GEN_GEN >= 7
5307 /* Set shadow function. */
5308 samp_st.AnisotropicAlgorithm =
5309 samp_st.MinModeFilter == MAPFILTER_ANISOTROPIC ?
5310 EWAApproximation : LEGACY;
5311 #endif
5312
5313 #if GEN_GEN >= 6
5314 samp_st.NonnormalizedCoordinateEnable = target == GL_TEXTURE_RECTANGLE;
5315 #endif
5316
5317 const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13;
5318 samp_st.MinLOD = CLAMP(sampler->MinLod, 0, hw_max_lod);
5319 samp_st.MaxLOD = CLAMP(sampler->MaxLod, 0, hw_max_lod);
5320 samp_st.TextureLODBias =
5321 CLAMP(tex_unit_lod_bias + sampler->LodBias, -16, 15);
5322
5323 #if GEN_GEN == 6
5324 samp_st.BaseMipLevel =
5325 CLAMP(texObj->MinLevel + texObj->BaseLevel, 0, hw_max_lod);
5326 samp_st.MinandMagStateNotEqual =
5327 samp_st.MinModeFilter != samp_st.MagModeFilter;
5328 #endif
5329
5330 /* Upload the border color if necessary. If not, just point it at
5331 * offset 0 (the start of the batch) - the color should be ignored,
5332 * but that address won't fault in case something reads it anyway.
5333 */
5334 uint32_t border_color_offset = 0;
5335 if (wrap_mode_needs_border_color(wrap_s) ||
5336 wrap_mode_needs_border_color(wrap_t) ||
5337 wrap_mode_needs_border_color(wrap_r)) {
5338 genX(upload_default_color)(brw, sampler, format, base_format,
5339 texObj->_IsIntegerFormat,
5340 texObj->StencilSampling,
5341 &border_color_offset);
5342 }
5343 #if GEN_GEN < 6
5344 samp_st.BorderColorPointer =
5345 ro_bo(brw->batch.state.bo, border_color_offset);
5346 #else
5347 samp_st.BorderColorPointer = border_color_offset;
5348 #endif
5349
5350 #if GEN_GEN >= 8
5351 samp_st.LODPreClampMode = CLAMP_MODE_OGL;
5352 #else
5353 samp_st.LODPreClampEnable = true;
5354 #endif
5355
5356 GENX(SAMPLER_STATE_pack)(brw, sampler_state, &samp_st);
5357 }
5358
5359 static void
5360 update_sampler_state(struct brw_context *brw,
5361 int unit,
5362 uint32_t *sampler_state)
5363 {
5364 struct gl_context *ctx = &brw->ctx;
5365 const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
5366 const struct gl_texture_object *texObj = texUnit->_Current;
5367 const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
5368
5369 /* These don't use samplers at all. */
5370 if (texObj->Target == GL_TEXTURE_BUFFER)
5371 return;
5372
5373 struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel];
5374 genX(update_sampler_state)(brw, texObj->Target,
5375 ctx->Texture.CubeMapSeamless,
5376 texUnit->LodBias,
5377 firstImage->TexFormat, firstImage->_BaseFormat,
5378 texObj, sampler,
5379 sampler_state);
5380 }
5381
5382 static void
5383 genX(upload_sampler_state_table)(struct brw_context *brw,
5384 struct gl_program *prog,
5385 struct brw_stage_state *stage_state)
5386 {
5387 struct gl_context *ctx = &brw->ctx;
5388 uint32_t sampler_count = stage_state->sampler_count;
5389
5390 GLbitfield SamplersUsed = prog->SamplersUsed;
5391
5392 if (sampler_count == 0)
5393 return;
5394
5395 /* SAMPLER_STATE is 4 DWords on all platforms. */
5396 const int dwords = GENX(SAMPLER_STATE_length);
5397 const int size_in_bytes = dwords * sizeof(uint32_t);
5398
5399 uint32_t *sampler_state = brw_state_batch(brw,
5400 sampler_count * size_in_bytes,
5401 32, &stage_state->sampler_offset);
5402 /* memset(sampler_state, 0, sampler_count * size_in_bytes); */
5403
5404 for (unsigned s = 0; s < sampler_count; s++) {
5405 if (SamplersUsed & (1 << s)) {
5406 const unsigned unit = prog->SamplerUnits[s];
5407 if (ctx->Texture.Unit[unit]._Current) {
5408 update_sampler_state(brw, unit, sampler_state);
5409 }
5410 }
5411
5412 sampler_state += dwords;
5413 }
5414
5415 if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
5416 /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
5417 genX(emit_sampler_state_pointers_xs)(brw, stage_state);
5418 } else {
5419 /* Flag that the sampler state table pointer has changed; later atoms
5420 * will handle it.
5421 */
5422 brw->ctx.NewDriverState |= BRW_NEW_SAMPLER_STATE_TABLE;
5423 }
5424 }
5425
5426 static void
5427 genX(upload_fs_samplers)(struct brw_context *brw)
5428 {
5429 /* BRW_NEW_FRAGMENT_PROGRAM */
5430 struct gl_program *fs = brw->programs[MESA_SHADER_FRAGMENT];
5431 genX(upload_sampler_state_table)(brw, fs, &brw->wm.base);
5432 }
5433
5434 static const struct brw_tracked_state genX(fs_samplers) = {
5435 .dirty = {
5436 .mesa = _NEW_TEXTURE,
5437 .brw = BRW_NEW_BATCH |
5438 BRW_NEW_BLORP |
5439 BRW_NEW_FRAGMENT_PROGRAM,
5440 },
5441 .emit = genX(upload_fs_samplers),
5442 };
5443
5444 static void
5445 genX(upload_vs_samplers)(struct brw_context *brw)
5446 {
5447 /* BRW_NEW_VERTEX_PROGRAM */
5448 struct gl_program *vs = brw->programs[MESA_SHADER_VERTEX];
5449 genX(upload_sampler_state_table)(brw, vs, &brw->vs.base);
5450 }
5451
5452 static const struct brw_tracked_state genX(vs_samplers) = {
5453 .dirty = {
5454 .mesa = _NEW_TEXTURE,
5455 .brw = BRW_NEW_BATCH |
5456 BRW_NEW_BLORP |
5457 BRW_NEW_VERTEX_PROGRAM,
5458 },
5459 .emit = genX(upload_vs_samplers),
5460 };
5461
5462 #if GEN_GEN >= 6
5463 static void
5464 genX(upload_gs_samplers)(struct brw_context *brw)
5465 {
5466 /* BRW_NEW_GEOMETRY_PROGRAM */
5467 struct gl_program *gs = brw->programs[MESA_SHADER_GEOMETRY];
5468 if (!gs)
5469 return;
5470
5471 genX(upload_sampler_state_table)(brw, gs, &brw->gs.base);
5472 }
5473
5474
5475 static const struct brw_tracked_state genX(gs_samplers) = {
5476 .dirty = {
5477 .mesa = _NEW_TEXTURE,
5478 .brw = BRW_NEW_BATCH |
5479 BRW_NEW_BLORP |
5480 BRW_NEW_GEOMETRY_PROGRAM,
5481 },
5482 .emit = genX(upload_gs_samplers),
5483 };
5484 #endif
5485
5486 #if GEN_GEN >= 7
5487 static void
5488 genX(upload_tcs_samplers)(struct brw_context *brw)
5489 {
5490 /* BRW_NEW_TESS_PROGRAMS */
5491 struct gl_program *tcs = brw->programs[MESA_SHADER_TESS_CTRL];
5492 if (!tcs)
5493 return;
5494
5495 genX(upload_sampler_state_table)(brw, tcs, &brw->tcs.base);
5496 }
5497
5498 static const struct brw_tracked_state genX(tcs_samplers) = {
5499 .dirty = {
5500 .mesa = _NEW_TEXTURE,
5501 .brw = BRW_NEW_BATCH |
5502 BRW_NEW_BLORP |
5503 BRW_NEW_TESS_PROGRAMS,
5504 },
5505 .emit = genX(upload_tcs_samplers),
5506 };
5507 #endif
5508
5509 #if GEN_GEN >= 7
5510 static void
5511 genX(upload_tes_samplers)(struct brw_context *brw)
5512 {
5513 /* BRW_NEW_TESS_PROGRAMS */
5514 struct gl_program *tes = brw->programs[MESA_SHADER_TESS_EVAL];
5515 if (!tes)
5516 return;
5517
5518 genX(upload_sampler_state_table)(brw, tes, &brw->tes.base);
5519 }
5520
5521 static const struct brw_tracked_state genX(tes_samplers) = {
5522 .dirty = {
5523 .mesa = _NEW_TEXTURE,
5524 .brw = BRW_NEW_BATCH |
5525 BRW_NEW_BLORP |
5526 BRW_NEW_TESS_PROGRAMS,
5527 },
5528 .emit = genX(upload_tes_samplers),
5529 };
5530 #endif
5531
5532 #if GEN_GEN >= 7
5533 static void
5534 genX(upload_cs_samplers)(struct brw_context *brw)
5535 {
5536 /* BRW_NEW_COMPUTE_PROGRAM */
5537 struct gl_program *cs = brw->programs[MESA_SHADER_COMPUTE];
5538 if (!cs)
5539 return;
5540
5541 genX(upload_sampler_state_table)(brw, cs, &brw->cs.base);
5542 }
5543
5544 const struct brw_tracked_state genX(cs_samplers) = {
5545 .dirty = {
5546 .mesa = _NEW_TEXTURE,
5547 .brw = BRW_NEW_BATCH |
5548 BRW_NEW_BLORP |
5549 BRW_NEW_COMPUTE_PROGRAM,
5550 },
5551 .emit = genX(upload_cs_samplers),
5552 };
5553 #endif
5554
5555 /* ---------------------------------------------------------------------- */
5556
5557 #if GEN_GEN <= 5
5558
5559 static void genX(upload_blend_constant_color)(struct brw_context *brw)
5560 {
5561 struct gl_context *ctx = &brw->ctx;
5562
5563 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_COLOR), blend_cc) {
5564 blend_cc.BlendConstantColorRed = ctx->Color.BlendColorUnclamped[0];
5565 blend_cc.BlendConstantColorGreen = ctx->Color.BlendColorUnclamped[1];
5566 blend_cc.BlendConstantColorBlue = ctx->Color.BlendColorUnclamped[2];
5567 blend_cc.BlendConstantColorAlpha = ctx->Color.BlendColorUnclamped[3];
5568 }
5569 }
5570
5571 static const struct brw_tracked_state genX(blend_constant_color) = {
5572 .dirty = {
5573 .mesa = _NEW_COLOR,
5574 .brw = BRW_NEW_CONTEXT |
5575 BRW_NEW_BLORP,
5576 },
5577 .emit = genX(upload_blend_constant_color)
5578 };
5579 #endif
5580
5581 /* ---------------------------------------------------------------------- */
5582
5583 void
5584 genX(init_atoms)(struct brw_context *brw)
5585 {
5586 #if GEN_GEN < 6
5587 static const struct brw_tracked_state *render_atoms[] =
5588 {
5589 &genX(vf_statistics),
5590
5591 /* Once all the programs are done, we know how large urb entry
5592 * sizes need to be and can decide if we need to change the urb
5593 * layout.
5594 */
5595 &brw_curbe_offsets,
5596 &brw_recalculate_urb_fence,
5597
5598 &genX(cc_vp),
5599 &genX(color_calc_state),
5600
5601 /* Surface state setup. Must come before the VS/WM unit. The binding
5602 * table upload must be last.
5603 */
5604 &brw_vs_pull_constants,
5605 &brw_wm_pull_constants,
5606 &brw_renderbuffer_surfaces,
5607 &brw_renderbuffer_read_surfaces,
5608 &brw_texture_surfaces,
5609 &brw_vs_binding_table,
5610 &brw_wm_binding_table,
5611
5612 &genX(fs_samplers),
5613 &genX(vs_samplers),
5614
5615 /* These set up state for brw_psp_urb_cbs */
5616 &genX(wm_state),
5617 &genX(sf_clip_viewport),
5618 &genX(sf_state),
5619 &genX(vs_state), /* always required, enabled or not */
5620 &genX(clip_state),
5621 &genX(gs_state),
5622
5623 /* Command packets:
5624 */
5625 &brw_binding_table_pointers,
5626 &genX(blend_constant_color),
5627
5628 &brw_depthbuffer,
5629
5630 &genX(polygon_stipple),
5631 &genX(polygon_stipple_offset),
5632
5633 &genX(line_stipple),
5634
5635 &brw_psp_urb_cbs,
5636
5637 &genX(drawing_rect),
5638 &brw_indices, /* must come before brw_vertices */
5639 &genX(index_buffer),
5640 &genX(vertices),
5641
5642 &brw_constant_buffer
5643 };
5644 #elif GEN_GEN == 6
5645 static const struct brw_tracked_state *render_atoms[] =
5646 {
5647 &genX(vf_statistics),
5648
5649 &genX(sf_clip_viewport),
5650
5651 /* Command packets: */
5652
5653 &genX(cc_vp),
5654
5655 &gen6_urb,
5656 &genX(blend_state), /* must do before cc unit */
5657 &genX(color_calc_state), /* must do before cc unit */
5658 &genX(depth_stencil_state), /* must do before cc unit */
5659
5660 &genX(vs_push_constants), /* Before vs_state */
5661 &genX(gs_push_constants), /* Before gs_state */
5662 &genX(wm_push_constants), /* Before wm_state */
5663
5664 /* Surface state setup. Must come before the VS/WM unit. The binding
5665 * table upload must be last.
5666 */
5667 &brw_vs_pull_constants,
5668 &brw_vs_ubo_surfaces,
5669 &brw_gs_pull_constants,
5670 &brw_gs_ubo_surfaces,
5671 &brw_wm_pull_constants,
5672 &brw_wm_ubo_surfaces,
5673 &gen6_renderbuffer_surfaces,
5674 &brw_renderbuffer_read_surfaces,
5675 &brw_texture_surfaces,
5676 &gen6_sol_surface,
5677 &brw_vs_binding_table,
5678 &gen6_gs_binding_table,
5679 &brw_wm_binding_table,
5680
5681 &genX(fs_samplers),
5682 &genX(vs_samplers),
5683 &genX(gs_samplers),
5684 &gen6_sampler_state,
5685 &genX(multisample_state),
5686
5687 &genX(vs_state),
5688 &genX(gs_state),
5689 &genX(clip_state),
5690 &genX(sf_state),
5691 &genX(wm_state),
5692
5693 &genX(scissor_state),
5694
5695 &gen6_binding_table_pointers,
5696
5697 &brw_depthbuffer,
5698
5699 &genX(polygon_stipple),
5700 &genX(polygon_stipple_offset),
5701
5702 &genX(line_stipple),
5703
5704 &genX(drawing_rect),
5705
5706 &brw_indices, /* must come before brw_vertices */
5707 &genX(index_buffer),
5708 &genX(vertices),
5709 };
5710 #elif GEN_GEN == 7
5711 static const struct brw_tracked_state *render_atoms[] =
5712 {
5713 &genX(vf_statistics),
5714
5715 /* Command packets: */
5716
5717 &genX(cc_vp),
5718 &genX(sf_clip_viewport),
5719
5720 &gen7_l3_state,
5721 &gen7_push_constant_space,
5722 &gen7_urb,
5723 #if GEN_IS_HASWELL
5724 &genX(cc_and_blend_state),
5725 #else
5726 &genX(blend_state), /* must do before cc unit */
5727 &genX(color_calc_state), /* must do before cc unit */
5728 #endif
5729 &genX(depth_stencil_state), /* must do before cc unit */
5730
5731 &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
5732 &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
5733 &brw_tes_image_surfaces, /* Before tes push/pull constants and binding table */
5734 &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
5735 &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
5736
5737 &genX(vs_push_constants), /* Before vs_state */
5738 &genX(tcs_push_constants),
5739 &genX(tes_push_constants),
5740 &genX(gs_push_constants), /* Before gs_state */
5741 &genX(wm_push_constants), /* Before wm_surfaces and constant_buffer */
5742
5743 /* Surface state setup. Must come before the VS/WM unit. The binding
5744 * table upload must be last.
5745 */
5746 &brw_vs_pull_constants,
5747 &brw_vs_ubo_surfaces,
5748 &brw_tcs_pull_constants,
5749 &brw_tcs_ubo_surfaces,
5750 &brw_tes_pull_constants,
5751 &brw_tes_ubo_surfaces,
5752 &brw_gs_pull_constants,
5753 &brw_gs_ubo_surfaces,
5754 &brw_wm_pull_constants,
5755 &brw_wm_ubo_surfaces,
5756 &gen6_renderbuffer_surfaces,
5757 &brw_renderbuffer_read_surfaces,
5758 &brw_texture_surfaces,
5759
5760 &genX(push_constant_packets),
5761
5762 &brw_vs_binding_table,
5763 &brw_tcs_binding_table,
5764 &brw_tes_binding_table,
5765 &brw_gs_binding_table,
5766 &brw_wm_binding_table,
5767
5768 &genX(fs_samplers),
5769 &genX(vs_samplers),
5770 &genX(tcs_samplers),
5771 &genX(tes_samplers),
5772 &genX(gs_samplers),
5773 &genX(multisample_state),
5774
5775 &genX(vs_state),
5776 &genX(hs_state),
5777 &genX(te_state),
5778 &genX(ds_state),
5779 &genX(gs_state),
5780 &genX(sol_state),
5781 &genX(clip_state),
5782 &genX(sbe_state),
5783 &genX(sf_state),
5784 &genX(wm_state),
5785 &genX(ps_state),
5786
5787 &genX(scissor_state),
5788
5789 &brw_depthbuffer,
5790
5791 &genX(polygon_stipple),
5792 &genX(polygon_stipple_offset),
5793
5794 &genX(line_stipple),
5795
5796 &genX(drawing_rect),
5797
5798 &brw_indices, /* must come before brw_vertices */
5799 &genX(index_buffer),
5800 &genX(vertices),
5801
5802 #if GEN_IS_HASWELL
5803 &genX(cut_index),
5804 #endif
5805 };
5806 #elif GEN_GEN >= 8
5807 static const struct brw_tracked_state *render_atoms[] =
5808 {
5809 &genX(vf_statistics),
5810
5811 &genX(cc_vp),
5812 &genX(sf_clip_viewport),
5813
5814 &gen7_l3_state,
5815 &gen7_push_constant_space,
5816 &gen7_urb,
5817 &genX(blend_state),
5818 &genX(color_calc_state),
5819
5820 &brw_vs_image_surfaces, /* Before vs push/pull constants and binding table */
5821 &brw_tcs_image_surfaces, /* Before tcs push/pull constants and binding table */
5822 &brw_tes_image_surfaces, /* Before tes push/pull constants and binding table */
5823 &brw_gs_image_surfaces, /* Before gs push/pull constants and binding table */
5824 &brw_wm_image_surfaces, /* Before wm push/pull constants and binding table */
5825
5826 &genX(vs_push_constants), /* Before vs_state */
5827 &genX(tcs_push_constants),
5828 &genX(tes_push_constants),
5829 &genX(gs_push_constants), /* Before gs_state */
5830 &genX(wm_push_constants), /* Before wm_surfaces and constant_buffer */
5831
5832 /* Surface state setup. Must come before the VS/WM unit. The binding
5833 * table upload must be last.
5834 */
5835 &brw_vs_pull_constants,
5836 &brw_vs_ubo_surfaces,
5837 &brw_tcs_pull_constants,
5838 &brw_tcs_ubo_surfaces,
5839 &brw_tes_pull_constants,
5840 &brw_tes_ubo_surfaces,
5841 &brw_gs_pull_constants,
5842 &brw_gs_ubo_surfaces,
5843 &brw_wm_pull_constants,
5844 &brw_wm_ubo_surfaces,
5845 &gen6_renderbuffer_surfaces,
5846 &brw_renderbuffer_read_surfaces,
5847 &brw_texture_surfaces,
5848
5849 &genX(push_constant_packets),
5850
5851 &brw_vs_binding_table,
5852 &brw_tcs_binding_table,
5853 &brw_tes_binding_table,
5854 &brw_gs_binding_table,
5855 &brw_wm_binding_table,
5856
5857 &genX(fs_samplers),
5858 &genX(vs_samplers),
5859 &genX(tcs_samplers),
5860 &genX(tes_samplers),
5861 &genX(gs_samplers),
5862 &genX(multisample_state),
5863
5864 &genX(vs_state),
5865 &genX(hs_state),
5866 &genX(te_state),
5867 &genX(ds_state),
5868 &genX(gs_state),
5869 &genX(sol_state),
5870 &genX(clip_state),
5871 &genX(raster_state),
5872 &genX(sbe_state),
5873 &genX(sf_state),
5874 &genX(ps_blend),
5875 &genX(ps_extra),
5876 &genX(ps_state),
5877 &genX(depth_stencil_state),
5878 &genX(wm_state),
5879
5880 &genX(scissor_state),
5881
5882 &brw_depthbuffer,
5883
5884 &genX(polygon_stipple),
5885 &genX(polygon_stipple_offset),
5886
5887 &genX(line_stipple),
5888
5889 &genX(drawing_rect),
5890
5891 &genX(vf_topology),
5892
5893 &brw_indices,
5894 &genX(index_buffer),
5895 &genX(vertices),
5896
5897 &genX(cut_index),
5898 &gen8_pma_fix,
5899 };
5900 #endif
5901
5902 STATIC_ASSERT(ARRAY_SIZE(render_atoms) <= ARRAY_SIZE(brw->render_atoms));
5903 brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE,
5904 render_atoms, ARRAY_SIZE(render_atoms));
5905
5906 #if GEN_GEN >= 7
5907 static const struct brw_tracked_state *compute_atoms[] =
5908 {
5909 &gen7_l3_state,
5910 &brw_cs_image_surfaces,
5911 &genX(cs_push_constants),
5912 &genX(cs_pull_constants),
5913 &brw_cs_ubo_surfaces,
5914 &brw_cs_texture_surfaces,
5915 &brw_cs_work_groups_surface,
5916 &genX(cs_samplers),
5917 &genX(cs_state),
5918 };
5919
5920 STATIC_ASSERT(ARRAY_SIZE(compute_atoms) <= ARRAY_SIZE(brw->compute_atoms));
5921 brw_copy_pipeline_atoms(brw, BRW_COMPUTE_PIPELINE,
5922 compute_atoms, ARRAY_SIZE(compute_atoms));
5923
5924 brw->vtbl.emit_mi_report_perf_count = genX(emit_mi_report_perf_count);
5925 brw->vtbl.emit_compute_walker = genX(emit_gpgpu_walker);
5926 #endif
5927 }
5928