1 /*
2  * Copyright © 2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "brw_fs.h"
27 #include "brw_nir.h"
28 #include "brw_vec4_tes.h"
29 #include "dev/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
32 
33 enum brw_reg_type
brw_type_for_base_type(const struct glsl_type * type)34 brw_type_for_base_type(const struct glsl_type *type)
35 {
36    switch (type->base_type) {
37    case GLSL_TYPE_FLOAT16:
38       return BRW_REGISTER_TYPE_HF;
39    case GLSL_TYPE_FLOAT:
40       return BRW_REGISTER_TYPE_F;
41    case GLSL_TYPE_INT:
42    case GLSL_TYPE_BOOL:
43    case GLSL_TYPE_SUBROUTINE:
44       return BRW_REGISTER_TYPE_D;
45    case GLSL_TYPE_INT16:
46       return BRW_REGISTER_TYPE_W;
47    case GLSL_TYPE_INT8:
48       return BRW_REGISTER_TYPE_B;
49    case GLSL_TYPE_UINT:
50       return BRW_REGISTER_TYPE_UD;
51    case GLSL_TYPE_UINT16:
52       return BRW_REGISTER_TYPE_UW;
53    case GLSL_TYPE_UINT8:
54       return BRW_REGISTER_TYPE_UB;
55    case GLSL_TYPE_ARRAY:
56       return brw_type_for_base_type(type->fields.array);
57    case GLSL_TYPE_STRUCT:
58    case GLSL_TYPE_INTERFACE:
59    case GLSL_TYPE_SAMPLER:
60    case GLSL_TYPE_ATOMIC_UINT:
61       /* These should be overridden with the type of the member when
62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
63        * way to trip up if we don't.
64        */
65       return BRW_REGISTER_TYPE_UD;
66    case GLSL_TYPE_IMAGE:
67       return BRW_REGISTER_TYPE_UD;
68    case GLSL_TYPE_DOUBLE:
69       return BRW_REGISTER_TYPE_DF;
70    case GLSL_TYPE_UINT64:
71       return BRW_REGISTER_TYPE_UQ;
72    case GLSL_TYPE_INT64:
73       return BRW_REGISTER_TYPE_Q;
74    case GLSL_TYPE_VOID:
75    case GLSL_TYPE_ERROR:
76    case GLSL_TYPE_FUNCTION:
77       unreachable("not reached");
78    }
79 
80    return BRW_REGISTER_TYPE_F;
81 }
82 
83 enum brw_conditional_mod
brw_conditional_for_comparison(unsigned int op)84 brw_conditional_for_comparison(unsigned int op)
85 {
86    switch (op) {
87    case ir_binop_less:
88       return BRW_CONDITIONAL_L;
89    case ir_binop_gequal:
90       return BRW_CONDITIONAL_GE;
91    case ir_binop_equal:
92    case ir_binop_all_equal: /* same as equal for scalars */
93       return BRW_CONDITIONAL_Z;
94    case ir_binop_nequal:
95    case ir_binop_any_nequal: /* same as nequal for scalars */
96       return BRW_CONDITIONAL_NZ;
97    default:
98       unreachable("not reached: bad operation for comparison");
99    }
100 }
101 
102 uint32_t
brw_math_function(enum opcode op)103 brw_math_function(enum opcode op)
104 {
105    switch (op) {
106    case SHADER_OPCODE_RCP:
107       return BRW_MATH_FUNCTION_INV;
108    case SHADER_OPCODE_RSQ:
109       return BRW_MATH_FUNCTION_RSQ;
110    case SHADER_OPCODE_SQRT:
111       return BRW_MATH_FUNCTION_SQRT;
112    case SHADER_OPCODE_EXP2:
113       return BRW_MATH_FUNCTION_EXP;
114    case SHADER_OPCODE_LOG2:
115       return BRW_MATH_FUNCTION_LOG;
116    case SHADER_OPCODE_POW:
117       return BRW_MATH_FUNCTION_POW;
118    case SHADER_OPCODE_SIN:
119       return BRW_MATH_FUNCTION_SIN;
120    case SHADER_OPCODE_COS:
121       return BRW_MATH_FUNCTION_COS;
122    case SHADER_OPCODE_INT_QUOTIENT:
123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
124    case SHADER_OPCODE_INT_REMAINDER:
125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
126    default:
127       unreachable("not reached: unknown math function");
128    }
129 }
130 
131 bool
brw_texture_offset(const nir_tex_instr * tex,unsigned src,uint32_t * offset_bits_out)132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
133                    uint32_t *offset_bits_out)
134 {
135    if (!nir_src_is_const(tex->src[src].src))
136       return false;
137 
138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
139 
140    /* Combine all three offsets into a single unsigned dword:
141     *
142     *    bits 11:8 - U Offset (X component)
143     *    bits  7:4 - V Offset (Y component)
144     *    bits  3:0 - R Offset (Z component)
145     */
146    uint32_t offset_bits = 0;
147    for (unsigned i = 0; i < num_components; i++) {
148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
149 
150       /* offset out of bounds; caller will handle it. */
151       if (offset > 7 || offset < -8)
152          return false;
153 
154       const unsigned shift = 4 * (2 - i);
155       offset_bits |= (offset << shift) & (0xF << shift);
156    }
157 
158    *offset_bits_out = offset_bits;
159 
160    return true;
161 }
162 
163 const char *
brw_instruction_name(const struct gen_device_info * devinfo,enum opcode op)164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
165 {
166    switch (op) {
167    case 0 ... NUM_BRW_OPCODES - 1:
168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
169        * start of a loop in the IR.
170        */
171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
172          return "do";
173 
174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
175        * then to mark that we want to do the conversion.
176        */
177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
178          return "f32to16";
179 
180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
181          return "f16to32";
182 
183       assert(brw_opcode_desc(devinfo, op)->name);
184       return brw_opcode_desc(devinfo, op)->name;
185    case FS_OPCODE_FB_WRITE:
186       return "fb_write";
187    case FS_OPCODE_FB_WRITE_LOGICAL:
188       return "fb_write_logical";
189    case FS_OPCODE_REP_FB_WRITE:
190       return "rep_fb_write";
191    case FS_OPCODE_FB_READ:
192       return "fb_read";
193    case FS_OPCODE_FB_READ_LOGICAL:
194       return "fb_read_logical";
195 
196    case SHADER_OPCODE_RCP:
197       return "rcp";
198    case SHADER_OPCODE_RSQ:
199       return "rsq";
200    case SHADER_OPCODE_SQRT:
201       return "sqrt";
202    case SHADER_OPCODE_EXP2:
203       return "exp2";
204    case SHADER_OPCODE_LOG2:
205       return "log2";
206    case SHADER_OPCODE_POW:
207       return "pow";
208    case SHADER_OPCODE_INT_QUOTIENT:
209       return "int_quot";
210    case SHADER_OPCODE_INT_REMAINDER:
211       return "int_rem";
212    case SHADER_OPCODE_SIN:
213       return "sin";
214    case SHADER_OPCODE_COS:
215       return "cos";
216 
217    case SHADER_OPCODE_SEND:
218       return "send";
219 
220    case SHADER_OPCODE_UNDEF:
221       return "undef";
222 
223    case SHADER_OPCODE_TEX:
224       return "tex";
225    case SHADER_OPCODE_TEX_LOGICAL:
226       return "tex_logical";
227    case SHADER_OPCODE_TXD:
228       return "txd";
229    case SHADER_OPCODE_TXD_LOGICAL:
230       return "txd_logical";
231    case SHADER_OPCODE_TXF:
232       return "txf";
233    case SHADER_OPCODE_TXF_LOGICAL:
234       return "txf_logical";
235    case SHADER_OPCODE_TXF_LZ:
236       return "txf_lz";
237    case SHADER_OPCODE_TXL:
238       return "txl";
239    case SHADER_OPCODE_TXL_LOGICAL:
240       return "txl_logical";
241    case SHADER_OPCODE_TXL_LZ:
242       return "txl_lz";
243    case SHADER_OPCODE_TXS:
244       return "txs";
245    case SHADER_OPCODE_TXS_LOGICAL:
246       return "txs_logical";
247    case FS_OPCODE_TXB:
248       return "txb";
249    case FS_OPCODE_TXB_LOGICAL:
250       return "txb_logical";
251    case SHADER_OPCODE_TXF_CMS:
252       return "txf_cms";
253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
254       return "txf_cms_logical";
255    case SHADER_OPCODE_TXF_CMS_W:
256       return "txf_cms_w";
257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
258       return "txf_cms_w_logical";
259    case SHADER_OPCODE_TXF_UMS:
260       return "txf_ums";
261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
262       return "txf_ums_logical";
263    case SHADER_OPCODE_TXF_MCS:
264       return "txf_mcs";
265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
266       return "txf_mcs_logical";
267    case SHADER_OPCODE_LOD:
268       return "lod";
269    case SHADER_OPCODE_LOD_LOGICAL:
270       return "lod_logical";
271    case SHADER_OPCODE_TG4:
272       return "tg4";
273    case SHADER_OPCODE_TG4_LOGICAL:
274       return "tg4_logical";
275    case SHADER_OPCODE_TG4_OFFSET:
276       return "tg4_offset";
277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
278       return "tg4_offset_logical";
279    case SHADER_OPCODE_SAMPLEINFO:
280       return "sampleinfo";
281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
282       return "sampleinfo_logical";
283 
284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
285       return "image_size_logical";
286 
287    case SHADER_OPCODE_SHADER_TIME_ADD:
288       return "shader_time_add";
289 
290    case VEC4_OPCODE_UNTYPED_ATOMIC:
291       return "untyped_atomic";
292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
293       return "untyped_atomic_logical";
294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
295       return "untyped_atomic_float_logical";
296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
297       return "untyped_surface_read";
298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
299       return "untyped_surface_read_logical";
300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
301       return "untyped_surface_write";
302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
303       return "untyped_surface_write_logical";
304    case SHADER_OPCODE_OWORD_BLOCK_READ_LOGICAL:
305       return "oword_block_read_logical";
306    case SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
307       return "unaligned_oword_block_read_logical";
308    case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
309       return "oword_block_write_logical";
310    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
311       return "a64_untyped_read_logical";
312    case SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
313       return "a64_oword_block_read_logical";
314    case SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
315       return "a64_unaligned_oword_block_read_logical";
316    case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
317       return "a64_oword_block_write_logical";
318    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
319       return "a64_untyped_write_logical";
320    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
321       return "a64_byte_scattered_read_logical";
322    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
323       return "a64_byte_scattered_write_logical";
324    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
325       return "a64_untyped_atomic_logical";
326    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
327       return "a64_untyped_atomic_int64_logical";
328    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
329       return "a64_untyped_atomic_float_logical";
330    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
331       return "typed_atomic_logical";
332    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
333       return "typed_surface_read_logical";
334    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
335       return "typed_surface_write_logical";
336    case SHADER_OPCODE_MEMORY_FENCE:
337       return "memory_fence";
338    case FS_OPCODE_SCHEDULING_FENCE:
339       return "scheduling_fence";
340    case SHADER_OPCODE_INTERLOCK:
341       /* For an interlock we actually issue a memory fence via sendc. */
342       return "interlock";
343 
344    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
345       return "byte_scattered_read_logical";
346    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
347       return "byte_scattered_write_logical";
348    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
349       return "dword_scattered_read_logical";
350    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
351       return "dword_scattered_write_logical";
352 
353    case SHADER_OPCODE_LOAD_PAYLOAD:
354       return "load_payload";
355    case FS_OPCODE_PACK:
356       return "pack";
357 
358    case SHADER_OPCODE_GEN4_SCRATCH_READ:
359       return "gen4_scratch_read";
360    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
361       return "gen4_scratch_write";
362    case SHADER_OPCODE_GEN7_SCRATCH_READ:
363       return "gen7_scratch_read";
364    case SHADER_OPCODE_SCRATCH_HEADER:
365       return "scratch_header";
366    case SHADER_OPCODE_URB_WRITE_SIMD8:
367       return "gen8_urb_write_simd8";
368    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
369       return "gen8_urb_write_simd8_per_slot";
370    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
371       return "gen8_urb_write_simd8_masked";
372    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
373       return "gen8_urb_write_simd8_masked_per_slot";
374    case SHADER_OPCODE_URB_READ_SIMD8:
375       return "urb_read_simd8";
376    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
377       return "urb_read_simd8_per_slot";
378 
379    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
380       return "find_live_channel";
381    case FS_OPCODE_LOAD_LIVE_CHANNELS:
382       return "load_live_channels";
383 
384    case SHADER_OPCODE_BROADCAST:
385       return "broadcast";
386    case SHADER_OPCODE_SHUFFLE:
387       return "shuffle";
388    case SHADER_OPCODE_SEL_EXEC:
389       return "sel_exec";
390    case SHADER_OPCODE_QUAD_SWIZZLE:
391       return "quad_swizzle";
392    case SHADER_OPCODE_CLUSTER_BROADCAST:
393       return "cluster_broadcast";
394 
395    case SHADER_OPCODE_GET_BUFFER_SIZE:
396       return "get_buffer_size";
397 
398    case VEC4_OPCODE_MOV_BYTES:
399       return "mov_bytes";
400    case VEC4_OPCODE_PACK_BYTES:
401       return "pack_bytes";
402    case VEC4_OPCODE_UNPACK_UNIFORM:
403       return "unpack_uniform";
404    case VEC4_OPCODE_DOUBLE_TO_F32:
405       return "double_to_f32";
406    case VEC4_OPCODE_DOUBLE_TO_D32:
407       return "double_to_d32";
408    case VEC4_OPCODE_DOUBLE_TO_U32:
409       return "double_to_u32";
410    case VEC4_OPCODE_TO_DOUBLE:
411       return "single_to_double";
412    case VEC4_OPCODE_PICK_LOW_32BIT:
413       return "pick_low_32bit";
414    case VEC4_OPCODE_PICK_HIGH_32BIT:
415       return "pick_high_32bit";
416    case VEC4_OPCODE_SET_LOW_32BIT:
417       return "set_low_32bit";
418    case VEC4_OPCODE_SET_HIGH_32BIT:
419       return "set_high_32bit";
420 
421    case FS_OPCODE_DDX_COARSE:
422       return "ddx_coarse";
423    case FS_OPCODE_DDX_FINE:
424       return "ddx_fine";
425    case FS_OPCODE_DDY_COARSE:
426       return "ddy_coarse";
427    case FS_OPCODE_DDY_FINE:
428       return "ddy_fine";
429 
430    case FS_OPCODE_LINTERP:
431       return "linterp";
432 
433    case FS_OPCODE_PIXEL_X:
434       return "pixel_x";
435    case FS_OPCODE_PIXEL_Y:
436       return "pixel_y";
437 
438    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
439       return "uniform_pull_const";
440    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
441       return "uniform_pull_const_gen7";
442    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
443       return "varying_pull_const_gen4";
444    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
445       return "varying_pull_const_logical";
446 
447    case FS_OPCODE_DISCARD_JUMP:
448       return "discard_jump";
449 
450    case FS_OPCODE_SET_SAMPLE_ID:
451       return "set_sample_id";
452 
453    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
454       return "pack_half_2x16_split";
455 
456    case FS_OPCODE_PLACEHOLDER_HALT:
457       return "placeholder_halt";
458 
459    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
460       return "interp_sample";
461    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
462       return "interp_shared_offset";
463    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
464       return "interp_per_slot_offset";
465 
466    case VS_OPCODE_URB_WRITE:
467       return "vs_urb_write";
468    case VS_OPCODE_PULL_CONSTANT_LOAD:
469       return "pull_constant_load";
470    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
471       return "pull_constant_load_gen7";
472 
473    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
474       return "unpack_flags_simd4x2";
475 
476    case GS_OPCODE_URB_WRITE:
477       return "gs_urb_write";
478    case GS_OPCODE_URB_WRITE_ALLOCATE:
479       return "gs_urb_write_allocate";
480    case GS_OPCODE_THREAD_END:
481       return "gs_thread_end";
482    case GS_OPCODE_SET_WRITE_OFFSET:
483       return "set_write_offset";
484    case GS_OPCODE_SET_VERTEX_COUNT:
485       return "set_vertex_count";
486    case GS_OPCODE_SET_DWORD_2:
487       return "set_dword_2";
488    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
489       return "prepare_channel_masks";
490    case GS_OPCODE_SET_CHANNEL_MASKS:
491       return "set_channel_masks";
492    case GS_OPCODE_GET_INSTANCE_ID:
493       return "get_instance_id";
494    case GS_OPCODE_FF_SYNC:
495       return "ff_sync";
496    case GS_OPCODE_SET_PRIMITIVE_ID:
497       return "set_primitive_id";
498    case GS_OPCODE_SVB_WRITE:
499       return "gs_svb_write";
500    case GS_OPCODE_SVB_SET_DST_INDEX:
501       return "gs_svb_set_dst_index";
502    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
503       return "gs_ff_sync_set_primitives";
504    case CS_OPCODE_CS_TERMINATE:
505       return "cs_terminate";
506    case SHADER_OPCODE_BARRIER:
507       return "barrier";
508    case SHADER_OPCODE_MULH:
509       return "mulh";
510    case SHADER_OPCODE_ISUB_SAT:
511       return "isub_sat";
512    case SHADER_OPCODE_USUB_SAT:
513       return "usub_sat";
514    case SHADER_OPCODE_MOV_INDIRECT:
515       return "mov_indirect";
516    case SHADER_OPCODE_MOV_RELOC_IMM:
517       return "mov_reloc_imm";
518 
519    case VEC4_OPCODE_URB_READ:
520       return "urb_read";
521    case TCS_OPCODE_GET_INSTANCE_ID:
522       return "tcs_get_instance_id";
523    case TCS_OPCODE_URB_WRITE:
524       return "tcs_urb_write";
525    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
526       return "tcs_set_input_urb_offsets";
527    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
528       return "tcs_set_output_urb_offsets";
529    case TCS_OPCODE_GET_PRIMITIVE_ID:
530       return "tcs_get_primitive_id";
531    case TCS_OPCODE_CREATE_BARRIER_HEADER:
532       return "tcs_create_barrier_header";
533    case TCS_OPCODE_SRC0_010_IS_ZERO:
534       return "tcs_src0<0,1,0>_is_zero";
535    case TCS_OPCODE_RELEASE_INPUT:
536       return "tcs_release_input";
537    case TCS_OPCODE_THREAD_END:
538       return "tcs_thread_end";
539    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
540       return "tes_create_input_read_header";
541    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
542       return "tes_add_indirect_urb_offset";
543    case TES_OPCODE_GET_PRIMITIVE_ID:
544       return "tes_get_primitive_id";
545 
546    case SHADER_OPCODE_RND_MODE:
547       return "rnd_mode";
548    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
549       return "float_control_mode";
550    }
551 
552    unreachable("not reached");
553 }
554 
555 bool
brw_saturate_immediate(enum brw_reg_type type,struct brw_reg * reg)556 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
557 {
558    union {
559       unsigned ud;
560       int d;
561       float f;
562       double df;
563    } imm, sat_imm = { 0 };
564 
565    const unsigned size = type_sz(type);
566 
567    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
568     * irrelevant, so just check the size of the type and copy from/to an
569     * appropriately sized field.
570     */
571    if (size < 8)
572       imm.ud = reg->ud;
573    else
574       imm.df = reg->df;
575 
576    switch (type) {
577    case BRW_REGISTER_TYPE_UD:
578    case BRW_REGISTER_TYPE_D:
579    case BRW_REGISTER_TYPE_UW:
580    case BRW_REGISTER_TYPE_W:
581    case BRW_REGISTER_TYPE_UQ:
582    case BRW_REGISTER_TYPE_Q:
583       /* Nothing to do. */
584       return false;
585    case BRW_REGISTER_TYPE_F:
586       sat_imm.f = SATURATE(imm.f);
587       break;
588    case BRW_REGISTER_TYPE_DF:
589       sat_imm.df = SATURATE(imm.df);
590       break;
591    case BRW_REGISTER_TYPE_UB:
592    case BRW_REGISTER_TYPE_B:
593       unreachable("no UB/B immediates");
594    case BRW_REGISTER_TYPE_V:
595    case BRW_REGISTER_TYPE_UV:
596    case BRW_REGISTER_TYPE_VF:
597       unreachable("unimplemented: saturate vector immediate");
598    case BRW_REGISTER_TYPE_HF:
599       unreachable("unimplemented: saturate HF immediate");
600    case BRW_REGISTER_TYPE_NF:
601       unreachable("no NF immediates");
602    }
603 
604    if (size < 8) {
605       if (imm.ud != sat_imm.ud) {
606          reg->ud = sat_imm.ud;
607          return true;
608       }
609    } else {
610       if (imm.df != sat_imm.df) {
611          reg->df = sat_imm.df;
612          return true;
613       }
614    }
615    return false;
616 }
617 
618 bool
brw_negate_immediate(enum brw_reg_type type,struct brw_reg * reg)619 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
620 {
621    switch (type) {
622    case BRW_REGISTER_TYPE_D:
623    case BRW_REGISTER_TYPE_UD:
624       reg->d = -reg->d;
625       return true;
626    case BRW_REGISTER_TYPE_W:
627    case BRW_REGISTER_TYPE_UW: {
628       uint16_t value = -(int16_t)reg->ud;
629       reg->ud = value | (uint32_t)value << 16;
630       return true;
631    }
632    case BRW_REGISTER_TYPE_F:
633       reg->f = -reg->f;
634       return true;
635    case BRW_REGISTER_TYPE_VF:
636       reg->ud ^= 0x80808080;
637       return true;
638    case BRW_REGISTER_TYPE_DF:
639       reg->df = -reg->df;
640       return true;
641    case BRW_REGISTER_TYPE_UQ:
642    case BRW_REGISTER_TYPE_Q:
643       reg->d64 = -reg->d64;
644       return true;
645    case BRW_REGISTER_TYPE_UB:
646    case BRW_REGISTER_TYPE_B:
647       unreachable("no UB/B immediates");
648    case BRW_REGISTER_TYPE_UV:
649    case BRW_REGISTER_TYPE_V:
650       assert(!"unimplemented: negate UV/V immediate");
651    case BRW_REGISTER_TYPE_HF:
652       reg->ud ^= 0x80008000;
653       return true;
654    case BRW_REGISTER_TYPE_NF:
655       unreachable("no NF immediates");
656    }
657 
658    return false;
659 }
660 
661 bool
brw_abs_immediate(enum brw_reg_type type,struct brw_reg * reg)662 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
663 {
664    switch (type) {
665    case BRW_REGISTER_TYPE_D:
666       reg->d = abs(reg->d);
667       return true;
668    case BRW_REGISTER_TYPE_W: {
669       uint16_t value = abs((int16_t)reg->ud);
670       reg->ud = value | (uint32_t)value << 16;
671       return true;
672    }
673    case BRW_REGISTER_TYPE_F:
674       reg->f = fabsf(reg->f);
675       return true;
676    case BRW_REGISTER_TYPE_DF:
677       reg->df = fabs(reg->df);
678       return true;
679    case BRW_REGISTER_TYPE_VF:
680       reg->ud &= ~0x80808080;
681       return true;
682    case BRW_REGISTER_TYPE_Q:
683       reg->d64 = imaxabs(reg->d64);
684       return true;
685    case BRW_REGISTER_TYPE_UB:
686    case BRW_REGISTER_TYPE_B:
687       unreachable("no UB/B immediates");
688    case BRW_REGISTER_TYPE_UQ:
689    case BRW_REGISTER_TYPE_UD:
690    case BRW_REGISTER_TYPE_UW:
691    case BRW_REGISTER_TYPE_UV:
692       /* Presumably the absolute value modifier on an unsigned source is a
693        * nop, but it would be nice to confirm.
694        */
695       assert(!"unimplemented: abs unsigned immediate");
696    case BRW_REGISTER_TYPE_V:
697       assert(!"unimplemented: abs V immediate");
698    case BRW_REGISTER_TYPE_HF:
699       reg->ud &= ~0x80008000;
700       return true;
701    case BRW_REGISTER_TYPE_NF:
702       unreachable("no NF immediates");
703    }
704 
705    return false;
706 }
707 
backend_shader(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const nir_shader * shader,struct brw_stage_prog_data * stage_prog_data)708 backend_shader::backend_shader(const struct brw_compiler *compiler,
709                                void *log_data,
710                                void *mem_ctx,
711                                const nir_shader *shader,
712                                struct brw_stage_prog_data *stage_prog_data)
713    : compiler(compiler),
714      log_data(log_data),
715      devinfo(compiler->devinfo),
716      nir(shader),
717      stage_prog_data(stage_prog_data),
718      mem_ctx(mem_ctx),
719      cfg(NULL), idom_analysis(this),
720      stage(shader->info.stage)
721 {
722    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
723    stage_name = _mesa_shader_stage_to_string(stage);
724    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
725 }
726 
~backend_shader()727 backend_shader::~backend_shader()
728 {
729 }
730 
731 bool
equals(const backend_reg & r) const732 backend_reg::equals(const backend_reg &r) const
733 {
734    return brw_regs_equal(this, &r) && offset == r.offset;
735 }
736 
737 bool
negative_equals(const backend_reg & r) const738 backend_reg::negative_equals(const backend_reg &r) const
739 {
740    return brw_regs_negative_equal(this, &r) && offset == r.offset;
741 }
742 
743 bool
is_zero() const744 backend_reg::is_zero() const
745 {
746    if (file != IMM)
747       return false;
748 
749    assert(type_sz(type) > 1);
750 
751    switch (type) {
752    case BRW_REGISTER_TYPE_HF:
753       assert((d & 0xffff) == ((d >> 16) & 0xffff));
754       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
755    case BRW_REGISTER_TYPE_F:
756       return f == 0;
757    case BRW_REGISTER_TYPE_DF:
758       return df == 0;
759    case BRW_REGISTER_TYPE_W:
760    case BRW_REGISTER_TYPE_UW:
761       assert((d & 0xffff) == ((d >> 16) & 0xffff));
762       return (d & 0xffff) == 0;
763    case BRW_REGISTER_TYPE_D:
764    case BRW_REGISTER_TYPE_UD:
765       return d == 0;
766    case BRW_REGISTER_TYPE_UQ:
767    case BRW_REGISTER_TYPE_Q:
768       return u64 == 0;
769    default:
770       return false;
771    }
772 }
773 
774 bool
is_one() const775 backend_reg::is_one() const
776 {
777    if (file != IMM)
778       return false;
779 
780    assert(type_sz(type) > 1);
781 
782    switch (type) {
783    case BRW_REGISTER_TYPE_HF:
784       assert((d & 0xffff) == ((d >> 16) & 0xffff));
785       return (d & 0xffff) == 0x3c00;
786    case BRW_REGISTER_TYPE_F:
787       return f == 1.0f;
788    case BRW_REGISTER_TYPE_DF:
789       return df == 1.0;
790    case BRW_REGISTER_TYPE_W:
791    case BRW_REGISTER_TYPE_UW:
792       assert((d & 0xffff) == ((d >> 16) & 0xffff));
793       return (d & 0xffff) == 1;
794    case BRW_REGISTER_TYPE_D:
795    case BRW_REGISTER_TYPE_UD:
796       return d == 1;
797    case BRW_REGISTER_TYPE_UQ:
798    case BRW_REGISTER_TYPE_Q:
799       return u64 == 1;
800    default:
801       return false;
802    }
803 }
804 
805 bool
is_negative_one() const806 backend_reg::is_negative_one() const
807 {
808    if (file != IMM)
809       return false;
810 
811    assert(type_sz(type) > 1);
812 
813    switch (type) {
814    case BRW_REGISTER_TYPE_HF:
815       assert((d & 0xffff) == ((d >> 16) & 0xffff));
816       return (d & 0xffff) == 0xbc00;
817    case BRW_REGISTER_TYPE_F:
818       return f == -1.0;
819    case BRW_REGISTER_TYPE_DF:
820       return df == -1.0;
821    case BRW_REGISTER_TYPE_W:
822       assert((d & 0xffff) == ((d >> 16) & 0xffff));
823       return (d & 0xffff) == 0xffff;
824    case BRW_REGISTER_TYPE_D:
825       return d == -1;
826    case BRW_REGISTER_TYPE_Q:
827       return d64 == -1;
828    default:
829       return false;
830    }
831 }
832 
833 bool
is_null() const834 backend_reg::is_null() const
835 {
836    return file == ARF && nr == BRW_ARF_NULL;
837 }
838 
839 
840 bool
is_accumulator() const841 backend_reg::is_accumulator() const
842 {
843    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
844 }
845 
846 bool
is_commutative() const847 backend_instruction::is_commutative() const
848 {
849    switch (opcode) {
850    case BRW_OPCODE_AND:
851    case BRW_OPCODE_OR:
852    case BRW_OPCODE_XOR:
853    case BRW_OPCODE_ADD:
854    case BRW_OPCODE_MUL:
855    case SHADER_OPCODE_MULH:
856       return true;
857    case BRW_OPCODE_SEL:
858       /* MIN and MAX are commutative. */
859       if (conditional_mod == BRW_CONDITIONAL_GE ||
860           conditional_mod == BRW_CONDITIONAL_L) {
861          return true;
862       }
863       /* fallthrough */
864    default:
865       return false;
866    }
867 }
868 
869 bool
is_3src(const struct gen_device_info * devinfo) const870 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
871 {
872    return ::is_3src(devinfo, opcode);
873 }
874 
875 bool
is_tex() const876 backend_instruction::is_tex() const
877 {
878    return (opcode == SHADER_OPCODE_TEX ||
879            opcode == FS_OPCODE_TXB ||
880            opcode == SHADER_OPCODE_TXD ||
881            opcode == SHADER_OPCODE_TXF ||
882            opcode == SHADER_OPCODE_TXF_LZ ||
883            opcode == SHADER_OPCODE_TXF_CMS ||
884            opcode == SHADER_OPCODE_TXF_CMS_W ||
885            opcode == SHADER_OPCODE_TXF_UMS ||
886            opcode == SHADER_OPCODE_TXF_MCS ||
887            opcode == SHADER_OPCODE_TXL ||
888            opcode == SHADER_OPCODE_TXL_LZ ||
889            opcode == SHADER_OPCODE_TXS ||
890            opcode == SHADER_OPCODE_LOD ||
891            opcode == SHADER_OPCODE_TG4 ||
892            opcode == SHADER_OPCODE_TG4_OFFSET ||
893            opcode == SHADER_OPCODE_SAMPLEINFO);
894 }
895 
896 bool
is_math() const897 backend_instruction::is_math() const
898 {
899    return (opcode == SHADER_OPCODE_RCP ||
900            opcode == SHADER_OPCODE_RSQ ||
901            opcode == SHADER_OPCODE_SQRT ||
902            opcode == SHADER_OPCODE_EXP2 ||
903            opcode == SHADER_OPCODE_LOG2 ||
904            opcode == SHADER_OPCODE_SIN ||
905            opcode == SHADER_OPCODE_COS ||
906            opcode == SHADER_OPCODE_INT_QUOTIENT ||
907            opcode == SHADER_OPCODE_INT_REMAINDER ||
908            opcode == SHADER_OPCODE_POW);
909 }
910 
911 bool
is_control_flow() const912 backend_instruction::is_control_flow() const
913 {
914    switch (opcode) {
915    case BRW_OPCODE_DO:
916    case BRW_OPCODE_WHILE:
917    case BRW_OPCODE_IF:
918    case BRW_OPCODE_ELSE:
919    case BRW_OPCODE_ENDIF:
920    case BRW_OPCODE_BREAK:
921    case BRW_OPCODE_CONTINUE:
922       return true;
923    default:
924       return false;
925    }
926 }
927 
928 bool
can_do_source_mods() const929 backend_instruction::can_do_source_mods() const
930 {
931    switch (opcode) {
932    case BRW_OPCODE_ADDC:
933    case BRW_OPCODE_BFE:
934    case BRW_OPCODE_BFI1:
935    case BRW_OPCODE_BFI2:
936    case BRW_OPCODE_BFREV:
937    case BRW_OPCODE_CBIT:
938    case BRW_OPCODE_FBH:
939    case BRW_OPCODE_FBL:
940    case BRW_OPCODE_ROL:
941    case BRW_OPCODE_ROR:
942    case BRW_OPCODE_SUBB:
943    case SHADER_OPCODE_BROADCAST:
944    case SHADER_OPCODE_CLUSTER_BROADCAST:
945    case SHADER_OPCODE_MOV_INDIRECT:
946       return false;
947    default:
948       return true;
949    }
950 }
951 
952 bool
can_do_saturate() const953 backend_instruction::can_do_saturate() const
954 {
955    switch (opcode) {
956    case BRW_OPCODE_ADD:
957    case BRW_OPCODE_ASR:
958    case BRW_OPCODE_AVG:
959    case BRW_OPCODE_CSEL:
960    case BRW_OPCODE_DP2:
961    case BRW_OPCODE_DP3:
962    case BRW_OPCODE_DP4:
963    case BRW_OPCODE_DPH:
964    case BRW_OPCODE_F16TO32:
965    case BRW_OPCODE_F32TO16:
966    case BRW_OPCODE_LINE:
967    case BRW_OPCODE_LRP:
968    case BRW_OPCODE_MAC:
969    case BRW_OPCODE_MAD:
970    case BRW_OPCODE_MATH:
971    case BRW_OPCODE_MOV:
972    case BRW_OPCODE_MUL:
973    case SHADER_OPCODE_MULH:
974    case BRW_OPCODE_PLN:
975    case BRW_OPCODE_RNDD:
976    case BRW_OPCODE_RNDE:
977    case BRW_OPCODE_RNDU:
978    case BRW_OPCODE_RNDZ:
979    case BRW_OPCODE_SEL:
980    case BRW_OPCODE_SHL:
981    case BRW_OPCODE_SHR:
982    case FS_OPCODE_LINTERP:
983    case SHADER_OPCODE_COS:
984    case SHADER_OPCODE_EXP2:
985    case SHADER_OPCODE_LOG2:
986    case SHADER_OPCODE_POW:
987    case SHADER_OPCODE_RCP:
988    case SHADER_OPCODE_RSQ:
989    case SHADER_OPCODE_SIN:
990    case SHADER_OPCODE_SQRT:
991       return true;
992    default:
993       return false;
994    }
995 }
996 
997 bool
can_do_cmod() const998 backend_instruction::can_do_cmod() const
999 {
1000    switch (opcode) {
1001    case BRW_OPCODE_ADD:
1002    case BRW_OPCODE_ADDC:
1003    case BRW_OPCODE_AND:
1004    case BRW_OPCODE_ASR:
1005    case BRW_OPCODE_AVG:
1006    case BRW_OPCODE_CMP:
1007    case BRW_OPCODE_CMPN:
1008    case BRW_OPCODE_DP2:
1009    case BRW_OPCODE_DP3:
1010    case BRW_OPCODE_DP4:
1011    case BRW_OPCODE_DPH:
1012    case BRW_OPCODE_F16TO32:
1013    case BRW_OPCODE_F32TO16:
1014    case BRW_OPCODE_FRC:
1015    case BRW_OPCODE_LINE:
1016    case BRW_OPCODE_LRP:
1017    case BRW_OPCODE_LZD:
1018    case BRW_OPCODE_MAC:
1019    case BRW_OPCODE_MACH:
1020    case BRW_OPCODE_MAD:
1021    case BRW_OPCODE_MOV:
1022    case BRW_OPCODE_MUL:
1023    case BRW_OPCODE_NOT:
1024    case BRW_OPCODE_OR:
1025    case BRW_OPCODE_PLN:
1026    case BRW_OPCODE_RNDD:
1027    case BRW_OPCODE_RNDE:
1028    case BRW_OPCODE_RNDU:
1029    case BRW_OPCODE_RNDZ:
1030    case BRW_OPCODE_SAD2:
1031    case BRW_OPCODE_SADA2:
1032    case BRW_OPCODE_SHL:
1033    case BRW_OPCODE_SHR:
1034    case BRW_OPCODE_SUBB:
1035    case BRW_OPCODE_XOR:
1036    case FS_OPCODE_LINTERP:
1037       return true;
1038    default:
1039       return false;
1040    }
1041 }
1042 
1043 bool
reads_accumulator_implicitly() const1044 backend_instruction::reads_accumulator_implicitly() const
1045 {
1046    switch (opcode) {
1047    case BRW_OPCODE_MAC:
1048    case BRW_OPCODE_MACH:
1049    case BRW_OPCODE_SADA2:
1050       return true;
1051    default:
1052       return false;
1053    }
1054 }
1055 
1056 bool
writes_accumulator_implicitly(const struct gen_device_info * devinfo) const1057 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1058 {
1059    return writes_accumulator ||
1060           (devinfo->gen < 6 &&
1061            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1062             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1063           (opcode == FS_OPCODE_LINTERP &&
1064            (!devinfo->has_pln || devinfo->gen <= 6));
1065 }
1066 
1067 bool
has_side_effects() const1068 backend_instruction::has_side_effects() const
1069 {
1070    switch (opcode) {
1071    case SHADER_OPCODE_SEND:
1072       return send_has_side_effects;
1073 
1074    case BRW_OPCODE_SYNC:
1075    case VEC4_OPCODE_UNTYPED_ATOMIC:
1076    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1077    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1078    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1079    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1080    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1081    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1082    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1083    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1084    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1085    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1086    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1087    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1088    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1089    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1090    case SHADER_OPCODE_MEMORY_FENCE:
1091    case SHADER_OPCODE_INTERLOCK:
1092    case SHADER_OPCODE_URB_WRITE_SIMD8:
1093    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1094    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1095    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1096    case FS_OPCODE_FB_WRITE:
1097    case FS_OPCODE_FB_WRITE_LOGICAL:
1098    case FS_OPCODE_REP_FB_WRITE:
1099    case SHADER_OPCODE_BARRIER:
1100    case TCS_OPCODE_URB_WRITE:
1101    case TCS_OPCODE_RELEASE_INPUT:
1102    case SHADER_OPCODE_RND_MODE:
1103    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1104    case FS_OPCODE_SCHEDULING_FENCE:
1105    case SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
1106    case SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
1107       return true;
1108    default:
1109       return eot;
1110    }
1111 }
1112 
1113 bool
is_volatile() const1114 backend_instruction::is_volatile() const
1115 {
1116    switch (opcode) {
1117    case SHADER_OPCODE_SEND:
1118       return send_is_volatile;
1119 
1120    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1121    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1122    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1123    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1124    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1125    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1126    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1127    case SHADER_OPCODE_URB_READ_SIMD8:
1128    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1129    case VEC4_OPCODE_URB_READ:
1130       return true;
1131    default:
1132       return false;
1133    }
1134 }
1135 
1136 #ifndef NDEBUG
1137 static bool
inst_is_in_block(const bblock_t * block,const backend_instruction * inst)1138 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1139 {
1140    bool found = false;
1141    foreach_inst_in_block (backend_instruction, i, block) {
1142       if (inst == i) {
1143          found = true;
1144       }
1145    }
1146    return found;
1147 }
1148 #endif
1149 
1150 static void
adjust_later_block_ips(bblock_t * start_block,int ip_adjustment)1151 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1152 {
1153    for (bblock_t *block_iter = start_block->next();
1154         block_iter;
1155         block_iter = block_iter->next()) {
1156       block_iter->start_ip += ip_adjustment;
1157       block_iter->end_ip += ip_adjustment;
1158    }
1159 }
1160 
1161 void
insert_after(bblock_t * block,backend_instruction * inst)1162 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1163 {
1164    assert(this != inst);
1165 
1166    if (!this->is_head_sentinel())
1167       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1168 
1169    block->end_ip++;
1170 
1171    adjust_later_block_ips(block, 1);
1172 
1173    exec_node::insert_after(inst);
1174 }
1175 
1176 void
insert_before(bblock_t * block,backend_instruction * inst)1177 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1178 {
1179    assert(this != inst);
1180 
1181    if (!this->is_tail_sentinel())
1182       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1183 
1184    block->end_ip++;
1185 
1186    adjust_later_block_ips(block, 1);
1187 
1188    exec_node::insert_before(inst);
1189 }
1190 
1191 void
insert_before(bblock_t * block,exec_list * list)1192 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1193 {
1194    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1195 
1196    unsigned num_inst = list->length();
1197 
1198    block->end_ip += num_inst;
1199 
1200    adjust_later_block_ips(block, num_inst);
1201 
1202    exec_node::insert_before(list);
1203 }
1204 
1205 void
remove(bblock_t * block)1206 backend_instruction::remove(bblock_t *block)
1207 {
1208    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1209 
1210    adjust_later_block_ips(block, -1);
1211 
1212    if (block->start_ip == block->end_ip) {
1213       block->cfg->remove_block(block);
1214    } else {
1215       block->end_ip--;
1216    }
1217 
1218    exec_node::remove();
1219 }
1220 
1221 void
dump_instructions() const1222 backend_shader::dump_instructions() const
1223 {
1224    dump_instructions(NULL);
1225 }
1226 
1227 void
dump_instructions(const char * name) const1228 backend_shader::dump_instructions(const char *name) const
1229 {
1230    FILE *file = stderr;
1231    if (name && geteuid() != 0) {
1232       file = fopen(name, "w");
1233       if (!file)
1234          file = stderr;
1235    }
1236 
1237    if (cfg) {
1238       int ip = 0;
1239       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1240          if (!(INTEL_DEBUG & DEBUG_OPTIMIZER))
1241             fprintf(file, "%4d: ", ip++);
1242          dump_instruction(inst, file);
1243       }
1244    } else {
1245       int ip = 0;
1246       foreach_in_list(backend_instruction, inst, &instructions) {
1247          if (!(INTEL_DEBUG & DEBUG_OPTIMIZER))
1248             fprintf(file, "%4d: ", ip++);
1249          dump_instruction(inst, file);
1250       }
1251    }
1252 
1253    if (file != stderr) {
1254       fclose(file);
1255    }
1256 }
1257 
1258 void
calculate_cfg()1259 backend_shader::calculate_cfg()
1260 {
1261    if (this->cfg)
1262       return;
1263    cfg = new(mem_ctx) cfg_t(this, &this->instructions);
1264 }
1265 
1266 void
invalidate_analysis(brw::analysis_dependency_class c)1267 backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
1268 {
1269    idom_analysis.invalidate(c);
1270 }
1271 
1272 extern "C" const unsigned *
brw_compile_tes(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const struct brw_tes_prog_key * key,const struct brw_vue_map * input_vue_map,struct brw_tes_prog_data * prog_data,nir_shader * nir,int shader_time_index,struct brw_compile_stats * stats,char ** error_str)1273 brw_compile_tes(const struct brw_compiler *compiler,
1274                 void *log_data,
1275                 void *mem_ctx,
1276                 const struct brw_tes_prog_key *key,
1277                 const struct brw_vue_map *input_vue_map,
1278                 struct brw_tes_prog_data *prog_data,
1279                 nir_shader *nir,
1280                 int shader_time_index,
1281                 struct brw_compile_stats *stats,
1282                 char **error_str)
1283 {
1284    const struct gen_device_info *devinfo = compiler->devinfo;
1285    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1286    const unsigned *assembly;
1287 
1288    nir->info.inputs_read = key->inputs_read;
1289    nir->info.patch_inputs_read = key->patch_inputs_read;
1290 
1291    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1292    brw_nir_lower_tes_inputs(nir, input_vue_map);
1293    brw_nir_lower_vue_outputs(nir);
1294    brw_postprocess_nir(nir, compiler, is_scalar);
1295 
1296    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1297                        nir->info.outputs_written,
1298                        nir->info.separate_shader, 1);
1299 
1300    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1301 
1302    assert(output_size_bytes >= 1);
1303    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1304       if (error_str)
1305          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1306       return NULL;
1307    }
1308 
1309    prog_data->base.clip_distance_mask =
1310       ((1 << nir->info.clip_distance_array_size) - 1);
1311    prog_data->base.cull_distance_mask =
1312       ((1 << nir->info.cull_distance_array_size) - 1) <<
1313       nir->info.clip_distance_array_size;
1314 
1315    /* URB entry sizes are stored as a multiple of 64 bytes. */
1316    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1317 
1318    prog_data->base.urb_read_length = 0;
1319 
1320    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1321    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1322                  TESS_SPACING_FRACTIONAL_ODD - 1);
1323    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1324                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1325 
1326    prog_data->partitioning =
1327       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1328 
1329    switch (nir->info.tess.primitive_mode) {
1330    case GL_QUADS:
1331       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1332       break;
1333    case GL_TRIANGLES:
1334       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1335       break;
1336    case GL_ISOLINES:
1337       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1338       break;
1339    default:
1340       unreachable("invalid domain shader primitive mode");
1341    }
1342 
1343    if (nir->info.tess.point_mode) {
1344       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1345    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1346       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1347    } else {
1348       /* Hardware winding order is backwards from OpenGL */
1349       prog_data->output_topology =
1350          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1351                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1352    }
1353 
1354    if (INTEL_DEBUG & DEBUG_TES) {
1355       fprintf(stderr, "TES Input ");
1356       brw_print_vue_map(stderr, input_vue_map);
1357       fprintf(stderr, "TES Output ");
1358       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1359    }
1360 
1361    if (is_scalar) {
1362       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1363                    &prog_data->base.base, nir, 8,
1364                    shader_time_index, input_vue_map);
1365       if (!v.run_tes()) {
1366          if (error_str)
1367             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1368          return NULL;
1369       }
1370 
1371       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1372       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1373 
1374       fs_generator g(compiler, log_data, mem_ctx,
1375                      &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
1376       if (INTEL_DEBUG & DEBUG_TES) {
1377          g.enable_debug(ralloc_asprintf(mem_ctx,
1378                                         "%s tessellation evaluation shader %s",
1379                                         nir->info.label ? nir->info.label
1380                                                         : "unnamed",
1381                                         nir->info.name));
1382       }
1383 
1384       g.generate_code(v.cfg, 8, v.shader_stats,
1385                       v.performance_analysis.require(), stats);
1386 
1387       g.add_const_data(nir->constant_data, nir->constant_data_size);
1388 
1389       assembly = g.get_assembly();
1390    } else {
1391       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1392 			      nir, mem_ctx, shader_time_index);
1393       if (!v.run()) {
1394 	 if (error_str)
1395 	    *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1396 	 return NULL;
1397       }
1398 
1399       if (INTEL_DEBUG & DEBUG_TES)
1400 	 v.dump_instructions();
1401 
1402       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1403                                             &prog_data->base, v.cfg,
1404                                             v.performance_analysis.require(),
1405                                             stats);
1406    }
1407 
1408    return assembly;
1409 }
1410