1  /*
2   * Copyright © 2013 Intel Corporation
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice (including the next
12   * paragraph) shall be included in all copies or substantial portions of the
13   * Software.
14   *
15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21   * IN THE SOFTWARE.
22   *
23   */
24 
25 #ifndef GEN_DEVICE_INFO_H
26 #define GEN_DEVICE_INFO_H
27 
28 #include <stdbool.h>
29 #include <stdint.h>
30 
31 #include "util/macros.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 struct drm_i915_query_topology_info;
38 
39 #define GEN_DEVICE_MAX_SLICES           (6)  /* Maximum on gen10 */
40 #define GEN_DEVICE_MAX_SUBSLICES        (8)  /* Maximum on gen11 */
41 #define GEN_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gen12 */
42 #define GEN_DEVICE_MAX_PIXEL_PIPES      (2)  /* Maximum on gen11 */
43 
44 /**
45  * Intel hardware information and quirks
46  */
47 struct gen_device_info
48 {
49    int gen; /**< Generation number: 4, 5, 6, 7, ... */
50    int revision;
51    int gt;
52 
53    bool is_g4x;
54    bool is_ivybridge;
55    bool is_baytrail;
56    bool is_haswell;
57    bool is_broadwell;
58    bool is_cherryview;
59    bool is_skylake;
60    bool is_broxton;
61    bool is_kabylake;
62    bool is_geminilake;
63    bool is_coffeelake;
64    bool is_elkhartlake;
65    bool is_dg1;
66 
67    bool has_hiz_and_separate_stencil;
68    bool must_use_separate_stencil;
69    bool has_sample_with_hiz;
70    bool has_llc;
71 
72    bool has_pln;
73    bool has_64bit_float;
74    bool has_64bit_int;
75    bool has_integer_dword_mul;
76    bool has_compr4;
77    bool has_surface_tile_offset;
78    bool supports_simd16_3src;
79    bool has_resource_streamer;
80    bool disable_ccs_repack;
81    bool has_aux_map;
82    bool has_tiling_uapi;
83 
84    /**
85     * \name Intel hardware quirks
86     *  @{
87     */
88    bool has_negative_rhw_bug;
89 
90    /**
91     * Some versions of Gen hardware don't do centroid interpolation correctly
92     * on unlit pixels, causing incorrect values for derivatives near triangle
93     * edges.  Enabling this flag causes the fragment shader to use
94     * non-centroid interpolation for unlit pixels, at the expense of two extra
95     * fragment shader instructions.
96     */
97    bool needs_unlit_centroid_workaround;
98    /** @} */
99 
100    /**
101     * \name GPU hardware limits
102     *
103     * In general, you can find shader thread maximums by looking at the "Maximum
104     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
105     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
106     * limits come from the "Number of URB Entries" field in the
107     * 3DSTATE_URB_VS command and friends.
108     *
109     * These fields are used to calculate the scratch space to allocate.  The
110     * amount of scratch space can be larger without being harmful on modern
111     * GPUs, however, prior to Haswell, programming the maximum number of threads
112     * to greater than the hardware maximum would cause GPU performance to tank.
113     *
114     *  @{
115     */
116    /**
117     * Total number of slices present on the device whether or not they've been
118     * fused off.
119     *
120     * XXX: CS thread counts are limited by the inability to do cross subslice
121     * communication. It is the effectively the number of logical threads which
122     * can be executed in a subslice. Fuse configurations may cause this number
123     * to change, so we program @max_cs_threads as the lower maximum.
124     */
125    unsigned num_slices;
126 
127    /**
128     * Number of subslices for each slice (used to be uniform until CNL).
129     */
130    unsigned num_subslices[GEN_DEVICE_MAX_SUBSLICES];
131 
132    /**
133     * Number of subslices on each pixel pipe (ICL).
134     */
135    unsigned ppipe_subslices[GEN_DEVICE_MAX_PIXEL_PIPES];
136 
137    /**
138     * Upper bound of number of EU per subslice (some SKUs might have just 1 EU
139     * fused across all subslices, like 47 EUs, in which case this number won't
140     * be acurate for one subslice).
141     */
142    unsigned num_eu_per_subslice;
143 
144    /**
145     * Number of threads per eu, varies between 4 and 8 between generations.
146     */
147    unsigned num_thread_per_eu;
148 
149    /**
150     * A bit mask of the slices available.
151     */
152    uint8_t slice_masks;
153 
154    /**
155     * An array of bit mask of the subslices available, use subslice_slice_stride
156     * to access this array.
157     */
158    uint8_t subslice_masks[GEN_DEVICE_MAX_SLICES *
159                           DIV_ROUND_UP(GEN_DEVICE_MAX_SUBSLICES, 8)];
160 
161    /**
162     * An array of bit mask of EUs available, use eu_slice_stride &
163     * eu_subslice_stride to access this array.
164     */
165    uint8_t eu_masks[GEN_DEVICE_MAX_SLICES *
166                     GEN_DEVICE_MAX_SUBSLICES *
167                     DIV_ROUND_UP(GEN_DEVICE_MAX_EUS_PER_SUBSLICE, 8)];
168 
169    /**
170     * Stride to access subslice_masks[].
171     */
172    uint16_t subslice_slice_stride;
173 
174    /**
175     * Strides to access eu_masks[].
176     */
177    uint16_t eu_slice_stride;
178    uint16_t eu_subslice_stride;
179 
180    unsigned l3_banks;
181    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
182    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
183    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
184    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
185    /**
186     * Theoretical maximum number of Pixel Shader threads.
187     *
188     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
189     * automatically scale pixel shader thread count, based on a single value
190     * programmed into 3DSTATE_PS.
191     *
192     * To calculate the maximum number of threads for Gen8 beyond (which have
193     * multiple Pixel Shader Dispatchers):
194     *
195     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
196     * - Usually there's only one PSD per subslice, so use the number of
197     *   subslices for number of PSDs.
198     * - For max_wm_threads, the total should be PSD threads * #PSDs.
199     */
200    unsigned max_wm_threads;
201 
202    /**
203     * Maximum Compute Shader threads.
204     *
205     * Thread count * number of EUs per subslice
206     */
207    unsigned max_cs_threads;
208 
209    struct {
210       /**
211        * Fixed size of the URB.
212        *
213        * On Gen6 and DG1, this is measured in KB.  Gen4-5 instead measure
214        * this in 512b blocks, as that's more convenient there.
215        *
216        * On most Gen7+ platforms, the URB is a section of the L3 cache,
217        * and can be resized based on the L3 programming.  For those platforms,
218        * simply leave this field blank (zero) - it isn't used.
219        */
220       unsigned size;
221 
222       /**
223        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
224        */
225       unsigned min_entries[4];
226 
227       /**
228        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
229        */
230       unsigned max_entries[4];
231    } urb;
232 
233    /**
234     * For the longest time the timestamp frequency for Gen's timestamp counter
235     * could be assumed to be 12.5MHz, where the least significant bit neatly
236     * corresponded to 80 nanoseconds.
237     *
238     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
239     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
240     * BXT.
241     *
242     * For simplicty to fit with the current code scaling by a single constant
243     * to map from raw timestamps to nanoseconds we now do the conversion in
244     * floating point instead of integer arithmetic.
245     *
246     * In general it's probably worth noting that the documented constants we
247     * have for the per-platform timestamp frequencies aren't perfect and
248     * shouldn't be trusted for scaling and comparing timestamps with a large
249     * delta.
250     *
251     * E.g. with crude testing on my system using the 'correct' scale factor I'm
252     * seeing a drift of ~2 milliseconds per second.
253     */
254    uint64_t timestamp_frequency;
255 
256    uint64_t aperture_bytes;
257 
258    /**
259     * ID to put into the .aub files.
260     */
261    int simulator_id;
262 
263    /**
264     * holds the pci device id
265     */
266    uint32_t chipset_id;
267 
268    /**
269     * no_hw is true when the chipset_id pci device id has been overridden
270     */
271    bool no_hw;
272    /** @} */
273 };
274 
275 #define gen_device_info_is_9lp(devinfo) \
276    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
277 
278 static inline bool
gen_device_info_subslice_available(const struct gen_device_info * devinfo,int slice,int subslice)279 gen_device_info_subslice_available(const struct gen_device_info *devinfo,
280                                    int slice, int subslice)
281 {
282    return (devinfo->subslice_masks[slice * devinfo->subslice_slice_stride +
283                                    subslice / 8] & (1U << (subslice % 8))) != 0;
284 }
285 
286 static inline bool
gen_device_info_eu_available(const struct gen_device_info * devinfo,int slice,int subslice,int eu)287 gen_device_info_eu_available(const struct gen_device_info *devinfo,
288                              int slice, int subslice, int eu)
289 {
290    unsigned subslice_offset = slice * devinfo->eu_slice_stride +
291       subslice * devinfo->eu_subslice_stride;
292 
293    return (devinfo->eu_masks[subslice_offset + eu / 8] & (1U << eu % 8)) != 0;
294 }
295 
296 int gen_device_name_to_pci_device_id(const char *name);
297 const char *gen_get_device_name(int devid);
298 
299 static inline uint64_t
gen_device_info_timebase_scale(const struct gen_device_info * devinfo,uint64_t gpu_timestamp)300 gen_device_info_timebase_scale(const struct gen_device_info *devinfo,
301                                uint64_t gpu_timestamp)
302 {
303    return (1000000000ull * gpu_timestamp) / devinfo->timestamp_frequency;
304 }
305 
306 bool gen_get_device_info_from_fd(int fh, struct gen_device_info *devinfo);
307 bool gen_get_device_info_from_pci_id(int pci_id,
308                                      struct gen_device_info *devinfo);
309 int gen_get_aperture_size(int fd, uint64_t *size);
310 
311 #ifdef __cplusplus
312 }
313 #endif
314 
315 #endif /* GEN_DEVICE_INFO_H */
316